blob: 6d24f568da293faccf8fe81b4f7e1c169c8418af [file] [log] [blame]
Uwe Hermanndf323fc2010-11-25 09:03:55 +00001/*
2 * This file is part of the coreboot project.
3 *
Uwe Hermann42b1c432010-12-09 18:09:14 +00004 * Copyright (C) 2004 Tyan Computer
5 * Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer.
6 * Copyright (C) 2006,2007 AMD
7 * Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
Uwe Hermanndf323fc2010-11-25 09:03:55 +00008 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
Uwe Hermanndf323fc2010-11-25 09:03:55 +000018 */
19
Uwe Hermann42b1c432010-12-09 18:09:14 +000020#include <stdint.h>
21#include <arch/io.h>
Uwe Hermann42b1c432010-12-09 18:09:14 +000022#include "mcp55.h"
23
24static void mcp55_enable_rom(void)
25{
Uwe Hermannc7f0c8f2011-01-04 19:51:33 +000026 u8 byte;
27 u16 word;
Edward O'Callaghan9a817ef2014-10-26 10:12:15 +110028 pci_devfn_t addr;
Uwe Hermann42b1c432010-12-09 18:09:14 +000029
Uwe Hermannc7f0c8f2011-01-04 19:51:33 +000030 /* Enable 4MB ROM access at 0xFFC00000 - 0xFFFFFFFF. */
Elyes HAOUAS49a7c372016-10-05 22:17:30 +020031
Uwe Hermannc7f0c8f2011-01-04 19:51:33 +000032 addr = PCI_DEV(0, (MCP55_DEVN_BASE + 1), 0);
Uwe Hermann42b1c432010-12-09 18:09:14 +000033
Uwe Hermannc7f0c8f2011-01-04 19:51:33 +000034 /* Set the 15MB enable bits. */
Uwe Hermann42b1c432010-12-09 18:09:14 +000035 byte = pci_read_config8(addr, 0x88);
Uwe Hermannc7f0c8f2011-01-04 19:51:33 +000036 byte |= 0xff; /* 256K */
Uwe Hermann42b1c432010-12-09 18:09:14 +000037 pci_write_config8(addr, 0x88, byte);
38 byte = pci_read_config8(addr, 0x8c);
Uwe Hermannc7f0c8f2011-01-04 19:51:33 +000039 byte |= 0xff; /* 1M */
Uwe Hermann42b1c432010-12-09 18:09:14 +000040 pci_write_config8(addr, 0x8c, byte);
41 word = pci_read_config16(addr, 0x90);
Uwe Hermannc7f0c8f2011-01-04 19:51:33 +000042 word |= 0x7fff; /* 15M */
Uwe Hermann42b1c432010-12-09 18:09:14 +000043 pci_write_config16(addr, 0x90, word);
44}
Uwe Hermanndf323fc2010-11-25 09:03:55 +000045
46static void bootblock_southbridge_init(void)
47{
48 mcp55_enable_rom();
49}