Lee Leahy | d4edacb | 2016-02-08 07:12:30 -0800 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2014 Google Inc. |
| 5 | * Copyright (C) 2015-2016 Intel Corporation. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | */ |
| 16 | |
Lee Leahy | 14d0926 | 2016-07-21 09:17:10 -0700 | [diff] [blame] | 17 | #include <assert.h> |
Lee Leahy | d4edacb | 2016-02-08 07:12:30 -0800 | [diff] [blame] | 18 | #include <console/console.h> |
Lee Leahy | b457649 | 2016-02-14 14:33:45 -0800 | [diff] [blame] | 19 | #include <device/device.h> |
Brandon Breitenstein | c6ec8dd | 2016-11-17 12:23:04 -0800 | [diff] [blame] | 20 | #include <romstage_handoff.h> |
Lee Leahy | 535333d | 2016-02-14 15:10:35 -0800 | [diff] [blame] | 21 | #include <soc/ramstage.h> |
Lee Leahy | 63e3dff | 2016-04-30 08:48:52 -0700 | [diff] [blame] | 22 | #include <soc/reg_access.h> |
| 23 | |
| 24 | /* Cat Trip Clear value must be less than Cat Trip Set value */ |
| 25 | #define PLATFORM_CATASTROPHIC_TRIP_CELSIUS 105 |
| 26 | #define PLATFORM_CATASTROPHIC_CLEAR_CELSIUS 65 |
| 27 | |
| 28 | static const struct reg_script thermal_init_script[] = { |
| 29 | |
| 30 | /* Setup RMU Thermal sensor registers for Ratiometric mode. */ |
| 31 | REG_SOC_UNIT_RMW(QUARK_SCSS_SOC_UNIT_TSCGF1_CONFIG, |
| 32 | ~(B_TSCGF1_CONFIG_ISNSCURRENTSEL_MASK |
| 33 | | B_TSCGF1_CONFIG_ISNSCHOPSEL_MASK |
| 34 | | B_TSCGF1_CONFIG_ISNSINTERNALVREFEN |
| 35 | | B_TSCGF1_CONFIG_IBGEN |
| 36 | | B_TSCGF1_CONFIG_IBGCHOPEN), |
| 37 | ((V_TSCGF1_CONFIG_ISNSCURRENTSEL_RATIO_MODE |
| 38 | << B_TSCGF1_CONFIG_ISNSCURRENTSEL_BP) |
| 39 | | (V_TSCGF1_CONFIG_ISNSCHOPSEL_RATIO_MODE |
| 40 | << B_TSCGF1_CONFIG_ISNSCHOPSEL_BP) |
| 41 | | (V_TSCGF1_CONFIG_ISNSINTERNALVREFEN_RATIO_MODE |
| 42 | << B_TSCGF1_CONFIG_ISNSINTERNALVREFEN_BP) |
| 43 | | (V_TSCGF1_CONFIG_IBGEN_RATIO_MODE |
| 44 | << B_TSCGF1_CONFIG_IBGEN_BP) |
| 45 | | (V_TSCGF1_CONFIG_IBGCHOPEN_RATIO_MODE |
| 46 | << B_TSCGF1_CONFIG_IBGCHOPEN_BP))), |
| 47 | |
| 48 | REG_SOC_UNIT_RMW(QUARK_SCSS_SOC_UNIT_TSCGF2_CONFIG2, |
| 49 | ~(B_TSCGF2_CONFIG2_ICALCONFIGSEL_MASK |
| 50 | | B_TSCGF2_CONFIG2_ISPARECTRL_MASK |
| 51 | | B_TSCGF2_CONFIG2_ICALCOARSETUNE_MASK), |
| 52 | ((V_TSCGF2_CONFIG2_ICALCONFIGSEL_RATIO_MODE |
| 53 | << B_TSCGF2_CONFIG2_ICALCONFIGSEL_BP) |
| 54 | | (V_TSCGF2_CONFIG2_ISPARECTRL_RATIO_MODE |
| 55 | << B_TSCGF2_CONFIG2_ISPARECTRL_BP) |
| 56 | | (V_TSCGF2_CONFIG2_ICALCOARSETUNE_RATIO_MODE |
| 57 | << B_TSCGF2_CONFIG2_ICALCOARSETUNE_BP))), |
| 58 | |
| 59 | REG_SOC_UNIT_RMW(QUARK_SCSS_SOC_UNIT_TSCGF2_CONFIG, |
| 60 | ~(B_TSCGF2_CONFIG_IDSCONTROL_MASK |
| 61 | | B_TSCGF2_CONFIG_IDSTIMING_MASK), |
| 62 | ((V_TSCGF2_CONFIG_IDSCONTROL_RATIO_MODE |
| 63 | << B_TSCGF2_CONFIG_IDSCONTROL_BP) |
| 64 | | (V_TSCGF2_CONFIG_IDSTIMING_RATIO_MODE |
| 65 | << B_TSCGF2_CONFIG_IDSTIMING_BP))), |
| 66 | |
| 67 | REG_SOC_UNIT_RMW(QUARK_SCSS_SOC_UNIT_TSCGF3_CONFIG, |
| 68 | ~B_TSCGF3_CONFIG_ITSGAMMACOEFF_MASK, |
| 69 | V_TSCGF3_CONFIG_ITSGAMMACOEFF_RATIO_MODE |
| 70 | << B_TSCGF3_CONFIG_ITSGAMMACOEFF_BP), |
| 71 | |
| 72 | /* Enable RMU Thermal sensor with a Catastrophic Trip point. */ |
| 73 | |
| 74 | /* Set up Catastrophic Trip point. |
| 75 | * |
| 76 | * Trip Register fields are 8-bit temperature values of granularity 1 |
| 77 | * degree C where 0x00 corresponds to -50 degrees C and 0xFF corresponds |
| 78 | * to 205 degrees C. |
| 79 | * |
| 80 | * Add 50 to Celsius values to get values for register fields. |
| 81 | */ |
| 82 | REG_RMU_TEMP_RMW(QUARK_NC_RMU_REG_TS_TRIP, |
| 83 | ~(TS_CAT_TRIP_SET_THOLD_MASK | TS_CAT_TRIP_CLEAR_THOLD_MASK), |
| 84 | (((PLATFORM_CATASTROPHIC_TRIP_CELSIUS + 50) |
| 85 | << TS_CAT_TRIP_SET_THOLD_BP) |
| 86 | | ((PLATFORM_CATASTROPHIC_CLEAR_CELSIUS + 50) |
| 87 | << TS_CAT_TRIP_CLEAR_THOLD_BP))), |
| 88 | |
| 89 | /* To enable the TS do the following: |
| 90 | * 1) Take the TS out of reset by setting itsrst to 0x0. |
| 91 | * 2) Enable the TS using RMU Thermal sensor mode register. |
| 92 | */ |
| 93 | REG_SOC_UNIT_AND(QUARK_SCSS_SOC_UNIT_TSCGF3_CONFIG, |
| 94 | ~B_TSCGF3_CONFIG_ITSRST), |
| 95 | REG_RMU_TEMP_OR(QUARK_NC_RMU_REG_TS_MODE, TS_ENABLE), |
| 96 | |
| 97 | /* Lock all RMU Thermal sensor control & trip point registers. */ |
| 98 | REG_RMU_TEMP_OR(QUARK_NC_RMU_REG_CONFIG, TS_LOCK_THRM_CTRL_REGS_ENABLE |
| 99 | | TS_LOCK_AUX_TRIP_PT_REGS_ENABLE), |
| 100 | REG_SCRIPT_END |
| 101 | }; |
Lee Leahy | d4edacb | 2016-02-08 07:12:30 -0800 | [diff] [blame] | 102 | |
Lee Leahy | b457649 | 2016-02-14 14:33:45 -0800 | [diff] [blame] | 103 | static void chip_init(void *chip_info) |
Lee Leahy | d4edacb | 2016-02-08 07:12:30 -0800 | [diff] [blame] | 104 | { |
Brandon Breitenstein | c6ec8dd | 2016-11-17 12:23:04 -0800 | [diff] [blame] | 105 | struct romstage_handoff *handoff; |
| 106 | |
Lee Leahy | 63e3dff | 2016-04-30 08:48:52 -0700 | [diff] [blame] | 107 | /* Validate the temperature settings */ |
| 108 | ASSERT(PLATFORM_CATASTROPHIC_TRIP_CELSIUS <= 255); |
| 109 | ASSERT(PLATFORM_CATASTROPHIC_TRIP_CELSIUS |
| 110 | > PLATFORM_CATASTROPHIC_CLEAR_CELSIUS); |
| 111 | |
| 112 | /* Set the temperature settings */ |
| 113 | reg_script_run(thermal_init_script); |
| 114 | |
| 115 | /* Verify that the thermal configuration is locked */ |
| 116 | ASSERT((reg_rmu_temp_read(QUARK_NC_RMU_REG_CONFIG) |
| 117 | & (TS_LOCK_THRM_CTRL_REGS_ENABLE |
| 118 | | TS_LOCK_AUX_TRIP_PT_REGS_ENABLE)) |
| 119 | == (TS_LOCK_THRM_CTRL_REGS_ENABLE |
| 120 | | TS_LOCK_AUX_TRIP_PT_REGS_ENABLE)); |
| 121 | |
Lee Leahy | d4edacb | 2016-02-08 07:12:30 -0800 | [diff] [blame] | 122 | /* Perform silicon specific init. */ |
Brandon Breitenstein | c6ec8dd | 2016-11-17 12:23:04 -0800 | [diff] [blame] | 123 | handoff = romstage_handoff_find_or_add(); |
| 124 | fsp_silicon_init(handoff->s3_resume); |
Lee Leahy | d4edacb | 2016-02-08 07:12:30 -0800 | [diff] [blame] | 125 | } |
| 126 | |
Lee Leahy | b457649 | 2016-02-14 14:33:45 -0800 | [diff] [blame] | 127 | static void pci_domain_set_resources(device_t dev) |
| 128 | { |
| 129 | assign_resources(dev->link_list); |
| 130 | } |
| 131 | |
| 132 | static struct device_operations pci_domain_ops = { |
| 133 | .read_resources = pci_domain_read_resources, |
| 134 | .set_resources = pci_domain_set_resources, |
| 135 | .scan_bus = pci_domain_scan_bus, |
| 136 | .ops_pci_bus = pci_bus_default_ops, |
| 137 | }; |
| 138 | |
| 139 | static void chip_enable_dev(device_t dev) |
| 140 | { |
Lee Leahy | b457649 | 2016-02-14 14:33:45 -0800 | [diff] [blame] | 141 | |
| 142 | /* Set the operations if it is a special bus type */ |
Lee Leahy | b457649 | 2016-02-14 14:33:45 -0800 | [diff] [blame] | 143 | if (dev->path.type == DEVICE_PATH_DOMAIN) |
| 144 | dev->ops = &pci_domain_ops; |
| 145 | } |
| 146 | |
Lee Leahy | d4edacb | 2016-02-08 07:12:30 -0800 | [diff] [blame] | 147 | struct chip_operations soc_intel_quark_ops = { |
| 148 | CHIP_NAME("Intel Quark") |
Lee Leahy | b457649 | 2016-02-14 14:33:45 -0800 | [diff] [blame] | 149 | .init = &chip_init, |
| 150 | .enable_dev = chip_enable_dev, |
Lee Leahy | d4edacb | 2016-02-08 07:12:30 -0800 | [diff] [blame] | 151 | }; |