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Marshall Dawson786bd5d2017-06-16 10:10:17 -06001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2015 Intel Corp.
5 * Copyright (C) 2017 Advanced Micro Devices
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18#include <arch/io.h>
19#include <cpu/x86/msr.h>
20#include <cpu/x86/tsc.h>
21#include <cpu/amd/amdfam15.h>
22#include <console/console.h>
23#include <soc/pci_devs.h>
24
25unsigned long tsc_freq_mhz(void)
26{
27 msr_t msr;
28 uint8_t cpufid;
29 uint8_t cpudid;
30 uint8_t boost_states;
31
32 /*
33 * See the Family 15h Models 70h-7Fh BKDG (PID 55072) definition for
34 * MSR0000_0010. The TSC increments at the P0 frequency. According
35 * to the "Software P-state Numbering" section, P0 is the highest
36 * non-boosted state. freq = 100MHz * (CpuFid + 10h) / (2^(CpuDid)).
37 */
38 boost_states = (pci_read_config32(DEV_D18F4, CORE_PERF_BOOST_CTRL)
39 >> 2) & 0x7;
40
41 msr = rdmsr(PSTATE_0_MSR + boost_states);
42 if (!(msr.hi & 0x80000000))
43 die("Unknown error: cannot determine P-state 0\n");
44
45 cpufid = (msr.lo & 0x3f);
46 cpudid = (msr.lo & 0x1c0) >> 6;
47
48 return (100 * (cpufid + 0x10)) / (0x01 << cpudid);
49}