blob: c94f5e7f69a02366afe157a95e9cdb37494a2750 [file] [log] [blame]
Marshall Dawson918c8712017-11-08 22:18:38 -07001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2012 Advanced Micro Devices, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <stdint.h>
17#include <stdlib.h>
18#include <string.h>
19#include <arch/io.h>
20#include <arch/early_variables.h>
Aaron Durbin0d2d77a2018-01-26 16:39:04 -070021#include <lib.h>
Marshall Dawson918c8712017-11-08 22:18:38 -070022#include <timer.h>
23#include <console/console.h>
24#include <commonlib/helpers.h>
25#include <spi_flash.h>
26#include <spi-generic.h>
27#include <device/device.h>
28#include <device/pci.h>
29#include <device/pci_ops.h>
30#include <soc/southbridge.h>
31#include <soc/pci_devs.h>
32#include <soc/imc.h>
33
Aaron Durbin0d2d77a2018-01-26 16:39:04 -070034#define SPI_DEBUG_DRIVER IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)
35
Marshall Dawson918c8712017-11-08 22:18:38 -070036static uintptr_t spibar CAR_GLOBAL;
37
38static uintptr_t get_spibase(void)
39{
Aaron Durbin9cf2f702018-01-24 11:59:09 -070040 return car_get_var(spibar);
Marshall Dawson918c8712017-11-08 22:18:38 -070041}
42
43static void set_spibar(uintptr_t base)
44{
Aaron Durbin9cf2f702018-01-24 11:59:09 -070045 car_set_var(spibar, base);
Marshall Dawson918c8712017-11-08 22:18:38 -070046}
47
48static inline uint8_t spi_read8(uint8_t reg)
49{
50 return read8((void *)(get_spibase() + reg));
51}
52
53static inline uint32_t spi_read32(uint8_t reg)
54{
55 return read32((void *)(get_spibase() + reg));
56}
57
58static inline void spi_write8(uint8_t reg, uint8_t val)
59{
60 write8((void *)(get_spibase() + reg), val);
61}
62
63static inline void spi_write32(uint8_t reg, uint32_t val)
64{
65 write32((void *)(get_spibase() + reg), val);
66}
67
Aaron Durbin0d2d77a2018-01-26 16:39:04 -070068static void dump_state(const char *str)
Marshall Dawson918c8712017-11-08 22:18:38 -070069{
Aaron Durbin0d2d77a2018-01-26 16:39:04 -070070 if (!SPI_DEBUG_DRIVER)
71 return;
72
73 printk(BIOS_DEBUG, "SPI: %s\n", str);
74 printk(BIOS_DEBUG, "Cntrl0: %x\n", spi_read32(SPI_CNTRL0));
75 printk(BIOS_DEBUG, "Status: %x\n", spi_read32(SPI_STATUS));
76 printk(BIOS_DEBUG, "TxByteCount: %x\n", spi_read8(SPI_TX_BYTE_COUNT));
77 printk(BIOS_DEBUG, "RxByteCount: %x\n", spi_read8(SPI_RX_BYTE_COUNT));
78 printk(BIOS_DEBUG, "CmdCode: %x\n", spi_read8(SPI_CMD_CODE));
79 hexdump((void *)(get_spibase() + SPI_FIFO), SPI_FIFO_DEPTH);
80}
81
82static int wait_for_ready(void)
83{
Marshall Dawson918c8712017-11-08 22:18:38 -070084 const uint32_t timeout_ms = 500;
85 struct stopwatch sw;
86
87 stopwatch_init_msecs_expire(&sw, timeout_ms);
88
89 do {
Aaron Durbin0d2d77a2018-01-26 16:39:04 -070090 if (!(spi_read32(SPI_STATUS) & SPI_BUSY))
Marshall Dawson918c8712017-11-08 22:18:38 -070091 return 0;
92 } while (!stopwatch_expired(&sw));
93
Marshall Dawson918c8712017-11-08 22:18:38 -070094 return -1;
95}
96
97static int execute_command(void)
98{
Aaron Durbin0d2d77a2018-01-26 16:39:04 -070099 dump_state("Before Execute");
Marshall Dawson918c8712017-11-08 22:18:38 -0700100
Aaron Durbin0d2d77a2018-01-26 16:39:04 -0700101 spi_write8(SPI_CMD_TRIGGER, SPI_CMD_TRIGGER_EXECUTE);
Marshall Dawson918c8712017-11-08 22:18:38 -0700102
Aaron Durbin0d2d77a2018-01-26 16:39:04 -0700103 if (wait_for_ready())
104 printk(BIOS_DEBUG,
105 "FCH SPI Error: Timeout executing command\n");
Marshall Dawson918c8712017-11-08 22:18:38 -0700106
Aaron Durbin0d2d77a2018-01-26 16:39:04 -0700107 dump_state("Transaction finished");
Marshall Dawson918c8712017-11-08 22:18:38 -0700108
Aaron Durbin0d2d77a2018-01-26 16:39:04 -0700109 return 0;
Marshall Dawson918c8712017-11-08 22:18:38 -0700110}
111
112void spi_init(void)
113{
114 uintptr_t bar;
115
116 bar = pci_read_config32(SOC_LPC_DEV, SPIROM_BASE_ADDRESS_REGISTER);
117 bar = ALIGN_DOWN(bar, 64);
118 set_spibar(bar);
119}
120
Marshall Dawson918c8712017-11-08 22:18:38 -0700121static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout,
122 size_t bytesout, void *din, size_t bytesin)
123{
Aaron Durbin0d2d77a2018-01-26 16:39:04 -0700124 size_t count;
Marshall Dawson918c8712017-11-08 22:18:38 -0700125 uint8_t cmd;
Aaron Durbin0d2d77a2018-01-26 16:39:04 -0700126 uint8_t *bufin = din;
127 const uint8_t *bufout = dout;
128
129 if (SPI_DEBUG_DRIVER)
Paul Menzele46ef4c2018-02-15 07:59:56 +0100130 printk(BIOS_DEBUG, "%s(%zx, %zx)\n", __func__, bytesout,
Aaron Durbin0d2d77a2018-01-26 16:39:04 -0700131 bytesin);
Marshall Dawson918c8712017-11-08 22:18:38 -0700132
133 /* First byte is cmd which cannot be sent through FIFO */
Aaron Durbin0d2d77a2018-01-26 16:39:04 -0700134 cmd = bufout[0];
135 bufout++;
Marshall Dawson918c8712017-11-08 22:18:38 -0700136 bytesout--;
137
138 /*
139 * Check if this is a write command attempting to transfer more bytes
140 * than the controller can handle. Iterations for writes are not
141 * supported here because each SPI write command needs to be preceded
142 * and followed by other SPI commands, and this sequence is controlled
143 * by the SPI chip driver.
144 */
Aaron Durbin0d2d77a2018-01-26 16:39:04 -0700145 if (bytesout + bytesin > SPI_FIFO_DEPTH) {
Marshall Dawson918c8712017-11-08 22:18:38 -0700146 printk(BIOS_DEBUG, "FCH SPI: Too much to write. Does your SPI"
147 " chip driver use spi_crop_chunk()?\n");
148 return -1;
149 }
150
Aaron Durbin0d2d77a2018-01-26 16:39:04 -0700151 if (wait_for_ready())
152 return -1;
153
154 spi_write8(SPI_CMD_CODE, cmd);
155 spi_write8(SPI_TX_BYTE_COUNT, bytesout);
156 spi_write8(SPI_RX_BYTE_COUNT, bytesin);
157
158 for (count = 0; count < bytesout; count++)
159 spi_write8(SPI_FIFO + count, bufout[count]);
160
161 if (execute_command())
162 return -1;
163
164 for (count = 0; count < bytesin; count++)
165 bufin[count] = spi_read8(SPI_FIFO + count + bytesout);
Marshall Dawson918c8712017-11-08 22:18:38 -0700166
167 return 0;
168}
169
170int chipset_volatile_group_begin(const struct spi_flash *flash)
171{
172 if (IS_ENABLED(CONFIG_STONEYRIDGE_IMC_FWM))
173 imc_sleep();
174 return 0;
175}
176
177int chipset_volatile_group_end(const struct spi_flash *flash)
178{
179 if (IS_ENABLED(CONFIG_STONEYRIDGE_IMC_FWM))
180 imc_wakeup();
181 return 0;
182}
183
184static const struct spi_ctrlr spi_ctrlr = {
185 .xfer = spi_ctrlr_xfer,
186 .xfer_vector = spi_xfer_two_vectors,
187 .max_xfer_size = SPI_FIFO_DEPTH,
Aaron Durbin063c00c2018-01-29 11:45:21 -0700188 .flags = SPI_CNTRLR_DEDUCT_CMD_LEN | SPI_CNTRLR_DEDUCT_OPCODE_LEN,
Marshall Dawson918c8712017-11-08 22:18:38 -0700189};
190
191const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = {
192 {
193 .ctrlr = &spi_ctrlr,
194 .bus_start = 0,
195 .bus_end = 0,
196 },
197};
198
199const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map);