blob: 6dea0c6864193144cf5a9c08e77da57a2b662fbd [file] [log] [blame]
Marc Jones24484842017-05-04 21:17:45 -06001/*
2 * This file is part of the coreboot project.
3 *
Richard Spiegelcb01efc2017-11-01 12:57:09 -07004 * Copyright (C) 2010-2017 Advanced Micro Devices, Inc.
Marc Jones24484842017-05-04 21:17:45 -06005 * Copyright (C) 2014 Sage Electronic Engineering, LLC
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
Martin Roth933ca5b2017-08-17 15:15:55 -060017#ifndef __STONEYRIDGE_H__
18#define __STONEYRIDGE_H__
Marc Jones24484842017-05-04 21:17:45 -060019
20#include <arch/io.h>
21#include <types.h>
22#include <device/pci_ids.h>
23#include <device/device.h>
Marshall Dawson07132a42017-10-30 14:52:01 -060024#include <device/pci_def.h>
Aaron Durbin4239a162017-11-03 12:57:45 -060025#include <soc/iomap.h>
Marc Jones24484842017-05-04 21:17:45 -060026#include "chip.h"
Richard Spiegele539c852017-12-25 18:25:58 -070027#include <rules.h>
Marc Jones24484842017-05-04 21:17:45 -060028
Marshall Dawson07132a42017-10-30 14:52:01 -060029/* PSP at D8F0 */
30#define PSP_MAILBOX_BAR PCI_BASE_ADDRESS_4 /* BKDG: "BAR3" */
31#define PSP_BAR_ENABLES 0x48
32#define PSP_MAILBOX_BAR_EN 0x10
33
Marshall Dawsond77c7642017-11-29 09:46:28 -070034/* Power management registers: 0xfed80300 or index/data at IO 0xcd6/cd7 */
Garrett Kirkendall9858bd22018-03-07 15:38:14 -060035#define PM_ISA_CONTROL 0x04
36#define MMIO_EN BIT(1)
Marshall Dawsonf039a0b2017-09-27 14:45:26 -060037#define PM_PCI_CTRL 0x08
38#define FORCE_SLPSTATE_RETRY BIT(25)
39#define FORCE_STPCLK_RETRY BIT(24)
Marc Jones24484842017-05-04 21:17:45 -060040#define PM_ACPI_MMIO_EN 0x24
41#define PM_SERIRQ_CONF 0x54
Richard Spiegelc5ecd3e2017-09-29 10:05:35 -070042#define PM_SERIRQ_NUM_BITS_17 0x0000
43#define PM_SERIRQ_NUM_BITS_18 0x0004
44#define PM_SERIRQ_NUM_BITS_19 0x0008
45#define PM_SERIRQ_NUM_BITS_20 0x000c
46#define PM_SERIRQ_NUM_BITS_21 0x0010
47#define PM_SERIRQ_NUM_BITS_22 0x0014
48#define PM_SERIRQ_NUM_BITS_23 0x0018
49#define PM_SERIRQ_NUM_BITS_24 0x001c
50#define PM_SERIRQ_MODE BIT(6)
51#define PM_SERIRQ_ENABLE BIT(7)
52
Richard Spiegel6a389142018-03-05 14:28:10 -070053#define PM_RTC_SHADOW 0x5b /* state when power resumes */
54#define PM_S5_AT_POWER_RECOVERY 0x04 /* S5 */
55#define PM_RESTORE_S0_IF_PREV_S0 0x07 /* S0 if previously at S0 */
56
Marc Jones24484842017-05-04 21:17:45 -060057#define PM_EVT_BLK 0x60
Marshall Dawson870fe792017-11-07 13:26:52 -070058#define WAK_STS BIT(15) /*AcpiPmEvtBlkx00 Pm1Status */
59#define PCIEXPWAK_STS BIT(14)
60#define RTC_STS BIT(10)
61#define PWRBTN_STS BIT(8)
62#define GBL_STS BIT(5)
63#define BM_STS BIT(4)
64#define TIMER_STS BIT(0)
65#define PCIEXPWAK_DIS BIT(14) /*AcpiPmEvtBlkx02 Pm1Enable */
66#define RTC_EN BIT(10)
67#define PWRBTN_EN BIT(8)
68#define GBL_EN BIT(5)
69#define TIMER_STS BIT(0)
Marc Jones24484842017-05-04 21:17:45 -060070#define PM1_CNT_BLK 0x62
71#define PM_TMR_BLK 0x64
72#define PM_CPU_CTRL 0x66
73#define PM_GPE0_BLK 0x68
Marshall Dawson4e101ad2017-06-15 12:17:38 -060074#define PM_ACPI_SMI_CMD 0x6a
Marc Jones24484842017-05-04 21:17:45 -060075#define PM_ACPI_CONF 0x74
Marshall Dawson7465b9d2017-11-10 16:33:21 -070076#define PM_ACPI_DECODE_STD BIT(0)
77#define PM_ACPI_GLOBAL_EN BIT(1)
78#define PM_ACPI_RTC_EN_EN BIT(2)
79#define PM_ACPI_TIMER_EN_EN BIT(4)
80#define PM_ACPI_MASK_ARB_DIS BIT(6)
81#define PM_ACPI_BIOS_RLS BIT(7)
82#define PM_ACPI_PWRBTNEN_EN BIT(8)
83#define PM_ACPI_REDUCED_HW_EN BIT(9)
84#define PM_ACPI_BLOCK_PCIE_PME BIT(24)
85#define PM_ACPI_PCIE_WAK_MASK BIT(25)
86#define PM_ACPI_WAKE_AS_GEVENT BIT(27)
87#define PM_ACPI_NB_PME_GEVENT BIT(28)
88#define PM_ACPI_RTC_WAKE_EN BIT(29)
Marshall Dawsonf039a0b2017-09-27 14:45:26 -060089#define PM_RST_CTRL1 0xbe
90#define SLPTYPE_CONTROL_EN BIT(5)
Marshall Dawson4e101ad2017-06-15 12:17:38 -060091#define PM_PMIO_DEBUG 0xd2
92#define PM_MANUAL_RESET 0xd3
93#define PM_HUD_SD_FLASH_CTRL 0xe7
94#define PM_YANG_SD_FLASH_CTRL 0xe8
95#define PM_PCIB_CFG 0xea
Martin Roth25721532018-01-11 16:14:39 -080096#define PM_GENINT_DISABLE BIT(0)
Richard Spiegelc5ecd3e2017-09-29 10:05:35 -070097#define PM_LPC_GATING 0xec
98#define PM_LPC_AB_NO_BYPASS_EN BIT(2)
99#define PM_LPC_A20_EN BIT(1)
100#define PM_LPC_ENABLE BIT(0)
Marc Jones24484842017-05-04 21:17:45 -0600101
Marshall Dawson4e101ad2017-06-15 12:17:38 -0600102#define SPIROM_BASE_ADDRESS_REGISTER 0xa0
Marc Jones24484842017-05-04 21:17:45 -0600103#define ROUTE_TPM_2_SPI BIT(3)
Richard Spiegelc5ecd3e2017-09-29 10:05:35 -0700104#define SPI_ABORT_ENABLE BIT(2)
105#define SPI_ROM_ENABLE BIT(1)
106#define SPI_ROM_ALT_ENABLE BIT(0)
107#define SPI_PRESERVE_BITS (BIT(0) | BIT(1) | BIT(2) | BIT(3))
Marc Jones24484842017-05-04 21:17:45 -0600108
Richard Spiegelc5ecd3e2017-09-29 10:05:35 -0700109#define LPC_PCI_CONTROL 0x40
110#define LEGACY_DMA_EN BIT(2)
111
Marc Jones24484842017-05-04 21:17:45 -0600112#define LPC_IO_PORT_DECODE_ENABLE 0x44
113#define DECODE_ENABLE_PARALLEL_PORT0 BIT(0)
114#define DECODE_ENABLE_PARALLEL_PORT1 BIT(1)
115#define DECODE_ENABLE_PARALLEL_PORT2 BIT(2)
116#define DECODE_ENABLE_PARALLEL_PORT3 BIT(3)
117#define DECODE_ENABLE_PARALLEL_PORT4 BIT(4)
118#define DECODE_ENABLE_PARALLEL_PORT5 BIT(5)
119#define DECODE_ENABLE_SERIAL_PORT0 BIT(6)
120#define DECODE_ENABLE_SERIAL_PORT1 BIT(7)
121#define DECODE_ENABLE_SERIAL_PORT2 BIT(8)
122#define DECODE_ENABLE_SERIAL_PORT3 BIT(9)
123#define DECODE_ENABLE_SERIAL_PORT4 BIT(10)
124#define DECODE_ENABLE_SERIAL_PORT5 BIT(11)
125#define DECODE_ENABLE_SERIAL_PORT6 BIT(12)
126#define DECODE_ENABLE_SERIAL_PORT7 BIT(13)
127#define DECODE_ENABLE_AUDIO_PORT0 BIT(14)
128#define DECODE_ENABLE_AUDIO_PORT1 BIT(15)
129#define DECODE_ENABLE_AUDIO_PORT2 BIT(16)
130#define DECODE_ENABLE_AUDIO_PORT3 BIT(17)
131#define DECODE_ENABLE_MIDI_PORT0 BIT(18)
132#define DECODE_ENABLE_MIDI_PORT1 BIT(19)
133#define DECODE_ENABLE_MIDI_PORT2 BIT(20)
134#define DECODE_ENABLE_MIDI_PORT3 BIT(21)
135#define DECODE_ENABLE_MSS_PORT0 BIT(22)
136#define DECODE_ENABLE_MSS_PORT1 BIT(23)
137#define DECODE_ENABLE_MSS_PORT2 BIT(24)
138#define DECODE_ENABLE_MSS_PORT3 BIT(25)
139#define DECODE_ENABLE_FDC_PORT0 BIT(26)
140#define DECODE_ENABLE_FDC_PORT1 BIT(27)
141#define DECODE_ENABLE_GAME_PORT BIT(28)
142#define DECODE_ENABLE_KBC_PORT BIT(29)
143#define DECODE_ENABLE_ACPIUC_PORT BIT(30)
144#define DECODE_ENABLE_ADLIB_PORT BIT(31)
145
146#define LPC_IO_OR_MEM_DECODE_ENABLE 0x48
147#define LPC_WIDEIO2_ENABLE BIT(25)
148#define LPC_WIDEIO1_ENABLE BIT(24)
Richard Spiegelc5ecd3e2017-09-29 10:05:35 -0700149#define DECODE_IO_PORT_ENABLE6 BIT(23)
150#define DECODE_IO_PORT_ENABLE5 BIT(22)
151#define DECODE_IO_PORT_ENABLE4 BIT(21)
152#define DECODE_IO_PORT_ENABLE3 BIT(19)
153#define DECODE_IO_PORT_ENABLE2 BIT(18)
154#define DECODE_IO_PORT_ENABLE1 BIT(17)
155#define DECODE_IO_PORT_ENABLE0 BIT(16)
156#define LPC_SYNC_TIMEOUT_COUNT_ENABLE BIT(7)
Marc Jones24484842017-05-04 21:17:45 -0600157#define LPC_WIDEIO0_ENABLE BIT(2)
Richard Spiegelc5ecd3e2017-09-29 10:05:35 -0700158/* Assuming word access to higher word (register 0x4a) */
159#define LPC_IO_OR_MEM_DEC_EN_HIGH 0x4a
160#define LPC_WIDEIO2_ENABLE_H BIT(9)
161#define LPC_WIDEIO1_ENABLE_H BIT(8)
162#define DECODE_IO_PORT_ENABLE6_H BIT(7)
163#define DECODE_IO_PORT_ENABLE5_H BIT(6)
164#define DECODE_IO_PORT_ENABLE4_H BIT(5)
165#define DECODE_IO_PORT_ENABLE3_H BIT(3)
166#define DECODE_IO_PORT_ENABLE2_H BIT(2)
167#define DECODE_IO_PORT_ENABLE1_H BIT(1)
168#define DECODE_IO_PORT_ENABLE0_H BIT(0)
Marc Jones24484842017-05-04 21:17:45 -0600169
Richard Spiegelc5ecd3e2017-09-29 10:05:35 -0700170/*
171 * Register 0x64 is 32-bit, composed by two 16-bit sub-registers.
172 * For ease of access, each sub-register is declared separetely.
173 */
Marc Jones24484842017-05-04 21:17:45 -0600174#define LPC_WIDEIO_GENERIC_PORT 0x64
Richard Spiegelc5ecd3e2017-09-29 10:05:35 -0700175#define LPC_WIDEIO1_GENERIC_PORT 0x66
176#define ROM_ADDRESS_RANGE1_START 0x68
177#define ROM_ADDRESS_RANGE1_END 0x6a
178#define ROM_ADDRESS_RANGE2_START 0x6c
179#define ROM_ADDRESS_RANGE2_END 0x6e
Marc Jones24484842017-05-04 21:17:45 -0600180
181#define LPC_ALT_WIDEIO_RANGE_ENABLE 0x74
182#define LPC_ALT_WIDEIO2_ENABLE BIT(3)
183#define LPC_ALT_WIDEIO1_ENABLE BIT(2)
184#define LPC_ALT_WIDEIO0_ENABLE BIT(0)
185
Richard Spiegelc5ecd3e2017-09-29 10:05:35 -0700186#define LPC_MISC_CONTROL_BITS 0x78
187#define LPC_NOHOG BIT(0)
188
Garrett Kirkendall65753062018-03-07 16:12:11 -0600189#define LPC_TRUSTED_PLATFORM_MODULE 0x7c
190#define TPM_12_EN BIT(0)
191#define TPM_LEGACY_EN BIT(2)
192
Marc Jones24484842017-05-04 21:17:45 -0600193#define LPC_WIDEIO2_GENERIC_PORT 0x90
194
Richard Spiegelc5ecd3e2017-09-29 10:05:35 -0700195/*
196 * LPC register 0xb8 is DWORD, here there are definitions for byte
197 * access. For example, bits 31-24 are accessed through byte access
198 * at register 0xbb ().
199 */
200#define LPC_ROM_DMA_EC_HOST_CONTROL 0xb8
201
202#define LPC_HOST_CONTROL 0xbb
203#define SPI_FROM_HOST_PREFETCH_EN BIT(0)
204
Marshall Dawson918c8712017-11-08 22:18:38 -0700205/* SPI Controller */
Marshall Dawson4e101ad2017-06-15 12:17:38 -0600206#define SPI_CNTRL0 0x00
Marshall Dawson918c8712017-11-08 22:18:38 -0700207#define SPI_BUSY BIT(31)
Marc Jones24484842017-05-04 21:17:45 -0600208#define SPI_READ_MODE_MASK (BIT(30) | BIT(29) | BIT(18))
209/* Nominal is 16.7MHz on older devices, 33MHz on newer */
210#define SPI_READ_MODE_NOM 0x00000000
211#define SPI_READ_MODE_DUAL112 ( BIT(29) )
212#define SPI_READ_MODE_QUAD114 ( BIT(29) | BIT(18))
213#define SPI_READ_MODE_DUAL122 (BIT(30) )
214#define SPI_READ_MODE_QUAD144 (BIT(30) | BIT(18))
215#define SPI_READ_MODE_NORMAL66 (BIT(30) | BIT(29) )
Marc Jones24484842017-05-04 21:17:45 -0600216#define SPI_READ_MODE_FAST (BIT(30) | BIT(29) | BIT(18))
Marshall Dawson918c8712017-11-08 22:18:38 -0700217#define SPI_FIFO_PTR_CLR BIT(20)
Marc Jones24484842017-05-04 21:17:45 -0600218#define SPI_ARB_ENABLE BIT(19)
Marshall Dawson918c8712017-11-08 22:18:38 -0700219#define EXEC_OPCODE BIT(16)
Marc Jones24484842017-05-04 21:17:45 -0600220#define SPI_CNTRL1 0x0c
Aaron Durbin0d2d77a2018-01-26 16:39:04 -0700221#define SPI_CMD_CODE 0x45
222#define SPI_CMD_TRIGGER 0x47
223#define SPI_CMD_TRIGGER_EXECUTE (BIT(7))
224#define SPI_TX_BYTE_COUNT 0x48
225#define SPI_RX_BYTE_COUNT 0x4B
226#define SPI_STATUS 0x4c
227#define SPI_DONE_BYTE_COUNT_SHIFT 0
228#define SPI_DONE_BYTE_COUNT_MASK 0xff
229#define SPI_FIFO_WR_PTR_SHIFT 8
230#define SPI_FIFO_WR_PTR_MASK 0x7f
231#define SPI_FIFO_RD_PTR_SHIFT 16
232#define SPI_FIFO_RD_PTR_MASK 0x7f
233#define SPI_FIFO 0x80
234#define SPI_FIFO_DEPTH (0xc7 - SPI_FIFO)
Marshall Dawson918c8712017-11-08 22:18:38 -0700235
236#define SPI100_SPEED_CONFIG 0x22
Marc Jonesdfeb1c42017-08-07 19:08:24 -0600237/* Use SPI_SPEED_16M-SPI_SPEED_66M below for the southbridge */
Marshall Dawson4e101ad2017-06-15 12:17:38 -0600238#define SPI_CNTRL1_SPEED_MASK (BIT(15) | BIT(14) | BIT(13) | BIT(12))
Marc Jones24484842017-05-04 21:17:45 -0600239#define SPI_NORM_SPEED_SH 12
240#define SPI_FAST_SPEED_SH 8
241
242#define SPI100_ENABLE 0x20
243#define SPI_USE_SPI100 BIT(0)
244
245#define SPI100_SPEED_CONFIG 0x22
246#define SPI_SPEED_66M (0x0)
247#define SPI_SPEED_33M ( BIT(0))
248#define SPI_SPEED_22M ( BIT(1) )
249#define SPI_SPEED_16M ( BIT(1) | BIT(0))
250#define SPI_SPEED_100M (BIT(2) )
251#define SPI_SPEED_800K (BIT(2) | BIT(0))
252#define SPI_NORM_SPEED_NEW_SH 12
253#define SPI_FAST_SPEED_NEW_SH 8
Marshall Dawson4e101ad2017-06-15 12:17:38 -0600254#define SPI_ALT_SPEED_NEW_SH 4
Marc Jones24484842017-05-04 21:17:45 -0600255#define SPI_TPM_SPEED_NEW_SH 0
256
Marshall Dawson4e101ad2017-06-15 12:17:38 -0600257#define SPI100_HOST_PREF_CONFIG 0x2c
Marc Jones24484842017-05-04 21:17:45 -0600258#define SPI_RD4DW_EN_HOST BIT(15)
259
Garrett Kirkendalld2558302018-03-06 09:05:20 -0600260#define MISC_MISC_CLK_CNTL_1 0x40
261#define OSCOUT1_CLK_OUTPUT_ENB BIT(2) /* 0 = Enabled, 1 = Disabled */
Richard Spiegelc5ecd3e2017-09-29 10:05:35 -0700262
Martin Roth48e44ee2017-11-12 14:54:09 -0700263/* IO 0xcf9 - Reset control port*/
264#define FULL_RST BIT(3)
265#define RST_CMD BIT(2)
266#define SYS_RST BIT(1)
267
268/* PMx10 - Power Reset Config */
269#define PWR_RESET_CFG 0x10
270#define TOGGLE_ALL_PWR_GOOD BIT(1)
271
Marc Jonesfb4c7d22017-11-22 22:16:31 -0700272#define XHCI_PM_INDIRECT_INDEX 0x48
273#define XHCI_PM_INDIRECT_DATA 0x4C
274#define XHCI_OVER_CURRENT_CONTROL 0x30
Marc Jonesfb4c7d22017-11-22 22:16:31 -0700275#define EHCI_OVER_CURRENT_CONTROL 0x70
276
277#define USB_OC0 0
278#define USB_OC1 1
279#define USB_OC2 2
280#define USB_OC3 3
281#define USB_OC4 4
282#define USB_OC5 5
283#define USB_OC6 6
284#define USB_OC7 7
285#define USB_OC_DISABLE 0xf
286#define USB_OC_DISABLE_ALL 0xffff
287
288#define OC_PORT0_SHIFT 0
289#define OC_PORT1_SHIFT 4
290#define OC_PORT2_SHIFT 8
291#define OC_PORT3_SHIFT 12
292
Richard Spiegelebf3aa82017-11-24 07:47:42 -0700293#define WIDEIO_RANGE_ERROR -1
294#define TOTAL_WIDEIO_PORTS 3
Richard Spiegele539c852017-12-25 18:25:58 -0700295#define AMD_GPIO_MUX_MASK 0x03
296
297#if ENV_BOOTBLOCK
298#define GPIO_TABLE_BOOTBLOCK 1
299#else
300#define GPIO_TABLE_BOOTBLOCK 0
301#endif
Richard Spiegele539c852017-12-25 18:25:58 -0700302
Garrett Kirkendall050b6fb2018-03-06 08:40:25 -0600303/* FCH AOAC Registers 0xfed81e00 */
304#define FCH_AOAC_D3_CONTROL_CLK_GEN 0x40
305#define FCH_AOAC_D3_CONTROL_I2C0 0x4A
306#define FCH_AOAC_D3_CONTROL_I2C1 0x4C
307#define FCH_AOAC_D3_CONTROL_I2C2 0x4E
308#define FCH_AOAC_D3_CONTROL_I2C3 0x50
309#define FCH_AOAC_D3_CONTROL_UART0 0x56
310#define FCH_AOAC_D3_CONTROL_UART1 0x58
311#define FCH_AOAC_D3_CONTROL_AMBA 0x62
312#define FCH_AOAC_D3_CONTROL_USB2 0x64
313#define FCH_AOAC_D3_CONTROL_USB3 0x6E
314/* Bit definitions for all FCH_AOAC_D3_CONTROL_* Registers */
315#define FCH_AOAC_TARGET_DEVICE_STATE (BIT(0) + BIT(1))
316#define FCH_AOAC_DEVICE_STATE BIT(2)
317#define FCH_AOAC_PWR_ON_DEV BIT(3)
318#define FCH_AOAC_SW_PWR_ON_RSTB BIT(4)
319#define FCH_AOAC_SW_REF_CLK_OK BIT(5)
320#define FCH_AOAC_SW_RST_B BIT(6)
321#define FCH_AOAC_IS_SW_CONTROL BIT(7)
322
323#define FCH_AOAC_D3_STATE_CLK_GEN 0x41
324#define FCH_AOAC_D3_STATE_I2C0 0x4B
325#define FCH_AOAC_D3_STATE_I2C1 0x4D
326#define FCH_AOAC_D3_STATE_I2C2 0x4F
327#define FCH_AOAC_D3_STATE_I2C3 0x51
328#define FCH_AOAC_D3_STATE_UART0 0x57
329#define FCH_AOAC_D3_STATE_UART1 0x59
330#define FCH_AOAC_D3_STATE_AMBA 0x63
331#define FCH_AOAC_D3_STATE_USB2 0x65
332#define FCH_AOAC_D3_STATE_USB3 0x6F
333/* Bit definitions for all FCH_AOAC_D3_STATE_* Registers */
334#define FCH_AOAC_PWR_RST_STATE BIT(0)
335#define FCH_AOAC_RST_CLK_OK_STATE BIT(1)
336#define FCH_AOAC_RST_B_STATE BIT(2)
337#define FCH_AOAC_DEV_OFF_GATING_STATE BIT(3)
338#define FCH_AOAC_D3COLD BIT(4)
339#define FCH_AOAC_CLK_OK_STATE BIT(5)
340#define FCH_AOAC_STAT0 BIT(6)
341#define FCH_AOAC_STAT1 BIT(7)
342
Richard Spiegele539c852017-12-25 18:25:58 -0700343struct soc_amd_stoneyridge_gpio {
344 uint8_t gpio;
345 uint8_t function;
346 uint8_t control;
347};
Richard Spiegelebf3aa82017-11-24 07:47:42 -0700348
Richard Spiegel0e0e93c2018-03-13 10:19:51 -0700349struct stoneyridge_aoac {
350 int enable;
351 int status;
352};
353
354void enable_aoac_devices(void);
Marc Jonesdfeb1c42017-08-07 19:08:24 -0600355void sb_enable_rom(void);
356void configure_stoneyridge_uart(void);
Garrett Kirkendall8da81da2018-03-07 09:00:05 -0600357void configure_stoneyridge_i2c(void);
Marc Jonesdfeb1c42017-08-07 19:08:24 -0600358void sb_clk_output_48Mhz(void);
359void sb_disable_4dw_burst(void);
360void sb_enable(device_t dev);
361void southbridge_final(void *chip_info);
362void southbridge_init(void *chip_info);
363void sb_lpc_port80(void);
364void sb_lpc_decode(void);
Garrett Kirkendall9858bd22018-03-07 15:38:14 -0600365void sb_acpi_mmio_decode(void);
Marc Jonesdfeb1c42017-08-07 19:08:24 -0600366void sb_pci_port80(void);
367void sb_read_mode(u32 mode);
368void sb_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm);
369void sb_set_readspeed(u16 norm, u16 fast);
Garrett Kirkendall65753062018-03-07 16:12:11 -0600370void sb_tpm_decode(void);
Marc Jonesdfeb1c42017-08-07 19:08:24 -0600371void sb_tpm_decode_spi(void);
Marc Jones24484842017-05-04 21:17:45 -0600372void lpc_wideio_512_window(uint16_t base);
373void lpc_wideio_16_window(uint16_t base);
374u8 pm_read8(u8 reg);
Marshall Dawsonf7ace0d2017-09-27 14:51:30 -0600375u16 pm_read16(u8 reg);
Marshall Dawson16745e32017-09-27 14:53:34 -0600376u32 pm_read32(u8 reg);
Marc Jones24484842017-05-04 21:17:45 -0600377void pm_write8(u8 reg, u8 value);
378void pm_write16(u8 reg, u16 value);
Marshall Dawson16745e32017-09-27 14:53:34 -0600379void pm_write32(u8 reg, u32 value);
Richard Spiegelcb01efc2017-11-01 12:57:09 -0700380uint8_t smi_read8(uint8_t offset);
381uint16_t smi_read16(uint8_t offset);
382uint32_t smi_read32(uint8_t offset);
383void smi_write8(uint8_t offset, uint8_t value);
384void smi_write16(uint8_t offset, uint16_t value);
385void smi_write32(uint8_t offset, uint32_t value);
Marshall Dawsona89d19a2017-11-28 17:51:29 -0700386uint8_t biosram_read8(uint8_t offset);
387void biosram_write8(uint8_t offset, uint8_t value);
388uint16_t biosram_read16(uint8_t offset);
389void biosram_write16(uint8_t offset, uint16_t value);
390uint32_t biosram_read32(uint8_t offset);
391void biosram_write32(uint8_t offset, uint32_t value);
Marshall Dawson813462e2017-10-04 15:05:17 -0600392uint16_t pm_acpi_pm_cnt_blk(void);
Marshall Dawson07568802017-11-08 15:43:06 -0700393uint16_t pm_acpi_pm_evt_blk(void);
Marc Jones7654f862017-12-01 17:17:43 -0700394void xhci_pm_write8(uint8_t reg, uint8_t value);
395uint8_t xhci_pm_read8(uint8_t reg);
396void xhci_pm_write16(uint8_t reg, uint16_t value);
397uint16_t xhci_pm_read16(uint8_t reg);
398void xhci_pm_write32(uint8_t reg, uint32_t value);
399uint32_t xhci_pm_read32(uint8_t reg);
Marshall Dawson9df969a2017-07-25 18:46:46 -0600400void bootblock_fch_early_init(void);
Richard Spiegelebf3aa82017-11-24 07:47:42 -0700401/**
Marc Jonesfa650f52018-02-08 23:19:29 -0700402 * @brief Save the UMA bize returned by AGESA
403 *
404 * @param size = in bytes
405 *
406 * @return none
407 */
408void save_uma_size(uint32_t size);
409/**
410 * @brief Save the UMA base address returned by AGESA
411 *
412 * @param base = 64bit base address
413 *
414 * @return none
415 */
416void save_uma_base(uint64_t base);
417/**
418 * @brief Get the saved UMA size
419 *
420 * @param none
421 *
422 * @return size in bytes
423 */
424uint32_t get_uma_size(void);
425/**
426 * @brief Get the saved UMA base
427 *
428 * @param none
429 *
430 * @return 64bit base address
431 */
432uint64_t get_uma_base(void);
433/**
Richard Spiegele539c852017-12-25 18:25:58 -0700434 * @brief program a particular set of GPIO
435 *
Justin TerAvest3fe3f042018-02-14 19:10:15 -0700436 * @param gpio_ptr = pointer to array of gpio configurations
437 * @param size = number of entries in array
438 *
Richard Spiegele539c852017-12-25 18:25:58 -0700439 * @return none
440 */
Justin TerAvest3fe3f042018-02-14 19:10:15 -0700441void sb_program_gpios(const struct soc_amd_stoneyridge_gpio *gpio_ptr,
442 size_t size);
Richard Spiegele539c852017-12-25 18:25:58 -0700443/**
Richard Spiegelebf3aa82017-11-24 07:47:42 -0700444 * @brief Find the size of a particular wide IO
445 *
446 * @param index = index of desired wide IO
447 *
448 * @return size of desired wide IO
449 */
450uint16_t sb_wideio_size(int index);
451/**
452 * @brief Identify if any LPC wide IO is covering the IO range
453 *
454 * @param start = start of IO range
455 * @param size = size of IO range
456 *
457 * @return Index of wide IO covering the range or error
458 */
459int sb_find_wideio_range(uint16_t start, uint16_t size);
460/**
461 * @brief Program a LPC wide IO to support an IO range
462 *
463 * @param start = start of range to be routed through wide IO
464 * @param size = size of range to be routed through wide IO
465 *
466 * @return Index of wide IO register used or error
467 */
468int sb_set_wideio_range(uint16_t start, uint16_t size);
Marc Jones24484842017-05-04 21:17:45 -0600469
Marc Jonesfb4c7d22017-11-22 22:16:31 -0700470/*
471 * Call the mainboard to get the USB Over Current Map. The mainboard
472 * returns the map and 0 on Success or -1 on error or no map. There is
473 * a default weak function in usb.c if the mainboard doesn't have any
474 * over current support.
475 */
476int mainboard_get_xhci_oc_map(uint16_t *usb_oc_map);
477int mainboard_get_ehci_oc_map(uint16_t *usb_oc_map);
478
Aaron Durbinde3e84c2018-01-29 17:44:58 -0700479/* Initialize all the i2c buses that are marked with early init. */
480void i2c_soc_early_init(void);
481
Daniel Kurtze0ea9822018-02-01 15:18:38 -0700482/* Initialize all the i2c buses that are not marked with early init. */
483void i2c_soc_init(void);
484
Martin Roth933ca5b2017-08-17 15:15:55 -0600485#endif /* __STONEYRIDGE_H__ */