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Marc Jones24484842017-05-04 21:17:45 -06001/*
Marshall Dawson714c0872017-09-22 14:13:09 -06002 * This file is part of the coreboot project.
Marc Jones24484842017-05-04 21:17:45 -06003 *
Marshall Dawson714c0872017-09-22 14:13:09 -06004 * Copyright (C) 2017 Advanced Micro Devices, Inc.
Marc Jones24484842017-05-04 21:17:45 -06005 * Copyright (C) 2014 Alexandru Gagniuc <mr.nuke.me@gmail.com>
Marshall Dawson714c0872017-09-22 14:13:09 -06006 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License, or (at your
10 * option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
Marc Jones24484842017-05-04 21:17:45 -060016 */
17
Martin Roth933ca5b2017-08-17 15:15:55 -060018#ifndef __SOUTHBRIDGE_AMD_PI_STONEYRIDGE_SMI_H__
19#define __SOUTHBRIDGE_AMD_PI_STONEYRIDGE_SMI_H__
Marc Jones24484842017-05-04 21:17:45 -060020
21#include <arch/io.h>
22
Marc Jonese8e72bd2017-10-04 22:12:31 -060023#define SMI_GEVENTS 24
24#define SCIMAPS 58
25#define SCI_GPES 32
26
27#define SMI_EVENT_STATUS 0x0
28#define SMI_EVENT_ENABLE 0x04
29#define SMI_SCI_TRIG 0x08
30#define SMI_SCI_LEVEL 0x0c
Marshall Dawson714c0872017-09-22 14:13:09 -060031#define SMI_SCI_STATUS 0x10
Marc Jonese8e72bd2017-10-04 22:12:31 -060032#define SMI_SCI_EN 0x14
33#define SMI_SCI_MAP0 0x40
34# define SMI_SCI_MAP(X) (SMI_SCI_MAP0 + (X))
Marc Jones24484842017-05-04 21:17:45 -060035
Marshall Dawson714c0872017-09-22 14:13:09 -060036/* SMI source and status */
37#define SMITYPE_AGPIO65 0
38#define SMITYPE_AGPIO66 1
39#define SMITYPE_AGPIO3 2
40#define SMITYPE_LPCPME_AGPIO22 3
41#define SMITYPE_GPIO4 4
42#define SMITYPE_LPCPD_AGPIOG21 5
43#define SMITYPE_IRTX1_G15 6
44#define SMITYPE_AGPIO5_DEVSLP0 7
45#define SMITYPE_WAKE_AGPIO2 8
46#define SMITYPE_APIO68_SGPIOCLK 9
47#define SMITYPE_AGPIO6 10
48#define SMITYPE_GPIO7 11
49#define SMITYPE_USBOC0_TRST_AGPIO16 12
50#define SMITYPE_USB0C1_TDI_AGPIO17 13
51#define SMITYPE_USBOC2_TCK_AGPIO18 14
52#define SMITYPE_TDO_USB0C3_AGPIO24 15
53#define SMITYPE_ACPRES_USBOC4_IRRX0_AGPIO23 16
54/* 17 Reserved */
55#define SMITYPE_BLINK_AGPIO11_USBOC7 18
56#define SMITYPE_SYSRESET_AGPIO1 19
57#define SMITYPE_IRRX1_AGPIO15 20
58#define SMITYPE_IRTX0_USBOC5_AGPIO13 21
59#define SMITYPE_GPIO9_SERPORTRX 22
60#define SMITYPE_GPIO8_SEPORTTX 23
61#define GEVENT_MASK ((1 << SMITYPE_AGPIO65) \
62 | (1 << SMITYPE_AGPIO66) \
63 | (1 << SMITYPE_AGPIO3) \
64 | (1 << SMITYPE_LPCPME_AGPIO22) \
65 | (1 << SMITYPE_GPIO4) \
66 | (1 << SMITYPE_LPCPD_AGPIOG21) \
67 | (1 << SMITYPE_IRTX1_G15) \
68 | (1 << SMITYPE_AGPIO5_DEVSLP0) \
69 | (1 << SMITYPE_WAKE_AGPIO2) \
70 | (1 << SMITYPE_APIO68_SGPIOCLK) \
71 | (1 << SMITYPE_AGPIO6) \
72 | (1 << SMITYPE_GPIO7) \
73 | (1 << SMITYPE_USBOC0_TRST_AGPIO16) \
74 | (1 << SMITYPE_USB0C1_TDI_AGPIO17) \
75 | (1 << SMITYPE_USBOC2_TCK_AGPIO18) \
76 | (1 << SMITYPE_TDO_USB0C3_AGPIO24) \
77 | (1 << SMITYPE_ACPRES_USBOC4_IRRX0_AGPIO23) \
78 | (1 << SMITYPE_BLINK_AGPIO11_USBOC7) \
79 | (1 << SMITYPE_SYSRESET_AGPIO1) \
80 | (1 << SMITYPE_IRRX1_AGPIO15) \
81 | (1 << SMITYPE_IRTX0_USBOC5_AGPIO13) \
82 | (1 << SMITYPE_GPIO9_SERPORTRX))
83#define SMITYPE_EHCI0_WAKE 24
84#define SMITYPE_EHCI1_WAKE 25
85#define SMITYPE_ESPI_SYS 26
86#define SMITYPE_ESPI_WAKE_PME 27
87/* 28-32 Reserved */
88#define SMITYPE_FCH_FAKE0 33
89#define SMITYPE_FCH_FAKE1 34
90#define SMITYPE_FCH_FAKE2 35
91/* 36 Reserved */
92#define SMITYPE_SATA_GEVENT0 37
93#define SMITYPE_SATA_GEVENT1 38
94#define SMITYPE_ACP_WAKE 39
95#define SMITYPE_ECG 40
96#define SMITYPE_GPIO_CTL 41
97#define SMITYPE_CIR_PME 42
98#define SMITYPE_ALT_HPET_ALARM 43
99#define SMITYPE_FAN_THERMAL 44
100#define SMITYPE_ASF_MASTER_SLAVE 45
101#define SMITYPE_I2S_WAKE 46
102#define SMITYPE_SMBUS0_MASTER 47
103#define SMITYPE_TWARN 48
104#define SMITYPE_TRAFFIC_MON 49
105#define SMITYPE_ILLB 50
106#define SMITYPE_PWRBUTTON_UP 51
107#define SMITYPE_PROCHOT 52
108#define SMITYPE_APU_HW 53
109#define SMITYPE_NB_SCI 54
110#define SMITYPE_RAS_SERR 55
111#define SMITYPE_XHC0_PME 56
112/* 57 Reserved */
113#define SMITYPE_ACDC_TIMER 58
114/* 59-62 Reserved */
115#define SMITYPE_TEMP_TSI 63
116#define SMITYPE_KB_RESET 64
117#define SMITYPE_SLP_TYP 65
118#define SMITYPE_AL2H_ACPI 66
119#define SMITYPE_AHCI 67
120/* 68-71 Reserved */
121#define SMITYPE_GBL_RLS 72
122#define SMITYPE_BIOS_RLS 73
123#define SMITYPE_PWRBUTTON_DOWN 74
124#define SMITYPE_SMI_CMD_PORT 75
125#define SMITYPE_USB_SMI 76
126#define SMITYPE_SERIRQ 77
127#define SMITYPE_SMBUS0_INTR 78
128#define SMITYPE_IMC 79
129#define SMITYPE_XHC_ERROR 80
130#define SMITYPE_INTRUDER 81
131#define SMITYPE_VBAT_LOW 82
132#define SMITYPE_PROTHOT 83
133#define SMITYPE_PCI_SERR 84
134#define SMITYPE_GPP_SERR 85
135/* 85-88 Reserved */
136#define SMITYPE_TMERTRIP 89
137#define SMITYPE_EMUL60_64 90
138#define SMITYPE_USB_FLR 91
139#define SMITYPE_SATA_FLR 92
140#define SMITYPE_AZ_FLR 93
141/* 94-132 Reserved */
142#define SMITYPE_FANIN0 133
143/* 134-137 Reserved */
144#define SMITYPE_FAKE0 138
145#define SMITYPE_FAKE1 139
146#define SMITYPE_FAKE2 140
147/* 141 Reserved */
148#define SMITYPE_SHORT_TIMER 142
149#define SMITYPE_LONG_TIMER 143
150#define SMITYPE_AB_SMI 144
151#define SMITYPE_SOFT_RESET 145
152/* 146-147 Reserved */
153#define SMITYPE_IOTRAP0 148
154/* 149-151 Reserved */
155#define SMITYPE_MEMTRAP0 152
156/* 153-155 Reserved */
157#define SMITYPE_CFGTRAP0 156
158/* 157-159 Reserved */
159#define NUMBER_SMITYPES 160
160#define TYPE_TO_MASK(X) (1 << (X) % 32)
161
162#define SMI_REG_SMISTS0 0x80
163#define SMI_REG_SMISTS1 0x84
164#define SMI_REG_SMISTS2 0x88
165#define SMI_REG_SMISTS3 0x8c
166#define SMI_REG_SMISTS4 0x90
167
168#define SMI_REG_POINTER 0x94
169# define SMI_STATUS_SRC_SCI (1 << 0)
170# define SMI_STATUS_SRC_0 (1 << 1) /* SMIx80 */
171# define SMI_STATUS_SRC_1 (1 << 2) /* SMIx84... */
172# define SMI_STATUS_SRC_2 (1 << 3)
173# define SMI_STATUS_SRC_3 (1 << 4)
174# define SMI_STATUS_SRC_4 (1 << 5)
175
176#define SMI_TIMER 0x96
177#define SMI_TIMER_MASK 0x7fff
178#define SMI_TIMER_EN (1 << 15)
179
180#define SMI_REG_SMITRIG0 0x98
181# define SMITRG0_EOS (1 << 28)
182# define SMI_TIMER_SEL (1 << 29)
183# define SMITRG0_SMIENB (1 << 31)
184
185#define SMI_REG_CONTROL0 0xa0
186#define SMI_REG_CONTROL1 0xa4
187#define SMI_REG_CONTROL2 0xa8
188#define SMI_REG_CONTROL3 0xac
189#define SMI_REG_CONTROL4 0xb0
190#define SMI_REG_CONTROL5 0xb4
191#define SMI_REG_CONTROL6 0xb8
192#define SMI_REG_CONTROL7 0xbc
193#define SMI_REG_CONTROL8 0xc0
194#define SMI_REG_CONTROL9 0xc4
Marc Jones24484842017-05-04 21:17:45 -0600195
196enum smi_mode {
197 SMI_MODE_DISABLE = 0,
198 SMI_MODE_SMI = 1,
199 SMI_MODE_NMI = 2,
200 SMI_MODE_IRQ13 = 3,
201};
202
Marc Jonese8e72bd2017-10-04 22:12:31 -0600203enum smi_sci_type {
204 NONE,
205 SCI,
206 SMI,
207 BOTH,
208};
209
210enum smi_sci_lvl {
211 SMI_SCI_LVL_LOW,
212 SMI_SCI_LVL_HIGH,
213};
214
215enum smi_sci_dir {
216 SMI_SCI_EDG,
217 SMI_SCI_LVL,
Marc Jones24484842017-05-04 21:17:45 -0600218};
219
Marshall Dawson36a23562017-09-28 17:21:09 -0600220struct smi_sources_t {
221 int type;
222 void (*handler)(void);
223};
224
Marc Jonese8e72bd2017-10-04 22:12:31 -0600225struct sci_source {
226 uint8_t scimap; /* SCIMAP 0-57 */
227 uint8_t gpe; /* 32 GPEs */
228 uint8_t direction; /* Active High or Low, smi_sci_lvl */
229 uint8_t level; /* Edge or Level, smi_sci_dir */
230};
231
Marshall Dawson66e62da2017-09-27 13:32:38 -0600232uint16_t pm_acpi_smi_cmd_port(void);
Marshall Dawsona05fdcb2017-09-27 15:01:37 -0600233void configure_smi(uint8_t smi_num, uint8_t mode);
Marc Jonesdfeb1c42017-08-07 19:08:24 -0600234void configure_gevent_smi(uint8_t gevent, uint8_t mode, uint8_t level);
Marc Jonese8e72bd2017-10-04 22:12:31 -0600235void configure_scimap(const struct sci_source *sci);
Marc Jonesdfeb1c42017-08-07 19:08:24 -0600236void disable_gevent_smi(uint8_t gevent);
Marc Jonese8e72bd2017-10-04 22:12:31 -0600237void gpe_configure_sci(const struct sci_source *scis, size_t num_gpes);
Marc Jones24484842017-05-04 21:17:45 -0600238
239#ifndef __SMM__
Marc Jonesdfeb1c42017-08-07 19:08:24 -0600240void enable_smi_generation(void);
Marc Jones24484842017-05-04 21:17:45 -0600241#endif
242
Martin Roth933ca5b2017-08-17 15:15:55 -0600243#endif /* __SOUTHBRIDGE_AMD_PI_STONEYRIDGE_SMI_H__ */