blob: 01171c3cf8062271546aa812a9aaafcf1b3cdc77 [file] [log] [blame]
Marc Jones24484842017-05-04 21:17:45 -06001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2017 Raptor Engineering, LLC
Aaron Durbin733ad922017-11-03 12:46:26 -06005 * Copyright 2017 Google Inc.
Marc Jones24484842017-05-04 21:17:45 -06006 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
Aaron Durbin733ad922017-11-03 12:46:26 -060017#ifndef __SOC_STONEYRIDGE_IOMAP_H__
18#define __SOC_STONEYRIDGE_IOMAP_H__
Marc Jones24484842017-05-04 21:17:45 -060019
Aaron Durbin4239a162017-11-03 12:57:45 -060020/* MMIO Ranges */
Marshall Dawson07132a42017-10-30 14:52:01 -060021#define PSP_MAILBOX_BAR3_BASE 0xf0a00000
Aaron Durbin4239a162017-11-03 12:57:45 -060022#define SPI_BASE_ADDRESS 0xfec10000
23#define IO_APIC2_ADDR 0xfec20000
24
Chris Ching6fc39d42017-12-20 16:06:03 -070025/* I2C fixed address */
26#define I2C_BASE_ADDRESS 0xfedc2000
27#define I2C_DEVICE_SIZE 0x00001000
28#define I2C_DEVICE_COUNT 4
29
Aaron Durbin4239a162017-11-03 12:57:45 -060030#if IS_ENABLED(CONFIG_HPET_ADDRESS_OVERRIDE)
31#error HPET address override is not allowed and must be fixed at 0xfed00000
32#endif
33#define HPET_BASE_ADDRESS 0xfed00000
34
35/* Register blocks at fixed offsets from FED8_0000h and enabled in PMx04[1] */
36#define AMD_SB_ACPI_MMIO_ADDR 0xfed80000
37#define APU_SMI_BASE 0xfed80200
38#define PM_MMIO_BASE 0xfed80300
Marshall Dawson50cc53d2018-01-24 21:00:55 -070039#define BIOSRAM_MMIO_BASE 0xfed80500
Garrett Kirkendall050b6fb2018-03-06 08:40:25 -060040#define IOMUX_MMIO_BASE 0xfed80d00
41#define MISC_MMIO_BASE 0xfed80e00
Marc Jones7654f862017-12-01 17:17:43 -070042#define XHCI_ACPI_PM_MMIO_BASE 0xfed81c00
Garrett Kirkendall050b6fb2018-03-06 08:40:25 -060043#define AOAC_MMIO_BASE 0xfed81e00
44
Aaron Durbin4239a162017-11-03 12:57:45 -060045#define APU_UART0_BASE 0xfedc6000
46#define APU_UART1_BASE 0xfedc8000
47
48#define FLASH_BASE_ADDR ((0xffffffff - CONFIG_ROM_SIZE) + 1)
49
50/* I/O Ranges */
51#define ACPI_SMI_CTL_PORT 0xb2
52#define STONEYRIDGE_ACPI_IO_BASE CONFIG_STONEYRIDGE_ACPI_IO_BASE
53#define ACPI_PM_EVT_BLK (STONEYRIDGE_ACPI_IO_BASE + 0x00) /* 4 bytes */
54#define ACPI_PM1_CNT_BLK (STONEYRIDGE_ACPI_IO_BASE + 0x04) /* 2 bytes */
55#define ACPI_CPU_CONTROL (STONEYRIDGE_ACPI_IO_BASE + 0x08) /* 6 bytes */
56#define ACPI_GPE0_BLK (STONEYRIDGE_ACPI_IO_BASE + 0x10) /* 8 bytes */
57#define ACPI_PM_TMR_BLK (STONEYRIDGE_ACPI_IO_BASE + 0x18) /* 4 bytes */
58#define SMB_BASE_ADDR 0xb00
Marshall Dawsond77c7642017-11-29 09:46:28 -070059#define PM2_INDEX 0xcd0
60#define PM2_DATA 0xcd1
61#define BIOSRAM_INDEX 0xcd4
62#define BIOSRAM_DATA 0xcd5
63#define PM_INDEX 0xcd6
64#define PM_DATA 0xcd7
Aaron Durbin4239a162017-11-03 12:57:45 -060065#define AB_INDX 0xcd8
66#define AB_DATA (AB_INDX+4)
67#define SYS_RESET 0xcf9
Marc Jones24484842017-05-04 21:17:45 -060068
Richard Spiegele539c852017-12-25 18:25:58 -070069/* GPIO control and mux access */
70#define AMD_GPIO_MUX (AMD_SB_ACPI_MMIO_ADDR + 0x00000d00)
71#define AMD_GPIO_CONTROL (AMD_SB_ACPI_MMIO_ADDR + 0x00001500)
72
Marshall Dawson22f54c52017-11-29 09:30:23 -070073/* BiosRam Ranges at 0xfed80500 or I/O 0xcd4/0xcd5 */
74#define BIOSRAM_CBMEM_TOP 0xf0 /* 4 bytes */
Marc Jonesfa650f52018-02-08 23:19:29 -070075#define BIOSRAM_UMA_SIZE 0xf4 /* 4 bytes */
76#define BIOSRAM_UMA_BASE 0xf8 /* 8 bytes */
Marshall Dawson22f54c52017-11-29 09:30:23 -070077
Aaron Durbin733ad922017-11-03 12:46:26 -060078#endif /* __SOC_STONEYRIDGE_IOMAP_H__ */