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Marc Jones24484842017-05-04 21:17:45 -06001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2014 Sage Electronic Engineering, LLC.
Richard Spiegel376dc822017-12-01 08:24:26 -07005 * Copyright (C) 2017 Advanced Micro Devices, Inc.
Marc Jones24484842017-05-04 21:17:45 -06006 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
Martin Roth933ca5b2017-08-17 15:15:55 -060017#ifndef __AMD_PCI_INT_DEFS_H__
18#define __AMD_PCI_INT_DEFS_H__
Marc Jones24484842017-05-04 21:17:45 -060019
20/*
Richard Spiegel376dc822017-12-01 08:24:26 -070021 * PIRQ and device routing - these define the index into the
22 * FCH PCI_INTR 0xC00/0xC01 interrupt routing table.
Marc Jones24484842017-05-04 21:17:45 -060023 */
24
Marshall Dawson4e101ad2017-06-15 12:17:38 -060025#define PIRQ_NC 0x1f /* Not Used */
Marc Jones24484842017-05-04 21:17:45 -060026#define PIRQ_A 0x00 /* INT A */
27#define PIRQ_B 0x01 /* INT B */
28#define PIRQ_C 0x02 /* INT C */
29#define PIRQ_D 0x03 /* INT D */
30#define PIRQ_E 0x04 /* INT E */
31#define PIRQ_F 0x05 /* INT F */
32#define PIRQ_G 0x06 /* INT G */
33#define PIRQ_H 0x07 /* INT H */
34#define PIRQ_MISC 0x08 /* Miscellaneous IRQ Settings - See FCH Spec */
35#define PIRQ_MISC0 0x09 /* Miscellaneous0 IRQ Settings */
Marshall Dawson4e101ad2017-06-15 12:17:38 -060036#define PIRQ_MISC1 0x0a /* Miscellaneous1 IRQ Settings */
37#define PIRQ_MISC2 0x0b /* Miscellaneous2 IRQ Settings */
38#define PIRQ_SIRQA 0x0c /* Serial IRQ INTA */
39#define PIRQ_SIRQB 0x0d /* Serial IRQ INTB */
40#define PIRQ_SIRQC 0x0e /* Serial IRQ INTC */
41#define PIRQ_SIRQD 0x0f /* Serial IRQ INTD */
Marc Jones24484842017-05-04 21:17:45 -060042#define PIRQ_SCI 0x10 /* SCI IRQ */
43#define PIRQ_SMBUS 0x11 /* SMBUS 14h.0 */
44#define PIRQ_ASF 0x12 /* ASF */
45#define PIRQ_HDA 0x13 /* HDA 14h.2 */
46#define PIRQ_FC 0x14 /* FC */
Marc Jones24484842017-05-04 21:17:45 -060047#define PIRQ_PMON 0x16 /* Performance Monitor */
Marshall Dawson4e101ad2017-06-15 12:17:38 -060048#define PIRQ_SD 0x17 /* SD */
Richard Spiegel376dc822017-12-01 08:24:26 -070049#define PIRQ_SDIO 0x1a /* SDIO */
Marc Jones24484842017-05-04 21:17:45 -060050#define PIRQ_IMC0 0x20 /* IMC INT0 */
51#define PIRQ_IMC1 0x21 /* IMC INT1 */
52#define PIRQ_IMC2 0x22 /* IMC INT2 */
53#define PIRQ_IMC3 0x23 /* IMC INT3 */
54#define PIRQ_IMC4 0x24 /* IMC INT4 */
55#define PIRQ_IMC5 0x25 /* IMC INT5 */
Richard Spiegel376dc822017-12-01 08:24:26 -070056#define PIRQ_EHCI 0x30 /* USB EHCI 12h.0 */
57#define PIRQ_XHCI 0x34 /* USB XHCI 10h.0 */
Marc Jones24484842017-05-04 21:17:45 -060058#define PIRQ_SATA 0x41 /* SATA 11h.0 */
Marc Jones24484842017-05-04 21:17:45 -060059#define PIRQ_GPIO 0x62 /* GPIO Controller Interrupt */
60#define PIRQ_I2C0 0x70
61#define PIRQ_I2C1 0x71
62#define PIRQ_I2C2 0x72
63#define PIRQ_I2C3 0x73
64#define PIRQ_UART0 0x74
65#define PIRQ_UART1 0x75
66
Martin Roth933ca5b2017-08-17 15:15:55 -060067#endif /* __AMD_PCI_INT_DEFS_H__ */