blob: 3e58d9a0c70f040973e5a28c533c57807726cf6b [file] [log] [blame]
Marc Jones257db582017-06-18 17:33:30 -06001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2016 Intel Corp.
5 * (Written by Lance Zhao <lijian.zhao@intel.com> for Intel Corp.)
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
Martin Roth933ca5b2017-08-17 15:15:55 -060018#ifndef __SOC_STONEYRIDGE_ACPI_H__
19#define __SOC_STONEYRIDGE_ACPI_H__
Marc Jones257db582017-06-18 17:33:30 -060020
21#include <arch/acpi.h>
22
23#if IS_ENABLED(CONFIG_STONEYRIDGE_LEGACY_FREE)
24 #define FADT_BOOT_ARCH ACPI_FADT_LEGACY_FREE
25#else
26 #define FADT_BOOT_ARCH (ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042)
27#endif
28
29#ifndef FADT_PM_PROFILE
30 #define FADT_PM_PROFILE PM_UNSPECIFIED
31#endif
32
33unsigned long southbridge_write_acpi_tables(device_t device,
34 unsigned long current, struct acpi_rsdp *rsdp);
35
36void southbridge_inject_dsdt(device_t device);
37
Martin Roth933ca5b2017-08-17 15:15:55 -060038#endif /* __SOC_STONEYRIDGE_ACPI_H__ */