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Lee Leahyeef40eb2017-03-23 10:54:57 -07001/*
2 * Copyright 2011, Marvell Semiconductor Inc.
3 * Lei Wen <leiwen@marvell.com>
4 *
5 * Copyright 2017 Intel Corporation
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
Lee Leahy48dbc662017-05-08 16:56:03 -070017#ifndef __COMMONLIB_STORAGE_SDHCI_H__
18#define __COMMONLIB_STORAGE_SDHCI_H__
Lee Leahyeef40eb2017-03-23 10:54:57 -070019
20#include <arch/io.h>
Lee Leahy48dbc662017-05-08 16:56:03 -070021#include <commonlib/sd_mmc_ctrlr.h>
Lee Leahyeef40eb2017-03-23 10:54:57 -070022
23/*
24 * Controller registers
25 */
26
27#define SDHCI_DMA_ADDRESS 0x00
28
29#define SDHCI_BLOCK_SIZE 0x04
30#define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF))
31
32#define SDHCI_BLOCK_COUNT 0x06
33
34#define SDHCI_ARGUMENT 0x08
35
36#define SDHCI_TRANSFER_MODE 0x0C
37#define SDHCI_TRNS_DMA 0x01
38#define SDHCI_TRNS_BLK_CNT_EN 0x02
39#define SDHCI_TRNS_ACMD12 0x04
40#define SDHCI_TRNS_READ 0x10
41#define SDHCI_TRNS_MULTI 0x20
42
43#define SDHCI_COMMAND 0x0E
44#define SDHCI_CMD_RESP_MASK 0x03
45#define SDHCI_CMD_CRC 0x08
46#define SDHCI_CMD_INDEX 0x10
47#define SDHCI_CMD_DATA 0x20
48#define SDHCI_CMD_ABORTCMD 0xC0
49
50#define SDHCI_CMD_RESP_NONE 0x00
51#define SDHCI_CMD_RESP_LONG 0x01
52#define SDHCI_CMD_RESP_SHORT 0x02
53#define SDHCI_CMD_RESP_SHORT_BUSY 0x03
54
55#define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff))
56#define SDHCI_GET_CMD(c) ((c>>8) & 0x3f)
57
58#define SDHCI_RESPONSE 0x10
59
60#define SDHCI_BUFFER 0x20
61
62#define SDHCI_PRESENT_STATE 0x24
63#define SDHCI_CMD_INHIBIT 0x00000001
64#define SDHCI_DATA_INHIBIT 0x00000002
65#define SDHCI_DOING_WRITE 0x00000100
66#define SDHCI_DOING_READ 0x00000200
67#define SDHCI_SPACE_AVAILABLE 0x00000400
68#define SDHCI_DATA_AVAILABLE 0x00000800
69#define SDHCI_CARD_PRESENT 0x00010000
70#define SDHCI_CARD_STATE_STABLE 0x00020000
71#define SDHCI_CARD_DETECT_PIN_LEVEL 0x00040000
72#define SDHCI_WRITE_PROTECT 0x00080000
73
74#define SDHCI_HOST_CONTROL 0x28
75#define SDHCI_CTRL_LED 0x01
76#define SDHCI_CTRL_4BITBUS 0x02
77#define SDHCI_CTRL_HISPD 0x04
78#define SDHCI_CTRL_DMA_MASK 0x18
79#define SDHCI_CTRL_SDMA 0x00
80#define SDHCI_CTRL_ADMA1 0x08
81#define SDHCI_CTRL_ADMA32 0x10
82#define SDHCI_CTRL_ADMA64 0x18
83#define SDHCI_CTRL_8BITBUS 0x20
84#define SDHCI_CTRL_CD_TEST_INS 0x40
85#define SDHCI_CTRL_CD_TEST 0x80
86
87#define SDHCI_POWER_CONTROL 0x29
88#define SDHCI_POWER_ON 0x01
89#define SDHCI_POWER_180 0x0A
90#define SDHCI_POWER_300 0x0C
91#define SDHCI_POWER_330 0x0E
92
93#define SDHCI_BLOCK_GAP_CONTROL 0x2A
94
95#define SDHCI_WAKE_UP_CONTROL 0x2B
96#define SDHCI_WAKE_ON_INT 0x01
97#define SDHCI_WAKE_ON_INSERT 0x02
98#define SDHCI_WAKE_ON_REMOVE 0x04
99
100#define SDHCI_CLOCK_CONTROL 0x2C
101#define SDHCI_DIVIDER_SHIFT 8
102#define SDHCI_DIVIDER_HI_SHIFT 6
103#define SDHCI_DIV_MASK 0xFF
104#define SDHCI_DIV_MASK_LEN 8
105#define SDHCI_DIV_HI_MASK 0x300
106#define SDHCI_CLOCK_CARD_EN 0x0004
107#define SDHCI_CLOCK_INT_STABLE 0x0002
108#define SDHCI_CLOCK_INT_EN 0x0001
109
110#define SDHCI_TIMEOUT_CONTROL 0x2E
111
112#define SDHCI_SOFTWARE_RESET 0x2F
113#define SDHCI_RESET_ALL 0x01
114#define SDHCI_RESET_CMD 0x02
115#define SDHCI_RESET_DATA 0x04
116
117#define SDHCI_INT_STATUS 0x30
118#define SDHCI_INT_ENABLE 0x34
119#define SDHCI_SIGNAL_ENABLE 0x38
120#define SDHCI_INT_RESPONSE 0x00000001
121#define SDHCI_INT_DATA_END 0x00000002
122#define SDHCI_INT_DMA_END 0x00000008
123#define SDHCI_INT_SPACE_AVAIL 0x00000010
124#define SDHCI_INT_DATA_AVAIL 0x00000020
125#define SDHCI_INT_CARD_INSERT 0x00000040
126#define SDHCI_INT_CARD_REMOVE 0x00000080
127#define SDHCI_INT_CARD_INT 0x00000100
128#define SDHCI_INT_ERROR 0x00008000
129#define SDHCI_INT_TIMEOUT 0x00010000
130#define SDHCI_INT_CRC 0x00020000
131#define SDHCI_INT_END_BIT 0x00040000
132#define SDHCI_INT_INDEX 0x00080000
133#define SDHCI_INT_DATA_TIMEOUT 0x00100000
134#define SDHCI_INT_DATA_CRC 0x00200000
135#define SDHCI_INT_DATA_END_BIT 0x00400000
136#define SDHCI_INT_BUS_POWER 0x00800000
137#define SDHCI_INT_ACMD12ERR 0x01000000
138#define SDHCI_INT_ADMA_ERROR 0x02000000
139
140#define SDHCI_INT_NORMAL_MASK 0x00007FFF
141#define SDHCI_INT_ERROR_MASK 0xFFFF8000
142
143#define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT \
144 | SDHCI_INT_CRC | SDHCI_INT_END_BIT \
145 | SDHCI_INT_INDEX)
146#define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END \
147 | SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL \
148 | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC \
149 | SDHCI_INT_DATA_END_BIT | SDHCI_INT_ADMA_ERROR)
150#define SDHCI_INT_ALL_MASK ((unsigned int)-1)
151
152#define SDHCI_ACMD12_ERR 0x3C
153
154#define SDHCI_HOST_CONTROL2 0x3E
155#define SDHCI_CTRL_UHS_MASK 0x0007
156#define SDHCI_CTRL_UHS_SDR12 0x0000
157#define SDHCI_CTRL_UHS_SDR25 0x0001
158#define SDHCI_CTRL_UHS_SDR50 0x0002
159#define SDHCI_CTRL_UHS_SDR104 0x0003
160#define SDHCI_CTRL_UHS_DDR50 0x0004
161#define SDHCI_CTRL_HS400 0x0005 /* reserved value in SDIO spec */
162#define SDHCI_CTRL_VDD_180 0x0008
163#define SDHCI_CTRL_DRV_TYPE_MASK 0x0030
164#define SDHCI_CTRL_DRV_TYPE_B 0x0000
165#define SDHCI_CTRL_DRV_TYPE_A 0x0010
166#define SDHCI_CTRL_DRV_TYPE_C 0x0020
167#define SDHCI_CTRL_DRV_TYPE_D 0x0030
168#define SDHCI_CTRL_EXEC_TUNING 0x0040
169#define SDHCI_CTRL_TUNED_CLK 0x0080
170#define SDHCI_CTRL_PRESET_VAL_ENABLE 0x8000
171
172#define SDHCI_CAPABILITIES 0x40
173#define SDHCI_TIMEOUT_CLK_MASK 0x0000003F
174#define SDHCI_TIMEOUT_CLK_SHIFT 0
175#define SDHCI_TIMEOUT_CLK_UNIT 0x00000080
176#define SDHCI_CLOCK_BASE_MASK 0x00003F00
177#define SDHCI_CLOCK_V3_BASE_MASK 0x0000FF00
178#define SDHCI_CLOCK_BASE_SHIFT 8
179#define SDHCI_MAX_BLOCK_MASK 0x00030000
180#define SDHCI_MAX_BLOCK_SHIFT 16
181#define SDHCI_CAN_DO_8BIT 0x00040000
182#define SDHCI_CAN_DO_ADMA2 0x00080000
183#define SDHCI_CAN_DO_ADMA1 0x00100000
184#define SDHCI_CAN_DO_HISPD 0x00200000
185#define SDHCI_CAN_DO_SDMA 0x00400000
186#define SDHCI_CAN_VDD_330 0x01000000
187#define SDHCI_CAN_VDD_300 0x02000000
188#define SDHCI_CAN_VDD_180 0x04000000
189#define SDHCI_CAN_64BIT 0x10000000
190
191#define SDHCI_CAPABILITIES_1 0x44
192#define SDHCI_SUPPORT_HS400 0x80000000
193
194#define SDHCI_MAX_CURRENT 0x48
195
196/* 4C-4F reserved for more max current */
197
198#define SDHCI_SET_ACMD12_ERROR 0x50
199#define SDHCI_SET_INT_ERROR 0x52
200
201#define SDHCI_ADMA_ERROR 0x54
202
203/* 55-57 reserved */
204
205#define SDHCI_ADMA_ADDRESS 0x58
206
207/* 60-FB reserved */
208
209#define SDHCI_SLOT_INT_STATUS 0xFC
210
211#define SDHCI_HOST_VERSION 0xFE
212#define SDHCI_VENDOR_VER_MASK 0xFF00
213#define SDHCI_VENDOR_VER_SHIFT 8
214#define SDHCI_SPEC_VER_MASK 0x00FF
215#define SDHCI_SPEC_VER_SHIFT 0
216#define SDHCI_SPEC_100 0
217#define SDHCI_SPEC_200 1
218#define SDHCI_SPEC_300 2
219
220/*
221 * End of controller registers.
222 */
223
224#define SDHCI_MAX_DIV_SPEC_200 256
225#define SDHCI_MAX_DIV_SPEC_300 2046
226
227/*
228 * Controller SDMA buffer boundary. Valid values from 4K to 512K in powers of 2.
229 */
230#define SDHCI_DEFAULT_BOUNDARY_SIZE (512 * 1024)
231#define SDHCI_DEFAULT_BOUNDARY_ARG (7)
232
233#define SDHCI_MAX_PER_DESCRIPTOR 0x10000
234
235/* ADMA descriptor attributes */
236#define SDHCI_ADMA_VALID (1 << 0)
237#define SDHCI_ADMA_END (1 << 1)
238#define SDHCI_ADMA_INT (1 << 2)
239#define SDHCI_ACT_NOP (0 << 4)
240#define SDHCI_ACT_TRAN (2 << 4)
241#define SDHCI_ACT_LINK (3 << 4)
242
243static inline void sdhci_writel(struct sdhci_ctrlr *sdhci_ctrlr, u32 val,
244 int reg)
245{
246 write32(sdhci_ctrlr->ioaddr + reg, val);
247}
248
249static inline void sdhci_writew(struct sdhci_ctrlr *sdhci_ctrlr, u16 val,
250 int reg)
251{
252 write16(sdhci_ctrlr->ioaddr + reg, val);
253}
254
255static inline void sdhci_writeb(struct sdhci_ctrlr *sdhci_ctrlr, u8 val,
256 int reg)
257{
258 write8(sdhci_ctrlr->ioaddr + reg, val);
259}
260static inline u32 sdhci_readl(struct sdhci_ctrlr *sdhci_ctrlr, int reg)
261{
262 return read32(sdhci_ctrlr->ioaddr + reg);
263}
264
265static inline u16 sdhci_readw(struct sdhci_ctrlr *sdhci_ctrlr, int reg)
266{
267 return read16(sdhci_ctrlr->ioaddr + reg);
268}
269
270static inline u8 sdhci_readb(struct sdhci_ctrlr *sdhci_ctrlr, int reg)
271{
272 return read8(sdhci_ctrlr->ioaddr + reg);
273}
274
275void sdhci_reset(struct sdhci_ctrlr *sdhci_ctrlr, u8 mask);
276void sdhci_cmd_done(struct sdhci_ctrlr *sdhci_ctrlr, struct mmc_command *cmd);
277int sdhci_setup_adma(struct sdhci_ctrlr *sdhci_ctrlr, struct mmc_data *data);
278int sdhci_complete_adma(struct sdhci_ctrlr *sdhci_ctrlr,
279 struct mmc_command *cmd);
280
Lee Leahy48dbc662017-05-08 16:56:03 -0700281#endif /* __COMMONLIB_STORAGE_SDHCI_H__ */