blob: bac510e12a17b3d953a8dac1b8ec0044e0fd1951 [file] [log] [blame]
Lee Leahyeef40eb2017-03-23 10:54:57 -07001/*
2 * Copyright 2011, Marvell Semiconductor Inc.
3 * Lei Wen <leiwen@marvell.com>
4 *
5 * Copyright 2017 Intel Corporation
6 *
7 * Secure Digital (SD) Host Controller interface specific code
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 */
19
20#include <assert.h>
21#include "bouncebuf.h"
22#include <console/console.h>
Lee Leahy48dbc662017-05-08 16:56:03 -070023#include <commonlib/sd_mmc_ctrlr.h>
24#include <commonlib/sdhci.h>
25#include <commonlib/storage.h>
Lee Leahyeef40eb2017-03-23 10:54:57 -070026#include <delay.h>
Lee Leahyeef40eb2017-03-23 10:54:57 -070027#include <endian.h>
28#include <halt.h>
29#include "sdhci.h"
30#include "sd_mmc.h"
31#include "storage.h"
32#include <string.h>
33#include <timer.h>
34#include <commonlib/stdlib.h>
35
36#define DMA_AVAILABLE ((CONFIG_SDHCI_ADMA_IN_BOOTBLOCK && ENV_BOOTBLOCK) \
37 || (CONFIG_SDHCI_ADMA_IN_VERSTAGE && ENV_VERSTAGE) \
38 || (CONFIG_SDHCI_ADMA_IN_ROMSTAGE && ENV_ROMSTAGE) \
39 || ENV_POSTCAR || ENV_RAMSTAGE)
40
41__attribute__((weak)) void *dma_malloc(size_t length_in_bytes)
42{
43 return malloc(length_in_bytes);
44}
45
46void sdhci_reset(struct sdhci_ctrlr *sdhci_ctrlr, u8 mask)
47{
48 struct stopwatch sw;
49
50 /* Wait max 100 ms */
51 stopwatch_init_msecs_expire(&sw, 100);
52
53 sdhci_writeb(sdhci_ctrlr, mask, SDHCI_SOFTWARE_RESET);
54 while (sdhci_readb(sdhci_ctrlr, SDHCI_SOFTWARE_RESET) & mask) {
55 if (stopwatch_expired(&sw)) {
56 sdhc_error("Reset 0x%x never completed.\n", (int)mask);
57 return;
58 }
59 udelay(1000);
60 }
61}
62
63void sdhci_cmd_done(struct sdhci_ctrlr *sdhci_ctrlr, struct mmc_command *cmd)
64{
65 int i;
66 if (cmd->resp_type & CARD_RSP_136) {
67 /* CRC is stripped so we need to do some shifting. */
68 for (i = 0; i < 4; i++) {
69 cmd->response[i] = sdhci_readl(sdhci_ctrlr,
70 SDHCI_RESPONSE + (3-i)*4) << 8;
71 if (i != 3)
72 cmd->response[i] |= sdhci_readb(sdhci_ctrlr,
73 SDHCI_RESPONSE + (3-i)*4-1);
74 }
75 sdhc_log_response(4, &cmd->response[0]);
76 sdhc_trace("Response: 0x%08x.%08x.%08x.%08x\n",
77 cmd->response[3], cmd->response[2], cmd->response[1],
78 cmd->response[0]);
79 } else {
80 cmd->response[0] = sdhci_readl(sdhci_ctrlr, SDHCI_RESPONSE);
81 sdhc_log_response(1, &cmd->response[0]);
82 sdhc_trace("Response: 0x%08x\n", cmd->response[0]);
83 }
84}
85
86static int sdhci_transfer_data(struct sdhci_ctrlr *sdhci_ctrlr,
87 struct mmc_data *data, unsigned int start_addr)
88{
89 uint32_t block_count;
90 uint32_t *buffer;
91 uint32_t *buffer_end;
92 uint32_t ps;
93 uint32_t ps_mask;
94 uint32_t stat;
95 struct stopwatch sw;
96
97 block_count = 0;
98 buffer = (uint32_t *)data->dest;
99 ps_mask = (data->flags & DATA_FLAG_READ)
100 ? SDHCI_DATA_AVAILABLE : SDHCI_SPACE_AVAILABLE;
101 stopwatch_init_msecs_expire(&sw, 100);
102 do {
103 /* Stop transfers if there is an error */
104 stat = sdhci_readl(sdhci_ctrlr, SDHCI_INT_STATUS);
105 sdhci_writel(sdhci_ctrlr, stat, SDHCI_INT_STATUS);
106 if (stat & SDHCI_INT_ERROR) {
107 sdhc_error("Error detected in status(0x%X)!\n", stat);
108 return -1;
109 }
110
111 /* Determine if the buffer is ready to move data */
112 ps = sdhci_readl(sdhci_ctrlr, SDHCI_PRESENT_STATE);
113 if (!(ps & ps_mask)) {
114 if (stopwatch_expired(&sw)) {
115 sdhc_error("Transfer data timeout\n");
116 return -1;
117 }
118 udelay(1);
119 continue;
120 }
121
122 /* Transfer a block of data */
123 buffer_end = &buffer[data->blocksize >> 2];
124 if (data->flags == DATA_FLAG_READ)
125 while (buffer_end > buffer)
126 *buffer++ = sdhci_readl(sdhci_ctrlr,
127 SDHCI_BUFFER);
128 else
129 while (buffer_end > buffer)
130 sdhci_writel(sdhci_ctrlr, *buffer++,
131 SDHCI_BUFFER);
132 if (++block_count >= data->blocks)
133 break;
134 } while (!(stat & SDHCI_INT_DATA_END));
135 return 0;
136}
137
138static int sdhci_send_command_bounced(struct sd_mmc_ctrlr *ctrlr,
139 struct mmc_command *cmd, struct mmc_data *data,
140 struct bounce_buffer *bbstate)
141{
142 struct sdhci_ctrlr *sdhci_ctrlr = (struct sdhci_ctrlr *)ctrlr;
143 u16 mode = 0;
144 unsigned int stat = 0;
145 int ret = 0;
146 u32 mask, flags;
147 unsigned int timeout, start_addr = 0;
148 struct stopwatch sw;
149
150 /* Wait max 1 s */
151 timeout = 1000;
152
153 sdhci_writel(sdhci_ctrlr, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
154 mask = SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT;
155
156 /* We shouldn't wait for data inihibit for stop commands, even
157 though they might use busy signaling */
158 if (cmd->flags & CMD_FLAG_IGNORE_INHIBIT)
159 mask &= ~SDHCI_DATA_INHIBIT;
160
161 while (sdhci_readl(sdhci_ctrlr, SDHCI_PRESENT_STATE) & mask) {
162 if (timeout == 0) {
163 sdhc_trace("Cmd: %2d, Arg: 0x%08x, not sent\n",
164 cmd->cmdidx, cmd->cmdarg);
165 sdhc_error("Controller never released inhibit bit(s), "
166 "present state %#8.8x.\n",
167 sdhci_readl(sdhci_ctrlr, SDHCI_PRESENT_STATE));
168 return CARD_COMM_ERR;
169 }
170 timeout--;
171 udelay(1000);
172 }
173
174 mask = SDHCI_INT_RESPONSE;
175 if (!(cmd->resp_type & CARD_RSP_PRESENT))
176 flags = SDHCI_CMD_RESP_NONE;
177 else if (cmd->resp_type & CARD_RSP_136)
178 flags = SDHCI_CMD_RESP_LONG;
179 else if (cmd->resp_type & CARD_RSP_BUSY) {
180 flags = SDHCI_CMD_RESP_SHORT_BUSY;
181 mask |= SDHCI_INT_DATA_END;
182 } else
183 flags = SDHCI_CMD_RESP_SHORT;
184
185 if (cmd->resp_type & CARD_RSP_CRC)
186 flags |= SDHCI_CMD_CRC;
187 if (cmd->resp_type & CARD_RSP_OPCODE)
188 flags |= SDHCI_CMD_INDEX;
189 if (data)
190 flags |= SDHCI_CMD_DATA;
191
192 /* Set Transfer mode regarding to data flag */
193 if (data) {
194 sdhci_writew(sdhci_ctrlr,
195 SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
196 data->blocksize), SDHCI_BLOCK_SIZE);
197
198 if (data->flags == DATA_FLAG_READ)
199 mode |= SDHCI_TRNS_READ;
200
201 if (data->blocks > 1)
202 mode |= SDHCI_TRNS_BLK_CNT_EN |
203 SDHCI_TRNS_MULTI | SDHCI_TRNS_ACMD12;
204
205 sdhci_writew(sdhci_ctrlr, data->blocks, SDHCI_BLOCK_COUNT);
206
207 if (DMA_AVAILABLE && (ctrlr->caps & DRVR_CAP_AUTO_CMD12)
208 && (cmd->cmdidx != MMC_CMD_AUTO_TUNING_SEQUENCE)) {
209 if (sdhci_setup_adma(sdhci_ctrlr, data))
210 return -1;
211 mode |= SDHCI_TRNS_DMA;
212 }
213 sdhci_writew(sdhci_ctrlr, mode, SDHCI_TRANSFER_MODE);
214 }
215
216 sdhc_trace("Cmd: %2d, Arg: 0x%08x\n", cmd->cmdidx, cmd->cmdarg);
217 sdhci_writel(sdhci_ctrlr, cmd->cmdarg, SDHCI_ARGUMENT);
218 sdhci_writew(sdhci_ctrlr, SDHCI_MAKE_CMD(cmd->cmdidx, flags),
219 SDHCI_COMMAND);
220 sdhc_log_command_issued();
221
222 if (DMA_AVAILABLE && (mode & SDHCI_TRNS_DMA))
223 return sdhci_complete_adma(sdhci_ctrlr, cmd);
224
225 stopwatch_init_msecs_expire(&sw, 2550);
226 do {
227 stat = sdhci_readl(sdhci_ctrlr, SDHCI_INT_STATUS);
228 if (stat & SDHCI_INT_ERROR) {
229 sdhc_trace("Error - IntStatus: 0x%08x\n", stat);
230 break;
231 }
232
233 if (stat & SDHCI_INT_DATA_AVAIL) {
234 sdhci_writel(sdhci_ctrlr, stat, SDHCI_INT_STATUS);
235 return 0;
236 }
237
238 /* Apply max timeout for R1b-type CMD defined in eMMC ext_csd
239 except for erase ones */
240 if (stopwatch_expired(&sw)) {
241 if (ctrlr->caps & DRVR_CAP_BROKEN_R1B)
242 return 0;
243 sdhc_error(
244 "Timeout for status update! IntStatus: 0x%08x\n",
245 stat);
246 return CARD_TIMEOUT;
247 }
248 } while ((stat & mask) != mask);
249
250 if ((stat & (SDHCI_INT_ERROR | mask)) == mask) {
251 if (cmd->cmdidx)
252 sdhci_cmd_done(sdhci_ctrlr, cmd);
253 sdhci_writel(sdhci_ctrlr, mask, SDHCI_INT_STATUS);
254 } else
255 ret = -1;
256
257 if (!ret && data)
258 ret = sdhci_transfer_data(sdhci_ctrlr, data, start_addr);
259
260 if (ctrlr->udelay_wait_after_cmd)
261 udelay(ctrlr->udelay_wait_after_cmd);
262
263 stat = sdhci_readl(sdhci_ctrlr, SDHCI_INT_STATUS);
264 sdhci_writel(sdhci_ctrlr, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
265
266 if (!ret)
267 return 0;
268
269 sdhci_reset(sdhci_ctrlr, SDHCI_RESET_CMD);
270 sdhci_reset(sdhci_ctrlr, SDHCI_RESET_DATA);
271 if (stat & SDHCI_INT_TIMEOUT) {
272 sdhc_error("CMD%d timeout, IntStatus: 0x%08x\n", cmd->cmdidx,
273 stat);
274 return CARD_TIMEOUT;
275 }
276
277 sdhc_error("CMD%d failed, IntStatus: 0x%08x\n", cmd->cmdidx, stat);
278 return CARD_COMM_ERR;
279}
280
281__attribute__((weak)) void sdhc_log_command(struct mmc_command *cmd)
282{
283}
284
285__attribute__((weak)) void sdhc_log_command_issued(void)
286{
287}
288
289__attribute__((weak)) void sdhc_log_response(uint32_t entries,
290 uint32_t *response)
291{
292}
293
294__attribute__((weak)) void sdhc_log_ret(int ret)
295{
296}
297
298static void sdhci_led_control(struct sd_mmc_ctrlr *ctrlr, int on)
299{
300 uint8_t host_ctrl;
301 struct sdhci_ctrlr *sdhci_ctrlr = (struct sdhci_ctrlr *)ctrlr;
302
303 host_ctrl = sdhci_readb(sdhci_ctrlr, SDHCI_HOST_CONTROL);
304 host_ctrl &= ~SDHCI_CTRL_LED;
305 if (on)
306 host_ctrl |= SDHCI_CTRL_LED;
307 sdhci_writeb(sdhci_ctrlr, host_ctrl, SDHCI_HOST_CONTROL);
308}
309
310static int sdhci_send_command(struct sd_mmc_ctrlr *ctrlr,
311 struct mmc_command *cmd, struct mmc_data *data)
312{
313 void *buf;
314 unsigned int bbflags;
315 size_t len;
316 struct bounce_buffer *bbstate = NULL;
317 struct bounce_buffer bbstate_val;
318 int ret;
319
320 sdhc_log_command(cmd);
321
322 if (IS_ENABLED(CONFIG_SDHCI_BOUNCE_BUFFER) && data) {
323 if (data->flags & DATA_FLAG_READ) {
324 buf = data->dest;
325 bbflags = GEN_BB_WRITE;
326 } else {
327 buf = (void *)data->src;
328 bbflags = GEN_BB_READ;
329 }
330 len = data->blocks * data->blocksize;
331
332 /*
333 * on some platform(like rk3399 etc) need to worry about
334 * cache coherency, so check the buffer, if not dma
335 * coherent, use bounce_buffer to do DMA management.
336 */
337 if (!dma_coherent(buf)) {
338 bbstate = &bbstate_val;
339 if (bounce_buffer_start(bbstate, buf, len, bbflags)) {
340 sdhc_error(
341 "ERROR: Failed to get bounce buffer.\n");
342 return -1;
343 }
344 }
345 }
346
347 sdhci_led_control(ctrlr, 1);
348 ret = sdhci_send_command_bounced(ctrlr, cmd, data, bbstate);
349 sdhci_led_control(ctrlr, 0);
350 sdhc_log_ret(ret);
351
352 if (IS_ENABLED(CONFIG_SDHCI_BOUNCE_BUFFER) && bbstate)
353 bounce_buffer_stop(bbstate);
354
355 return ret;
356}
357
358static int sdhci_set_clock(struct sdhci_ctrlr *sdhci_ctrlr, unsigned int clock)
359{
360 struct sd_mmc_ctrlr *ctrlr = &sdhci_ctrlr->sd_mmc_ctrlr;
361 unsigned int actual, div, clk, timeout;
362
363 /* Turn off the clock if requested */
364 actual = clock;
365 if (actual == 0) {
366 sdhci_writew(sdhci_ctrlr, 0, SDHCI_CLOCK_CONTROL);
367 sdhc_debug("SDHCI bus clock: Off\n");
368 return 0;
369 }
370
371 /* Compute the divisor for the new clock frequency */
372 actual = MIN(actual, ctrlr->f_max);
373 actual = MAX(actual, ctrlr->f_min);
374 if (ctrlr->clock_base <= actual)
375 div = 0;
376 else {
377 /* Version 3.00 divisors must be a multiple of 2. */
378 if ((ctrlr->version & SDHCI_SPEC_VER_MASK)
379 >= SDHCI_SPEC_300) {
380 div = MIN(((ctrlr->clock_base + actual - 1)
381 / actual), SDHCI_MAX_DIV_SPEC_300);
382 actual = ctrlr->clock_base / div;
383 div += 1;
384 } else {
385 /* Version 2.00 divisors must be a power of 2. */
386 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
387 if ((ctrlr->clock_base / div) <= actual)
388 break;
389 }
390 actual = ctrlr->clock_base / div;
391 }
392 div >>= 1;
393 }
394
395 /* Set the new clock frequency */
396 if (actual != ctrlr->bus_hz) {
397 /* Turn off the clock */
398 sdhci_writew(sdhci_ctrlr, 0, SDHCI_CLOCK_CONTROL);
399
400 /* Set the new clock frequency */
401 clk = (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
402 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
403 << SDHCI_DIVIDER_HI_SHIFT;
404 clk |= SDHCI_CLOCK_INT_EN;
405 sdhci_writew(sdhci_ctrlr, clk, SDHCI_CLOCK_CONTROL);
406
407 /* Display the requested clock frequency */
408 sdhc_debug("SDHCI bus clock: %d.%03d MHz\n",
409 actual / 1000000,
410 (actual / 1000) % 1000);
411
412 /* Wait max 20 ms */
413 timeout = 20;
414 while (!((clk = sdhci_readw(sdhci_ctrlr, SDHCI_CLOCK_CONTROL))
415 & SDHCI_CLOCK_INT_STABLE)) {
416 if (timeout == 0) {
417 sdhc_error(
418 "Internal clock never stabilised.\n");
419 return -1;
420 }
421 timeout--;
422 udelay(1000);
423 }
424
425 clk |= SDHCI_CLOCK_CARD_EN;
426 sdhci_writew(sdhci_ctrlr, clk, SDHCI_CLOCK_CONTROL);
427 ctrlr->bus_hz = actual;
428 }
429 return 0;
430}
431
432/* Find leftmost set bit in a 32 bit integer */
433static int fls(u32 x)
434{
435 int r = 32;
436
437 if (!x)
438 return 0;
439 if (!(x & 0xffff0000u)) {
440 x <<= 16;
441 r -= 16;
442 }
443 if (!(x & 0xff000000u)) {
444 x <<= 8;
445 r -= 8;
446 }
447 if (!(x & 0xf0000000u)) {
448 x <<= 4;
449 r -= 4;
450 }
451 if (!(x & 0xc0000000u)) {
452 x <<= 2;
453 r -= 2;
454 }
455 if (!(x & 0x80000000u)) {
456 x <<= 1;
457 r -= 1;
458 }
459 return r;
460}
461
462static void sdhci_set_power(struct sdhci_ctrlr *sdhci_ctrlr,
463 unsigned short power)
464{
465 struct sd_mmc_ctrlr *ctrlr = &sdhci_ctrlr->sd_mmc_ctrlr;
466 u8 pwr = 0;
467 u8 pwr_ctrl;
468 const char *voltage;
469
470 if (power != (unsigned short)-1) {
471 switch (1 << power) {
472 case MMC_VDD_165_195:
473 voltage = "1.8";
474 pwr = SDHCI_POWER_180;
475 break;
476 case MMC_VDD_29_30:
477 case MMC_VDD_30_31:
478 voltage = "3.0";
479 pwr = SDHCI_POWER_300;
480 break;
481 case MMC_VDD_32_33:
482 case MMC_VDD_33_34:
483 voltage = "3.3";
484 pwr = SDHCI_POWER_330;
485 break;
486 }
487 }
488
489 /* Determine the power state */
490 pwr_ctrl = sdhci_readb(sdhci_ctrlr, SDHCI_POWER_CONTROL);
491 if (pwr == 0) {
492 if (pwr_ctrl & SDHCI_POWER_ON)
493 sdhc_debug("SDHCI voltage: Off\n");
494 sdhci_writeb(sdhci_ctrlr, 0, SDHCI_POWER_CONTROL);
495 return;
496 }
497
498 /* Determine if the power has changed */
499 if (pwr_ctrl != (pwr | SDHCI_POWER_ON)) {
500 sdhc_debug("SDHCI voltage: %s Volts\n", voltage);
501
502 /* Select the voltage */
503 if (ctrlr->caps & DRVR_CAP_NO_SIMULT_VDD_AND_POWER)
504 sdhci_writeb(sdhci_ctrlr, pwr, SDHCI_POWER_CONTROL);
505
506 /* Apply power to the SD/MMC device */
507 pwr |= SDHCI_POWER_ON;
508 sdhci_writeb(sdhci_ctrlr, pwr, SDHCI_POWER_CONTROL);
509 }
510}
511
512const u16 speed_driver_voltage[] = {
513 0, /* 0: BUS_TIMING_LEGACY */
514 0, /* 1: BUS_TIMING_MMC_HS */
515 0, /* 2: BUS_TIMING_SD_HS */
516 SDHCI_CTRL_UHS_SDR12 | SDHCI_CTRL_VDD_180, /* 3: BUS_TIMING_UHS_SDR12 */
517 SDHCI_CTRL_UHS_SDR25 | SDHCI_CTRL_VDD_180, /* 4: BUS_TIMING_UHS_SDR25 */
518 SDHCI_CTRL_UHS_SDR50 | SDHCI_CTRL_VDD_180, /* 5: BUS_TIMING_UHS_SDR50 */
519 /* 6: BUS_TIMING_UHS_SDR104 */
520 SDHCI_CTRL_UHS_SDR104 | SDHCI_CTRL_DRV_TYPE_A | SDHCI_CTRL_VDD_180,
521 SDHCI_CTRL_UHS_DDR50 | SDHCI_CTRL_VDD_180, /* 7: BUS_TIMING_UHS_DDR50 */
522 SDHCI_CTRL_UHS_DDR50 | SDHCI_CTRL_VDD_180, /* 8: BUS_TIMING_MMC_DDR52 */
523 /* 9: BUS_TIMING_MMC_HS200 */
524 SDHCI_CTRL_UHS_SDR104 | SDHCI_CTRL_DRV_TYPE_A | SDHCI_CTRL_VDD_180,
525 /* 10: BUS_TIMING_MMC_HS400 */
526 SDHCI_CTRL_HS400 | SDHCI_CTRL_DRV_TYPE_A | SDHCI_CTRL_VDD_180,
527 /* 11: BUS_TIMING_MMC_HS400ES */
528 SDHCI_CTRL_HS400 | SDHCI_CTRL_DRV_TYPE_A | SDHCI_CTRL_VDD_180
529};
530
531static void sdhci_set_uhs_signaling(struct sdhci_ctrlr *sdhci_ctrlr,
532 uint32_t timing)
533{
534 u16 ctrl_2;
535
536 /* Select bus speed mode, driver and VDD 1.8 volt support */
537 ctrl_2 = sdhci_readw(sdhci_ctrlr, SDHCI_HOST_CONTROL2);
538 ctrl_2 &= ~(SDHCI_CTRL_UHS_MASK | SDHCI_CTRL_DRV_TYPE_MASK
539 | SDHCI_CTRL_VDD_180);
540 if (timing < ARRAY_SIZE(speed_driver_voltage))
541 ctrl_2 |= speed_driver_voltage[timing];
542 sdhci_writew(sdhci_ctrlr, ctrl_2, SDHCI_HOST_CONTROL2);
543}
544
545static void sdhci_set_ios(struct sd_mmc_ctrlr *ctrlr)
546{
547 struct sdhci_ctrlr *sdhci_ctrlr = (struct sdhci_ctrlr *)ctrlr;
548 u32 ctrl;
549 u32 previous_ctrl;
550 u32 bus_width;
551 int version;
552
Lee Leahyeef40eb2017-03-23 10:54:57 -0700553 /* Set the clock frequency */
554 if (ctrlr->bus_hz != ctrlr->request_hz)
555 sdhci_set_clock(sdhci_ctrlr, ctrlr->request_hz);
556
557 /* Switch to 1.8 volt for HS200 */
558 if (ctrlr->caps & DRVR_CAP_1V8_VDD)
559 if (ctrlr->bus_hz == CLOCK_200MHZ)
560 sdhci_set_power(sdhci_ctrlr, MMC_VDD_165_195_SHIFT);
561
562 /* Determine the new bus width */
563 bus_width = 1;
564 ctrl = sdhci_readb(sdhci_ctrlr, SDHCI_HOST_CONTROL);
565 previous_ctrl = ctrl;
566 ctrl &= ~SDHCI_CTRL_4BITBUS;
567 version = ctrlr->version & SDHCI_SPEC_VER_MASK;
568 if (version >= SDHCI_SPEC_300)
569 ctrl &= ~SDHCI_CTRL_8BITBUS;
570
571 if ((ctrlr->bus_width == 8) && (version >= SDHCI_SPEC_300)) {
572 ctrl |= SDHCI_CTRL_8BITBUS;
573 bus_width = 8;
574 } else if (ctrlr->bus_width == 4) {
575 ctrl |= SDHCI_CTRL_4BITBUS;
576 bus_width = 4;
577 }
578
579 if (!(ctrlr->timing == BUS_TIMING_LEGACY) &&
580 !(ctrlr->caps & DRVR_CAP_NO_HISPD_BIT))
581 ctrl |= SDHCI_CTRL_HISPD;
582 else
583 ctrl &= ~SDHCI_CTRL_HISPD;
584
585 sdhci_set_uhs_signaling(sdhci_ctrlr, ctrlr->timing);
586
587 if (DMA_AVAILABLE) {
588 if (ctrlr->caps & DRVR_CAP_AUTO_CMD12) {
589 ctrl &= ~SDHCI_CTRL_DMA_MASK;
590 if (ctrlr->caps & DRVR_CAP_DMA_64BIT)
591 ctrl |= SDHCI_CTRL_ADMA64;
592 else
593 ctrl |= SDHCI_CTRL_ADMA32;
594 }
595 }
596
597 /* Set the new bus width */
598 if (IS_ENABLED(CONFIG_SDHC_DEBUG)
599 && ((ctrl ^ previous_ctrl) & (SDHCI_CTRL_4BITBUS
600 | ((version >= SDHCI_SPEC_300) ? SDHCI_CTRL_8BITBUS : 0))))
601 sdhc_debug("SDHCI bus width: %d bit%s\n", bus_width,
602 (bus_width != 1) ? "s" : "");
603 sdhci_writeb(sdhci_ctrlr, ctrl, SDHCI_HOST_CONTROL);
604}
605
606static void sdhci_tuning_start(struct sd_mmc_ctrlr *ctrlr, int retune)
607{
608 uint16_t host_ctrl2;
609 struct sdhci_ctrlr *sdhci_ctrlr = (struct sdhci_ctrlr *)ctrlr;
610
611 /* Start the bus tuning */
612 host_ctrl2 = sdhci_readw(sdhci_ctrlr, SDHCI_HOST_CONTROL2);
613 host_ctrl2 &= ~SDHCI_CTRL_TUNED_CLK;
614 host_ctrl2 |= (retune ? SDHCI_CTRL_TUNED_CLK : 0)
615 | SDHCI_CTRL_EXEC_TUNING;
616 sdhci_writew(sdhci_ctrlr, host_ctrl2, SDHCI_HOST_CONTROL2);
617}
618
619static int sdhci_is_tuning_complete(struct sd_mmc_ctrlr *ctrlr, int *successful)
620{
621 uint16_t host_ctrl2;
622 struct sdhci_ctrlr *sdhci_ctrlr = (struct sdhci_ctrlr *)ctrlr;
623
624 /* Determine if the bus tuning has completed */
625 host_ctrl2 = sdhci_readw(sdhci_ctrlr, SDHCI_HOST_CONTROL2);
626 *successful = ((host_ctrl2 & SDHCI_CTRL_TUNED_CLK) != 0);
627 return ((host_ctrl2 & SDHCI_CTRL_EXEC_TUNING) == 0);
628}
629
630/* Prepare SDHCI controller to be initialized */
631static int sdhci_pre_init(struct sdhci_ctrlr *sdhci_ctrlr)
632{
633 struct sd_mmc_ctrlr *ctrlr = &sdhci_ctrlr->sd_mmc_ctrlr;
634 unsigned int caps, caps_1;
635
636 /* Get controller version and capabilities */
637 ctrlr->version = sdhci_readw(sdhci_ctrlr, SDHCI_HOST_VERSION) & 0xff;
638 caps = sdhci_readl(sdhci_ctrlr, SDHCI_CAPABILITIES);
639 caps_1 = sdhci_readl(sdhci_ctrlr, SDHCI_CAPABILITIES_1);
640
641 /* Determine the supported voltages */
642 if (caps & SDHCI_CAN_VDD_330)
643 ctrlr->voltages |= MMC_VDD_32_33 | MMC_VDD_33_34;
644 if (caps & SDHCI_CAN_VDD_300)
645 ctrlr->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31;
646 if (caps & SDHCI_CAN_VDD_180)
647 ctrlr->voltages |= MMC_VDD_165_195;
648
649 /* Get the controller's base clock frequency */
650 if ((ctrlr->version & SDHCI_SPEC_VER_MASK) >= SDHCI_SPEC_300)
651 ctrlr->clock_base = (caps & SDHCI_CLOCK_V3_BASE_MASK)
652 >> SDHCI_CLOCK_BASE_SHIFT;
653 else
654 ctrlr->clock_base = (caps & SDHCI_CLOCK_BASE_MASK)
655 >> SDHCI_CLOCK_BASE_SHIFT;
656 ctrlr->clock_base *= 1000000;
657 ctrlr->f_max = ctrlr->clock_base;
658
659 /* Determine the controller's clock frequency range */
660 ctrlr->f_min = 0;
661 if ((ctrlr->version & SDHCI_SPEC_VER_MASK) >= SDHCI_SPEC_300)
662 ctrlr->f_min =
663 ctrlr->clock_base / SDHCI_MAX_DIV_SPEC_300;
664 else
665 ctrlr->f_min =
666 ctrlr->clock_base / SDHCI_MAX_DIV_SPEC_200;
667
668 /* Determine the controller's modes of operation */
669 ctrlr->caps |= DRVR_CAP_HS52 | DRVR_CAP_HS;
670 if (ctrlr->clock_base >= CLOCK_200MHZ) {
671 ctrlr->caps |= DRVR_CAP_HS200 | DRVR_CAP_HS200_TUNING;
672 if (caps_1 & SDHCI_SUPPORT_HS400)
673 ctrlr->caps |= DRVR_CAP_HS400
674 | DRVR_CAP_ENHANCED_STROBE;
675 }
676
677 /* Determine the bus widths the controller supports */
678 ctrlr->caps |= DRVR_CAP_4BIT;
679 if (caps & SDHCI_CAN_DO_8BIT)
680 ctrlr->caps |= DRVR_CAP_8BIT;
681
682 /* Determine the controller's DMA support */
683 if (caps & SDHCI_CAN_DO_ADMA2)
684 ctrlr->caps |= DRVR_CAP_AUTO_CMD12;
685 if (DMA_AVAILABLE && (caps & SDHCI_CAN_64BIT))
686 ctrlr->caps |= DRVR_CAP_DMA_64BIT;
687
688 /* Specify the modes that the driver stack supports */
689 ctrlr->caps |= DRVR_CAP_HC;
690
691 /* Let the SOC adjust the configuration to handle controller quirks */
692 soc_sd_mmc_controller_quirks(&sdhci_ctrlr->sd_mmc_ctrlr);
693 if (ctrlr->clock_base == 0) {
694 sdhc_error("Hardware doesn't specify base clock frequency\n");
695 return -1;
696 }
697 if (!ctrlr->f_max)
698 ctrlr->f_max = ctrlr->clock_base;
699
700 /* Display the results */
701 sdhc_trace("0x%08x: ctrlr->caps\n", ctrlr->caps);
702 sdhc_trace("%d.%03d MHz: ctrlr->clock_base\n",
703 ctrlr->clock_base / 1000000,
704 (ctrlr->clock_base / 1000) % 1000);
705 sdhc_trace("%d.%03d MHz: ctrlr->f_max\n",
706 ctrlr->f_max / 1000000,
707 (ctrlr->f_max / 1000) % 1000);
708 sdhc_trace("%d.%03d MHz: ctrlr->f_min\n",
709 ctrlr->f_min / 1000000,
710 (ctrlr->f_min / 1000) % 1000);
711 sdhc_trace("0x%08x: ctrlr->voltages\n", ctrlr->voltages);
712
713 sdhci_reset(sdhci_ctrlr, SDHCI_RESET_ALL);
714
715 return 0;
716}
717
718__attribute__((weak)) void soc_sd_mmc_controller_quirks(struct sd_mmc_ctrlr
719 *ctrlr)
720{
721}
722
723static int sdhci_init(struct sdhci_ctrlr *sdhci_ctrlr)
724{
725 struct sd_mmc_ctrlr *ctrlr = &sdhci_ctrlr->sd_mmc_ctrlr;
726 int rv;
727
728 /* Only initialize the controller upon reset or card insertion */
729 if (ctrlr->initialized)
730 return 0;
731
732 sdhc_debug("SDHCI Controller Base Address: 0x%p\n",
733 sdhci_ctrlr->ioaddr);
734
735 rv = sdhci_pre_init(sdhci_ctrlr);
736 if (rv)
737 return rv; /* The error has been already reported */
738
739 sdhci_set_power(sdhci_ctrlr, fls(ctrlr->voltages) - 1);
740
741 if (ctrlr->caps & DRVR_CAP_NO_CD) {
742 unsigned int status;
743
744 sdhci_writel(sdhci_ctrlr, SDHCI_CTRL_CD_TEST_INS
745 | SDHCI_CTRL_CD_TEST, SDHCI_HOST_CONTROL);
746
747 status = sdhci_readl(sdhci_ctrlr, SDHCI_PRESENT_STATE);
748 while ((!(status & SDHCI_CARD_PRESENT)) ||
749 (!(status & SDHCI_CARD_STATE_STABLE)) ||
750 (!(status & SDHCI_CARD_DETECT_PIN_LEVEL)))
751 status = sdhci_readl(sdhci_ctrlr, SDHCI_PRESENT_STATE);
752 }
753
754 /* Enable only interrupts served by the SD controller */
755 sdhci_writel(sdhci_ctrlr, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK,
756 SDHCI_INT_ENABLE);
757 /* Mask all sdhci interrupt sources */
758 sdhci_writel(sdhci_ctrlr, 0x0, SDHCI_SIGNAL_ENABLE);
759
760 /* Set timeout to maximum, shouldn't happen if everything's right. */
761 sdhci_writeb(sdhci_ctrlr, 0xe, SDHCI_TIMEOUT_CONTROL);
762
763 mdelay(10);
764 ctrlr->initialized = 1;
765 return 0;
766}
767
768static int sdhci_update(struct sdhci_ctrlr *sdhci_ctrlr)
769{
770 struct sd_mmc_ctrlr *ctrlr = &sdhci_ctrlr->sd_mmc_ctrlr;
771
772 if (ctrlr->caps & DRVR_CAP_REMOVABLE) {
773 int present = (sdhci_readl(sdhci_ctrlr, SDHCI_PRESENT_STATE) &
774 SDHCI_CARD_PRESENT) != 0;
775
776 if (!present) {
777 /* A card was present indicate the controller needs
778 * initialization on the next call.
779 */
780 ctrlr->initialized = 0;
781 return 0;
782 }
783 }
784
785 /* A card is present, get it ready. */
786 if (sdhci_init(sdhci_ctrlr))
787 return -1;
788 return 0;
789}
790
791void sdhci_update_pointers(struct sdhci_ctrlr *sdhci_ctrlr)
792{
793 struct sd_mmc_ctrlr *ctrlr = &sdhci_ctrlr->sd_mmc_ctrlr;
794
795 /* Update the routine pointers */
796 ctrlr->send_cmd = &sdhci_send_command;
797 ctrlr->set_ios = &sdhci_set_ios;
798 ctrlr->tuning_start = &sdhci_tuning_start;
799 ctrlr->is_tuning_complete = &sdhci_is_tuning_complete;
800}
801
802int add_sdhci(struct sdhci_ctrlr *sdhci_ctrlr)
803{
804 struct sd_mmc_ctrlr *ctrlr = &sdhci_ctrlr->sd_mmc_ctrlr;
805
806 sdhci_update_pointers(sdhci_ctrlr);
807
808 /* TODO(vbendeb): check if SDHCI spec allows to retrieve this value. */
809 ctrlr->b_max = 65535;
810
811 /* Initialize the SDHC controller */
812 return sdhci_update(sdhci_ctrlr);
813}