blob: ca067054e052263259c9cb7d76e275c0657a3168 [file] [log] [blame]
Lee Leahyeef40eb2017-03-23 10:54:57 -07001/*
2 * Copyright 2008, Freescale Semiconductor, Inc
3 * Andy Fleming
4 *
5 * Copyright 2013 Google Inc. All rights reserved.
6 * Copyright 2017 Intel Corporation
7 *
8 * MultiMediaCard (MMC) and eMMC specific support code
9 * This code is controller independent
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 */
21
Lee Leahy48dbc662017-05-08 16:56:03 -070022#include <commonlib/storage.h>
Lee Leahyeef40eb2017-03-23 10:54:57 -070023#include <console/console.h>
Lee Leahy927f06a2017-06-19 10:53:18 -070024#include <delay.h>
Lee Leahyeef40eb2017-03-23 10:54:57 -070025#include "sd_mmc.h"
26#include "mmc.h"
27#include "sd_mmc.h"
28#include "storage.h"
29#include <string.h>
Lee Leahy927f06a2017-06-19 10:53:18 -070030#include <timer.h>
Lee Leahyeef40eb2017-03-23 10:54:57 -070031
32/* We pass in the cmd since otherwise the init seems to fail */
33static int mmc_send_op_cond_iter(struct storage_media *media,
34 struct mmc_command *cmd, int use_arg)
35{
36 struct sd_mmc_ctrlr *ctrlr = media->ctrlr;
37
38 cmd->cmdidx = MMC_CMD_SEND_OP_COND;
39 cmd->resp_type = CARD_RSP_R3;
40
41 /* Set the controller's operating conditions */
42 if (use_arg) {
43 uint32_t mask = media->op_cond_response &
44 (OCR_VOLTAGE_MASK | OCR_ACCESS_MODE);
45 cmd->cmdarg = ctrlr->voltages & mask;
46
47 /* Always request high capacity if supported by the
48 * controller
49 */
50 if (ctrlr->caps & DRVR_CAP_HC)
51 cmd->cmdarg |= OCR_HCS;
52 }
53 cmd->flags = 0;
54 int err = ctrlr->send_cmd(ctrlr, cmd, NULL);
55 if (err)
56 return err;
57
58 media->op_cond_response = cmd->response[0];
59 return 0;
60}
61
62int mmc_send_op_cond(struct storage_media *media)
63{
64 struct mmc_command cmd;
65 int max_iters = 2;
66
67 /* Ask the card for its operating conditions */
68 cmd.cmdarg = 0;
69 for (int i = 0; i < max_iters; i++) {
70 int err = mmc_send_op_cond_iter(media, &cmd, i != 0);
71 if (err)
72 return err;
73
74 // OCR_BUSY is active low, this bit set means
75 // "initialization complete".
76 if (media->op_cond_response & OCR_BUSY)
77 return 0;
78 }
79 return CARD_IN_PROGRESS;
80}
81
82int mmc_complete_op_cond(struct storage_media *media)
83{
84 struct mmc_command cmd;
85 struct stopwatch sw;
86
87 stopwatch_init_msecs_expire(&sw, MMC_INIT_TIMEOUT_US_MS);
88 while (1) {
89 // CMD1 queries whether initialization is done.
90 int err = mmc_send_op_cond_iter(media, &cmd, 1);
91 if (err)
92 return err;
93
94 // OCR_BUSY means "initialization complete".
95 if (media->op_cond_response & OCR_BUSY)
96 break;
97
98 // Check if init timeout has expired.
99 if (stopwatch_expired(&sw))
100 return CARD_UNUSABLE_ERR;
101
102 udelay(100);
103 }
104
105 media->version = MMC_VERSION_UNKNOWN;
106 media->ocr = cmd.response[0];
107
108 media->high_capacity = ((media->ocr & OCR_HCS) == OCR_HCS);
109 media->rca = 0;
110 return 0;
111}
112
113int mmc_send_ext_csd(struct sd_mmc_ctrlr *ctrlr, unsigned char *ext_csd)
114{
115 struct mmc_command cmd;
116 struct mmc_data data;
117 int rv;
118
119 /* Get the Card Status Register */
120 cmd.cmdidx = MMC_CMD_SEND_EXT_CSD;
121 cmd.resp_type = CARD_RSP_R1;
122 cmd.cmdarg = 0;
123 cmd.flags = 0;
124
125 data.dest = (char *)ext_csd;
126 data.blocks = 1;
127 data.blocksize = 512;
128 data.flags = DATA_FLAG_READ;
129
130 rv = ctrlr->send_cmd(ctrlr, &cmd, &data);
131
132 if (!rv && IS_ENABLED(CONFIG_SD_MMC_TRACE)) {
133 int i, size;
134
135 size = data.blocks * data.blocksize;
136 sd_mmc_trace("\t%p ext_csd:", ctrlr);
137 for (i = 0; i < size; i++) {
138 if (!(i % 32))
139 sd_mmc_trace("\n");
140 sd_mmc_trace(" %2.2x", ext_csd[i]);
141 }
142 sd_mmc_trace("\n");
143 }
144 return rv;
145}
146
147static int mmc_switch(struct storage_media *media, uint8_t index, uint8_t value)
148{
149 struct mmc_command cmd;
150 struct sd_mmc_ctrlr *ctrlr = media->ctrlr;
151
152 cmd.cmdidx = MMC_CMD_SWITCH;
153 cmd.resp_type = CARD_RSP_R1b;
154 cmd.cmdarg = ((MMC_SWITCH_MODE_WRITE_BYTE << 24) |
155 (index << 16) | (value << 8));
156 cmd.flags = 0;
157
158 int ret = ctrlr->send_cmd(ctrlr, &cmd, NULL);
159
160 /* Waiting for the ready status */
161 sd_mmc_send_status(media, SD_MMC_IO_RETRIES);
162 return ret;
163
164}
165
166static void mmc_recalculate_clock(struct storage_media *media)
167{
168 uint32_t clock;
169
170 clock = CLOCK_26MHZ;
171 if (media->caps & DRVR_CAP_HS) {
172 if ((media->caps & DRVR_CAP_HS200) ||
173 (media->caps & DRVR_CAP_HS400))
174 clock = CLOCK_200MHZ;
175 else if (media->caps & DRVR_CAP_HS52)
176 clock = CLOCK_52MHZ;
177 }
178 SET_CLOCK(media->ctrlr, clock);
179}
180
181static int mmc_select_hs(struct storage_media *media)
182{
183 int ret;
184
185 /* Switch the MMC device into high speed mode */
186 ret = mmc_switch(media, EXT_CSD_HS_TIMING, EXT_CSD_TIMING_HS);
187 if (ret) {
188 sd_mmc_error("Timing switch to high speed failed\n");
189 return ret;
190 }
191 sdhc_debug("SDHCI switched MMC to high speed\n");
192
193 /* Increase the controller clock speed */
194 SET_TIMING(media->ctrlr, BUS_TIMING_MMC_HS);
195 media->caps |= DRVR_CAP_HS52 | DRVR_CAP_HS;
196 mmc_recalculate_clock(media);
197 ret = sd_mmc_send_status(media, SD_MMC_IO_RETRIES);
198 return ret;
199}
200
201static int mmc_send_tunning_seq(struct sd_mmc_ctrlr *ctrlr, char *buffer)
202{
203 struct mmc_command cmd;
204 struct mmc_data data;
205
206 /* Request the device send the tuning sequence to the host */
207 cmd.cmdidx = MMC_CMD_AUTO_TUNING_SEQUENCE;
208 cmd.resp_type = CARD_RSP_R1;
209 cmd.cmdarg = 0;
210 cmd.flags = CMD_FLAG_IGNORE_INHIBIT;
211
212 data.dest = buffer;
213 data.blocks = 1;
214 data.blocksize = (ctrlr->bus_width == 8) ? 128 : 64;
215 data.flags = DATA_FLAG_READ;
216 return ctrlr->send_cmd(ctrlr, &cmd, &data);
217}
218
219static int mmc_bus_tuning(struct storage_media *media)
220{
221 ALLOC_CACHE_ALIGN_BUFFER(char, buffer, 128);
222 struct sd_mmc_ctrlr *ctrlr = media->ctrlr;
223 int index;
224 int successful;
225
226 /* Request the device send the tuning sequence up to 40 times */
227 ctrlr->tuning_start(ctrlr, 0);
228 for (index = 0; index < 40; index++) {
229 mmc_send_tunning_seq(ctrlr, buffer);
230 if (ctrlr->is_tuning_complete(ctrlr, &successful)) {
231 if (successful)
232 return 0;
233 break;
234 }
235 }
236 sd_mmc_error("Bus tuning failed!\n");
237 return -1;
238}
239
240static int mmc_select_hs400(struct storage_media *media)
241{
242 uint8_t bus_width;
243 uint32_t caps;
244 struct sd_mmc_ctrlr *ctrlr = media->ctrlr;
245 int ret;
246 uint32_t timing;
247
248 /* Switch the MMC device into high speed mode */
249 ret = mmc_select_hs(media);
250 if (ret)
251 return ret;
252
253 /* Switch MMC device to 8-bit DDR with strobe */
254 bus_width = EXT_CSD_DDR_BUS_WIDTH_8;
255 caps = DRVR_CAP_HS400 | DRVR_CAP_HS52 | DRVR_CAP_HS;
256 timing = BUS_TIMING_MMC_HS400;
257 if ((ctrlr->caps & DRVR_CAP_ENHANCED_STROBE)
258 && (media->caps & DRVR_CAP_ENHANCED_STROBE)) {
259 bus_width |= EXT_CSD_BUS_WIDTH_STROBE;
260 caps |= DRVR_CAP_ENHANCED_STROBE;
261 timing = BUS_TIMING_MMC_HS400ES;
262 }
263 ret = mmc_switch(media, EXT_CSD_BUS_WIDTH, bus_width);
264 if (ret) {
265 sd_mmc_error("Switching bus width for HS400 failed\n");
266 return ret;
267 }
268 sdhc_debug("SDHCI switched MMC to 8-bit DDR\n");
269
270 /* Set controller to 8-bit mode */
271 SET_BUS_WIDTH(ctrlr, 8);
272 media->caps |= EXT_CSD_BUS_WIDTH_8;
273
274 /* Switch MMC device to HS400 */
275 ret = mmc_switch(media, EXT_CSD_HS_TIMING, EXT_CSD_TIMING_HS400);
276 if (ret) {
277 sd_mmc_error("Switch to HS400 timing failed\n");
278 return ret;
279 }
280
281 /* Set controller to 200 MHz and use receive strobe */
282 SET_TIMING(ctrlr, timing);
283 media->caps |= caps;
284 mmc_recalculate_clock(media);
285 ret = sd_mmc_send_status(media, SD_MMC_IO_RETRIES);
286 return ret;
287}
288
289static int mmc_select_hs200(struct storage_media *media)
290{
291 struct sd_mmc_ctrlr *ctrlr = media->ctrlr;
292 int ret;
293
294 /* Switch the MMC device to 8-bit SDR */
295 ret = mmc_switch(media, EXT_CSD_BUS_WIDTH, EXT_CSD_BUS_WIDTH_8);
296 if (ret) {
297 sd_mmc_error("Switching bus width for HS200 failed\n");
298 return ret;
299 }
300
301 /* Set controller to 8-bit mode */
302 SET_BUS_WIDTH(ctrlr, 8);
303 media->caps |= EXT_CSD_BUS_WIDTH_8;
304
305 /* Switch to HS200 */
306 ret = mmc_switch(media, EXT_CSD_HS_TIMING, EXT_CSD_TIMING_HS200);
307
308 if (ret) {
309 sd_mmc_error("Switch to HS200 failed\n");
310 return ret;
311 }
312 sdhc_debug("SDHCI switched MMC to 8-bit SDR\n");
313
314 /* Set controller to 200 MHz */
315 SET_TIMING(ctrlr, BUS_TIMING_MMC_HS200);
316 media->caps |= DRVR_CAP_HS200 | DRVR_CAP_HS52 | DRVR_CAP_HS;
317 mmc_recalculate_clock(media);
318
319 /* Tune the receive sampling point for the bus */
320 if ((!ret) && (ctrlr->caps & DRVR_CAP_HS200_TUNING))
321 ret = mmc_bus_tuning(media);
322 return ret;
323}
324
325int mmc_change_freq(struct storage_media *media)
326{
327 struct sd_mmc_ctrlr *ctrlr = media->ctrlr;
328 int err;
329 ALLOC_CACHE_ALIGN_BUFFER(unsigned char, ext_csd, 512);
330
331 media->caps = 0;
332
333 /* Only version 4 supports high-speed */
334 if (media->version < MMC_VERSION_4)
335 return 0;
336
337 err = mmc_send_ext_csd(ctrlr, ext_csd);
338 if (err)
339 return err;
340
Barnali Sarkare9628402017-12-27 13:51:18 +0530341 /* Determine if the device supports enhanced strobe */
342 media->caps |= ext_csd[EXT_CSD_STROBE_SUPPORT]
343 ? DRVR_CAP_ENHANCED_STROBE : 0;
344
Lee Leahyeef40eb2017-03-23 10:54:57 -0700345 if ((ctrlr->caps & DRVR_CAP_HS400) &&
346 (ext_csd[EXT_CSD_CARD_TYPE] & MMC_HS400))
347 err = mmc_select_hs400(media);
348 else if ((ctrlr->caps & DRVR_CAP_HS200) &&
349 (ext_csd[EXT_CSD_CARD_TYPE] & MMC_HS_200MHZ))
350 err = mmc_select_hs200(media);
351 else
352 err = mmc_select_hs(media);
353
354 return err;
355}
356
357int mmc_set_bus_width(struct storage_media *media)
358{
359 struct sd_mmc_ctrlr *ctrlr = media->ctrlr;
360 int err;
361 int width;
362
363 ALLOC_CACHE_ALIGN_BUFFER(unsigned char, ext_csd, EXT_CSD_SIZE);
364 ALLOC_CACHE_ALIGN_BUFFER(unsigned char, test_csd, EXT_CSD_SIZE);
365
366 /* Set the bus width */
367 err = 0;
368 for (width = EXT_CSD_BUS_WIDTH_8; width >= 0; width--) {
369 /* If HS200 is switched, Bus Width has been 8-bit */
370 if ((media->caps & DRVR_CAP_HS200) ||
371 (media->caps & DRVR_CAP_HS400))
372 break;
373
374 /* Set the card to use 4 bit*/
375 err = mmc_switch(media, EXT_CSD_BUS_WIDTH, width);
376 if (err)
377 continue;
378
379 if (!width) {
380 SET_BUS_WIDTH(ctrlr, 1);
381 break;
382 }
383 SET_BUS_WIDTH(ctrlr, 4 * width);
384
385 err = mmc_send_ext_csd(ctrlr, test_csd);
386 if (!err &&
387 (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] ==
388 test_csd[EXT_CSD_PARTITIONING_SUPPORT]) &&
389 (ext_csd[EXT_CSD_ERASE_GROUP_DEF] ==
390 test_csd[EXT_CSD_ERASE_GROUP_DEF]) &&
391 (ext_csd[EXT_CSD_REV] ==
392 test_csd[EXT_CSD_REV]) &&
393 (ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] ==
394 test_csd[EXT_CSD_HC_ERASE_GRP_SIZE]) &&
395 memcmp(&ext_csd[EXT_CSD_SEC_CNT],
396 &test_csd[EXT_CSD_SEC_CNT], 4) == 0) {
397 media->caps |= width;
398 break;
399 }
400 }
401 return err;
402}
403
404int mmc_update_capacity(struct storage_media *media)
405{
406 uint64_t capacity;
407 struct sd_mmc_ctrlr *ctrlr = media->ctrlr;
408 int err;
409 ALLOC_CACHE_ALIGN_BUFFER(unsigned char, ext_csd, EXT_CSD_SIZE);
410 uint32_t erase_size;
411 uint32_t hc_erase_size;
412 uint64_t hc_wp_size;
413 int index;
414
415 if (media->version < MMC_VERSION_4)
416 return 0;
417
418 /* check ext_csd version and capacity */
419 err = mmc_send_ext_csd(ctrlr, ext_csd);
420 if (err)
421 return err;
422
423 if (ext_csd[EXT_CSD_REV] < 2)
424 return 0;
425
Lee Leahyeef40eb2017-03-23 10:54:57 -0700426 /* Determine the eMMC device information */
427 media->partition_config = ext_csd[EXT_CSD_PART_CONF]
428 & EXT_CSD_PART_ACCESS_MASK;
429
430 /* Determine the user partition size
431 *
432 * According to the JEDEC Standard, the value of
433 * ext_csd's capacity is valid if the value is
434 * more than 2GB
435 */
Lee Leahyf968a4c2017-06-27 09:28:35 -0700436 capacity = (uint32_t)(ext_csd[EXT_CSD_SEC_CNT + 0] << 0 |
Lee Leahyeef40eb2017-03-23 10:54:57 -0700437 ext_csd[EXT_CSD_SEC_CNT + 1] << 8 |
438 ext_csd[EXT_CSD_SEC_CNT + 2] << 16 |
439 ext_csd[EXT_CSD_SEC_CNT + 3] << 24);
440 capacity *= 512;
441 if ((capacity >> 20) > 2 * 1024)
442 media->capacity[MMC_PARTITION_USER] = capacity;
443
444 /* Determine the boot parition sizes */
445 hc_erase_size = ext_csd[224] * 512 * KiB;
446 capacity = ext_csd[EXT_CSD_BOOT_SIZE_MULT] * 128 * KiB;
447 media->capacity[MMC_PARTITION_BOOT_1] = capacity;
448 media->capacity[MMC_PARTITION_BOOT_2] = capacity;
449
450 /* Determine the RPMB size */
451 hc_wp_size = ext_csd[EXT_CSD_HC_WP_GRP_SIZE] * hc_erase_size;
452 capacity = 128 * KiB * ext_csd[EXT_CSD_RPMB_SIZE_MULT];
453 media->capacity[MMC_PARTITION_RPMB] = capacity;
454
455 /* Determine the general partition sizes */
456 capacity = (ext_csd[EXT_CSD_GP_SIZE_MULT_GP0 + 2] << 16)
457 | (ext_csd[EXT_CSD_GP_SIZE_MULT_GP0 + 1] << 8)
458 | ext_csd[EXT_CSD_GP_SIZE_MULT_GP0];
459 capacity *= hc_wp_size;
460 media->capacity[MMC_PARTITION_GP1] = capacity;
461
462 capacity = (ext_csd[EXT_CSD_GP_SIZE_MULT_GP1 + 2] << 16)
463 | (ext_csd[EXT_CSD_GP_SIZE_MULT_GP1 + 1] << 8)
464 | ext_csd[EXT_CSD_GP_SIZE_MULT_GP1];
465 capacity *= hc_wp_size;
466 media->capacity[MMC_PARTITION_GP2] = capacity;
467
468 capacity = (ext_csd[EXT_CSD_GP_SIZE_MULT_GP2 + 2] << 16)
469 | (ext_csd[EXT_CSD_GP_SIZE_MULT_GP2 + 1] << 8)
470 | ext_csd[EXT_CSD_GP_SIZE_MULT_GP2];
471 capacity *= hc_wp_size;
472 media->capacity[MMC_PARTITION_GP3] = capacity;
473
474 capacity = (ext_csd[EXT_CSD_GP_SIZE_MULT_GP3 + 2] << 16)
475 | (ext_csd[EXT_CSD_GP_SIZE_MULT_GP3 + 1] << 8)
476 | ext_csd[EXT_CSD_GP_SIZE_MULT_GP3];
477 capacity *= hc_wp_size;
478 media->capacity[MMC_PARTITION_GP4] = capacity;
479
480 /* Determine the erase size */
481 erase_size = (sd_mmc_extract_uint32_bits(media->csd,
482 81, 5) + 1) *
483 (sd_mmc_extract_uint32_bits(media->csd, 86, 5)
484 + 1);
485 for (index = MMC_PARTITION_BOOT_1; index <= MMC_PARTITION_GP4;
486 index++) {
487 if (media->capacity[index] != 0) {
488 /* Enable the partitions */
489 err = mmc_switch(media, EXT_CSD_ERASE_GROUP_DEF,
490 EXT_CSD_PARTITION_ENABLE);
491 if (err) {
492 sdhc_error("Failed to enable partition access\n");
493 return err;
494 }
495
496 /* Use HC erase group size */
497 erase_size = hc_erase_size / media->write_bl_len;
498 break;
499 }
500 }
501 media->erase_blocks = erase_size;
502 media->trim_mult = ext_csd[EXT_CSD_TRIM_MULT];
503
504 return 0;
505}
506
507int mmc_set_partition(struct storage_media *media,
508 unsigned int partition_number)
509{
510 uint8_t partition_config;
511
512 /* Validate the partition number */
513 if ((partition_number > MMC_PARTITION_GP4)
514 || (!media->capacity[partition_number]))
515 return -1;
516
517 /* Update the partition register */
518 partition_config = media->partition_config;
519 partition_config &= ~EXT_CSD_PART_ACCESS_MASK;
520 partition_config |= partition_number;
521
522 /* Select the new partition */
523 int ret = mmc_switch(media, EXT_CSD_PART_CONF, partition_config);
524 if (!ret)
525 media->partition_config = partition_config;
526
527 return ret;
528}
529
530const char *mmc_partition_name(struct storage_media *media,
531 unsigned int partition_number)
532{
533 static const char * const partition_name[8] = {
534 "User", /* 0 */
535 "Boot 1", /* 1 */
536 "Boot 2", /* 2 */
537 "RPMB", /* 3 */
538 "GP 1", /* 4 */
539 "GP 2", /* 5 */
540 "GP 3", /* 6 */
541 "GP 4" /* 7 */
542 };
543
544 if (partition_number >= ARRAY_SIZE(partition_name))
545 return "";
546 return partition_name[partition_number];
547}