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Mario Scheithauer2d981202017-03-27 13:25:57 +02001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright 2016 Google Inc.
Mario Scheithauerd127be12018-04-23 10:55:39 +02005 * Copyright (C) 2017-2018 Siemens AG
Mario Scheithauer2d981202017-03-27 13:25:57 +02006 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
14 * GNU General Public License for more details.
15 */
16
Mario Scheithauer2d981202017-03-27 13:25:57 +020017#include <commonlib/helpers.h>
Aaron Durbin64031672018-04-21 14:45:32 -060018#include <compiler.h>
Mario Scheithauerd127be12018-04-23 10:55:39 +020019#include <baseboard/variants.h>
Mario Scheithauer2d981202017-03-27 13:25:57 +020020
21/*
22 * Pad configuration in ramstage. The order largely follows the 'GPIO Muxing'
23 * table found in EDS vol 1, but some pins aren't grouped functionally in
24 * the table so those were moved for more logical grouping.
25 */
26static const struct pad_config gpio_table[] = {
27
28 /* Southwest Community */
29
30 /* PCIE_WAKE[0:3]_N */
Mario Scheithauer0e1a5262018-08-22 14:43:24 +020031 PAD_CFG_NF(GPIO_205, NONE, DEEP, NF1), /* PCIE_WAKE0_N */
32 PAD_CFG_NF(GPIO_206, NONE, DEEP, NF1), /* PCIE_WAKE1_N */
33 PAD_CFG_NF(GPIO_207, NONE, DEEP, NF1), /* PCIE_WAKE2_N */
34 PAD_CFG_NF(GPIO_208, NONE, DEEP, NF1), /* PCIE_WAKE3_N */
Mario Scheithauer2d981202017-03-27 13:25:57 +020035
36 /* EMMC interface. */
37 PAD_CFG_NF(GPIO_156, DN_20K, DEEP, NF1), /* EMMC_CLK */
Mario Scheithauer0e1a5262018-08-22 14:43:24 +020038 PAD_CFG_NF(GPIO_157, NONE, DEEP, NF1), /* EMMC_D0 */
39 PAD_CFG_NF(GPIO_158, NONE, DEEP, NF1), /* EMMC_D1 */
40 PAD_CFG_NF(GPIO_159, NONE, DEEP, NF1), /* EMMC_D2 */
41 PAD_CFG_NF(GPIO_160, NONE, DEEP, NF1), /* EMMC_D3 */
42 PAD_CFG_NF(GPIO_161, NONE, DEEP, NF1), /* EMMC_D4 */
43 PAD_CFG_NF(GPIO_162, NONE, DEEP, NF1), /* EMMC_D5 */
44 PAD_CFG_NF(GPIO_163, NONE, DEEP, NF1), /* EMMC_D6 */
45 PAD_CFG_NF(GPIO_164, NONE, DEEP, NF1), /* EMMC_D7 */
46 PAD_CFG_NF(GPIO_165, NONE, DEEP, NF1), /* EMMC_CMD */
Mario Scheithauer2d981202017-03-27 13:25:57 +020047 PAD_CFG_NF(GPIO_182, DN_20K, DEEP, NF1), /* EMMC_RCLK */
48
49 /* SDIO -- unused */
50 PAD_CFG_GPI(GPIO_166, DN_20K, DEEP), /* SDIO_CLK */
Mario Scheithauer0e1a5262018-08-22 14:43:24 +020051 PAD_CFG_GPI(GPIO_167, NONE, DEEP), /* SDIO_D0 */
Mario Scheithauer2d981202017-03-27 13:25:57 +020052 /* Configure SDIO to enable power gating. */
Mario Scheithauer0e1a5262018-08-22 14:43:24 +020053 PAD_CFG_GPI(GPIO_168, NONE, DEEP), /* SDIO_D1 */
54 PAD_CFG_GPI(GPIO_169, NONE, DEEP), /* SDIO_D2 */
55 PAD_CFG_GPI(GPIO_170, NONE, DEEP), /* SDIO_D3 */
56 PAD_CFG_GPI(GPIO_171, NONE, DEEP), /* SDIO_CMD */
Mario Scheithauer2d981202017-03-27 13:25:57 +020057
58 /* SDCARD */
59 /* Pull down clock by 20K. */
60 PAD_CFG_NF(GPIO_172, DN_20K, DEEP, NF1), /* SDCARD_CLK */
Mario Scheithauer0e1a5262018-08-22 14:43:24 +020061 PAD_CFG_NF(GPIO_173, NONE, DEEP, NF1), /* SDCARD_D0 */
62 PAD_CFG_NF(GPIO_174, NONE, DEEP, NF1), /* SDCARD_D1 */
63 PAD_CFG_NF(GPIO_175, NONE, DEEP, NF1), /* SDCARD_D2 */
64 PAD_CFG_NF(GPIO_176, NONE, DEEP, NF1), /* SDCARD_D3 */
Mario Scheithauer2d981202017-03-27 13:25:57 +020065 /* Card detect is active LOW with external pull up. */
Mario Scheithauer0e1a5262018-08-22 14:43:24 +020066 PAD_CFG_NF(GPIO_177, NONE, DEEP, NF1), /* SDCARD_CD_N */
67 PAD_CFG_NF(GPIO_178, NONE, DEEP, NF1), /* SDCARD_CMD */
Mario Scheithauer2d981202017-03-27 13:25:57 +020068 /* CLK feedback, internal signal, needs 20K pull down. */
69 PAD_CFG_NF(GPIO_179, DN_20K, DEEP, NF1), /* SDCARD_CLK_FB */
Mario Scheithauer0e1a5262018-08-22 14:43:24 +020070 PAD_CFG_GPI(GPIO_186, NONE, DEEP), /* SDCARD_LVL_WP */
Mario Scheithauer2d981202017-03-27 13:25:57 +020071 /* EN_SD_SOCKET_PWR_L for SD slot power control. Default on. */
Mario Scheithauer4125dde2017-05-08 12:49:58 +020072 PAD_CFG_GPO(GPIO_183, 1, DEEP), /* SDIO_PWR_DOWN_N */
Mario Scheithauer2d981202017-03-27 13:25:57 +020073
74 /* SMBus */
Mario Scheithauer0e1a5262018-08-22 14:43:24 +020075 PAD_CFG_GPI(SMB_ALERTB, NONE, DEEP), /* SMB_ALERT _N */
76 PAD_CFG_NF(SMB_CLK, NONE, DEEP, NF1), /* SMB_CLK */
77 PAD_CFG_NF(SMB_DATA, NONE, DEEP, NF1), /* SMB_DATA */
Mario Scheithauer2d981202017-03-27 13:25:57 +020078
79 /* LPC */
Mario Scheithauer0e1a5262018-08-22 14:43:24 +020080 PAD_CFG_NF(LPC_ILB_SERIRQ, NONE, DEEP, NF1), /* LPC_SERIRQ */
Mario Scheithauer2d981202017-03-27 13:25:57 +020081 PAD_CFG_NF(LPC_CLKOUT0, NONE, DEEP, NF1), /* LPC_CLKOUT0 */
82 PAD_CFG_GPI(LPC_CLKOUT1, UP_20K, DEEP), /* LPC_CLKOUT1 */
Mario Scheithauer0e1a5262018-08-22 14:43:24 +020083 PAD_CFG_NF(LPC_AD0, NONE, DEEP, NF1), /* LPC_AD0 */
84 PAD_CFG_NF(LPC_AD1, NONE, DEEP, NF1), /* LPC_AD1 */
85 PAD_CFG_NF(LPC_AD2, NONE, DEEP, NF1), /* LPC_AD2 */
86 PAD_CFG_NF(LPC_AD3, NONE, DEEP, NF1), /* LPC_AD3 */
Mario Scheithauer403458e2018-08-22 13:03:55 +020087 PAD_CFG_NF(LPC_CLKRUNB, NONE, DEEP, NF1), /* LPC_CLKRUN_N */
Mario Scheithauer0e1a5262018-08-22 14:43:24 +020088 PAD_CFG_NF(LPC_FRAMEB, NONE, DEEP, NF1), /* LPC_FRAME_N */
Mario Scheithauer2d981202017-03-27 13:25:57 +020089
90 /* West Community */
91
92 /* I2C0 - I2C Level Shifter */
Mario Scheithauer0e1a5262018-08-22 14:43:24 +020093 PAD_CFG_NF(GPIO_124, NONE, DEEP, NF1), /* LPSS_I2C0_SDA */
94 PAD_CFG_NF(GPIO_125, NONE, DEEP, NF1), /* LPSS_I2C0_SCL */
Mario Scheithauer2d981202017-03-27 13:25:57 +020095
96 /* I2C[1:7] -- unused */
97 PAD_CFG_GPI(GPIO_126, UP_20K, DEEP), /* LPSS_I2C1_SDA */
98 PAD_CFG_GPI(GPIO_127, UP_20K, DEEP), /* LPSS_I2C1_SCL */
99 PAD_CFG_GPI(GPIO_128, UP_20K, DEEP), /* LPSS_I2C2_SDA */
100 PAD_CFG_GPI(GPIO_129, UP_20K, DEEP), /* LPSS_I2C2_SCL */
101 PAD_CFG_GPI(GPIO_130, UP_20K, DEEP), /* LPSS_I2C3_SDA */
102 PAD_CFG_GPI(GPIO_131, UP_20K, DEEP), /* LPSS_I2C3_SCL */
103 PAD_CFG_GPI(GPIO_132, UP_20K, DEEP), /* LPSS_I2C4_SDA */
104 PAD_CFG_GPI(GPIO_133, UP_20K, DEEP), /* LPSS_I2C4_SCL */
105 PAD_CFG_GPI(GPIO_134, UP_20K, DEEP), /* LPSS_I2C5_SDA */
106 PAD_CFG_GPI(GPIO_135, UP_20K, DEEP), /* LPSS_I2C5_SCL */
107 PAD_CFG_GPI(GPIO_136, UP_20K, DEEP), /* LPSS_I2C6_SDA */
108 PAD_CFG_GPI(GPIO_137, UP_20K, DEEP), /* LPSS_I2C6_SCL */
109 PAD_CFG_GPI(GPIO_138, UP_20K, DEEP), /* LPSS_I2C7_SDA */
110 PAD_CFG_GPI(GPIO_139, UP_20K, DEEP), /* LPSS_I2C7_SCL */
111
112 /* ISH_GPIO_[0:9] -- unused */
113 PAD_CFG_GPI(GPIO_146, DN_20K, DEEP), /* ISH_GPIO_0 */
114 PAD_CFG_GPI(GPIO_147, DN_20K, DEEP), /* ISH_GPIO_1 */
115 PAD_CFG_GPI(GPIO_148, DN_20K, DEEP), /* ISH_GPIO_2 */
116 PAD_CFG_GPI(GPIO_149, DN_20K, DEEP), /* ISH_GPIO_3 */
117 PAD_CFG_GPI(GPIO_150, DN_20K, DEEP), /* ISH_GPIO_4 */
118 PAD_CFG_GPI(GPIO_151, DN_20K, DEEP), /* ISH_GPIO_5 */
119 PAD_CFG_GPI(GPIO_152, DN_20K, DEEP), /* ISH_GPIO_6 */
120 PAD_CFG_GPI(GPIO_153, DN_20K, DEEP), /* ISH_GPIO_7 */
121 PAD_CFG_GPI(GPIO_154, DN_20K, DEEP), /* ISH_GPIO_8 */
122 PAD_CFG_GPI(GPIO_155, DN_20K, DEEP), /* ISH_GPIO_9 */
123
124 /* PCIE_CLKREQ[0:3]_N */
Mario Scheithauer0e1a5262018-08-22 14:43:24 +0200125 PAD_CFG_NF(GPIO_209, NONE, DEEP, NF1),
126 PAD_CFG_NF(GPIO_210, NONE, DEEP, NF1),
127 PAD_CFG_NF(GPIO_211, NONE, DEEP, NF1),
128 PAD_CFG_NF(GPIO_212, NONE, DEEP, NF1),
Mario Scheithauer2d981202017-03-27 13:25:57 +0200129
130 /* OSC_CLK_OUT_0 - RES_CLK_CPU_FPGA */
131 PAD_CFG_NF(OSC_CLK_OUT_0, DN_20K, DEEP, NF1),
132 /* OSC_CLK_OUT_[1:4] -- unused */
133 PAD_CFG_GPI(OSC_CLK_OUT_1, DN_20K, DEEP),
134 PAD_CFG_GPI(OSC_CLK_OUT_2, DN_20K, DEEP),
135 PAD_CFG_GPI(OSC_CLK_OUT_3, DN_20K, DEEP),
136 PAD_CFG_GPI(OSC_CLK_OUT_4, DN_20K, DEEP),
137
138 /* PMU Signals */
Mario Scheithauer0e1a5262018-08-22 14:43:24 +0200139 PAD_CFG_GPI(PMU_AC_PRESENT, NONE, DEEP), /* PMU_AC_PRESENT */
Mario Scheithauer2d981202017-03-27 13:25:57 +0200140 PAD_CFG_NF(PMU_BATLOW_B, UP_20K, DEEP, NF1), /* PMU_BATLOW_N */
141 PAD_CFG_NF(PMU_PLTRST_B, NONE, DEEP, NF1), /* PMU_PLTRST_N */
Mario Scheithauer0e1a5262018-08-22 14:43:24 +0200142 PAD_CFG_NF(PMU_PWRBTN_B, NONE, DEEP, NF1), /* PMU_PWRBTN_N */
Mario Scheithauer2d981202017-03-27 13:25:57 +0200143 PAD_CFG_NF(PMU_RESETBUTTON_B, NONE, DEEP, NF1), /* PMU_RSTBTN_N */
144 /* PMU_SLP_S0_N */
145 PAD_CFG_NF_IOSSTATE(PMU_SLP_S0_B, NONE, DEEP, NF1, IGNORE),
146 PAD_CFG_NF(PMU_SLP_S3_B, NONE, DEEP, NF1), /* PMU_SLP_S3_N */
147 PAD_CFG_NF(PMU_SLP_S4_B, NONE, DEEP, NF1), /* PMU_SLP_S4_N */
148 PAD_CFG_NF(PMU_SUSCLK, NONE, DEEP, NF1), /* PMU_SUSCLK */
149 PAD_CFG_GPO(PMU_WAKE_B, 1, DEEP), /* EN_PP3300_EMMC */
150 PAD_CFG_NF(SUS_STAT_B, NONE, DEEP, NF1), /* SUS_STAT_N */
151 PAD_CFG_NF(SUSPWRDNACK, NONE, DEEP, NF1), /* SUSPWRDNACK */
152
153 /* Northwest Community */
154
155 /* DDI0 SDA and SCL -- unused */
156 PAD_CFG_GPI(GPIO_187, DN_20K, DEEP), /* HV_DDI0_DDC_SDA */
157 PAD_CFG_GPI(GPIO_188, DN_20K, DEEP), /* HV_DDI0_DDC_SCL */
158 /* DDI1 SDA and SCL - Display-Port */
Mario Scheithauer0e1a5262018-08-22 14:43:24 +0200159 PAD_CFG_NF(GPIO_189, NONE, DEEP, NF1), /* HV_DDI1_DDC_SDA */
160 PAD_CFG_NF(GPIO_190, NONE, DEEP, NF1), /* HV_DDI1_DDC_SCL */
Mario Scheithauer2d981202017-03-27 13:25:57 +0200161
162 /* MIPI I2C -- unused */
163 PAD_CFG_GPI(GPIO_191, DN_20K, DEEP), /* MIPI_I2C_SDA */
164 PAD_CFG_GPI(GPIO_192, DN_20K, DEEP), /* MIPI_I2C_SCL */
165
166 /* Panel 0 control -- unused */
Mario Scheithauer0e1a5262018-08-22 14:43:24 +0200167 PAD_CFG_TERM_GPO(GPIO_193, 0, DN_20K, DEEP), /* PNL0_VDDEN */
168 PAD_CFG_TERM_GPO(GPIO_194, 0, DN_20K, DEEP), /* PNL0_BKLTEN */
169 PAD_CFG_TERM_GPO(GPIO_195, 0, DN_20K, DEEP), /* PNL0_BKLTCTL */
Mario Scheithauer2d981202017-03-27 13:25:57 +0200170
171 /* Panel 1 control -- unused */
Mario Scheithauer0e1a5262018-08-22 14:43:24 +0200172 PAD_CFG_GPI(GPIO_196, DN_20K, DEEP), /* PNL1_VDDEN */
173 PAD_CFG_GPI(GPIO_197, DN_20K, DEEP), /* PNL1_BKLTEN */
174 PAD_CFG_GPI(GPIO_198, DN_20K, DEEP), /* PNL1_BKLTCTL */
Mario Scheithauer2d981202017-03-27 13:25:57 +0200175
176 /* DDI[0:1]_HPD -- unused */
Mario Scheithauer0e1a5262018-08-22 14:43:24 +0200177 PAD_CFG_GPI(GPIO_199, NONE, DEEP), /* XHPD_DP */
Mario Scheithauer2d981202017-03-27 13:25:57 +0200178 PAD_CFG_GPI(GPIO_200, DN_20K, DEEP), /* unused */
179
180 /* MDSI signals -- unused */
181 PAD_CFG_GPI(GPIO_201, DN_20K, DEEP), /* MDSI_A_TE */
182 PAD_CFG_GPI(GPIO_202, DN_20K, DEEP), /* MDSI_C_TE */
183
184 /* USB overcurrent pins. */
Mario Scheithauer0e1a5262018-08-22 14:43:24 +0200185 PAD_CFG_NF(GPIO_203, NONE, DEEP, NF1), /* USB_OC0_N */
186 PAD_CFG_NF(GPIO_204, NONE, DEEP, NF1), /* USB_OC1_N */
Mario Scheithauer2d981202017-03-27 13:25:57 +0200187
188 /* PMC SPI -- almost entirely unused. */
189 PAD_CFG_GPI(PMC_SPI_FS0, UP_20K, DEEP),
Mario Scheithauer0e1a5262018-08-22 14:43:24 +0200190 PAD_CFG_NF(PMC_SPI_FS1, NONE, DEEP, NF2), /* XHPD_EDP_APL */
Mario Scheithauer2d981202017-03-27 13:25:57 +0200191 PAD_CFG_GPI(PMC_SPI_FS2, UP_20K, DEEP),
192 PAD_CFG_GPI(PMC_SPI_RXD, DN_20K, DEEP),
193 PAD_CFG_GPI(PMC_SPI_TXD, DN_20K, DEEP),
194 PAD_CFG_GPI(PMC_SPI_CLK, DN_20K, DEEP),
195
196 /* PMIC Signals unused signals related to an old PMIC interface. */
197 PAD_CFG_GPO(PMIC_PWRGOOD, 1, DEEP), /* PMIC_PWRGOOD */
Mario Scheithauer0e1a5262018-08-22 14:43:24 +0200198 PAD_CFG_GPI(PMIC_RESET_B, DN_20K, DEEP), /* PMIC_RESET_B */
199 PAD_CFG_TERM_GPO(GPIO_213, 0, DN_20K, DEEP), /* NFC_OUT_RESERVE */
200 PAD_CFG_TERM_GPO(GPIO_214, 0, DN_20K, DEEP), /* NFC_EN */
Mario Scheithauer2d981202017-03-27 13:25:57 +0200201 PAD_CFG_GPI(GPIO_215, DN_20K, DEEP), /* NFC_IN_RESERVE */
202 /* THERMTRIP_N */
203 PAD_CFG_NF(PMIC_THERMTRIP_B, UP_20K, DEEP, NF1),
Mario Scheithauer0e1a5262018-08-22 14:43:24 +0200204 PAD_CFG_GPO(PMIC_STDBY, 0, DEEP), /* unused */
205 PAD_CFG_NF(PROCHOT_B, NONE, DEEP, NF1), /* PROCHOT_N */
206 PAD_CFG_NF(PMIC_I2C_SCL, NONE, DEEP, NF1), /* PMIC_I2C_SCL */
207 PAD_CFG_NF(PMIC_I2C_SDA, NONE, DEEP, NF1), /* PMIC_I2C_SDA */
Mario Scheithauer2d981202017-03-27 13:25:57 +0200208
209 /* I2S1 -- unused */
210 PAD_CFG_GPI(GPIO_74, DN_20K, DEEP), /* I2S1_MCLK */
211 PAD_CFG_GPI(GPIO_75, DN_20K, DEEP), /* I2S1_BCLK */
212 PAD_CFG_GPI(GPIO_76, DN_20K, DEEP), /* I2S1_WS_SYNC */
213 PAD_CFG_GPI(GPIO_77, DN_20K, DEEP), /* I2S1_SDI */
214 PAD_CFG_GPI(GPIO_78, DN_20K, DEEP), /* I2S1_SDO */
215
216 /* DMIC or I2S4 -- unused */
217 PAD_CFG_GPI(GPIO_79, DN_20K, DEEP), /* AVS_M_CLK_A1 */
218 PAD_CFG_GPI(GPIO_80, DN_20K, DEEP), /* AVS_M_CLK_B1 */
219 PAD_CFG_GPI(GPIO_81, DN_20K, DEEP), /* AVS_M_DATA_1 */
220 PAD_CFG_GPI(GPIO_82, DN_20K, DEEP), /* AVS_M_CLK_AB2 */
221 PAD_CFG_GPI(GPIO_83, DN_20K, DEEP), /* AVS_M_DATA_2 */
222
223 /* I2S2 -- unused */
224 PAD_CFG_GPI(GPIO_84, DN_20K, DEEP), /* AVS_I2S2_MCLK */
225 PAD_CFG_GPI(GPIO_85, DN_20K, DEEP), /* AVS_I2S2_BCLK */
226 PAD_CFG_GPI(GPIO_86, DN_20K, DEEP), /* AVS_I2S2_WS_SYNC */
227 PAD_CFG_GPI(GPIO_87, DN_20K, DEEP), /* AVS_I2S2_SDI */
228 PAD_CFG_GPI(GPIO_88, DN_20K, DEEP), /* AVS_I2S2_SDO */
229
230 /* I2S3 -- unused */
231 PAD_CFG_GPI(GPIO_89, DN_20K, DEEP), /* AVS_I2S3_BCLK */
232 PAD_CFG_GPI(GPIO_90, DN_20K, DEEP), /* AVS_I2S3_WS_SYNC */
233 PAD_CFG_GPI(GPIO_91, DN_20K, DEEP), /* AVS_I2S3_SDI */
234 PAD_CFG_GPI(GPIO_92, DN_20K, DEEP), /* AVS_I2S3_SDO */
235
236 /* Fast SPI */
237 /* FST_SPI_CS0_B */
238 PAD_CFG_NF_IOSSTATE(GPIO_97, NATIVE, DEEP, NF1, IGNORE),
239 /* FST_SPI_CS1_B -- unused */
240 PAD_CFG_GPI(GPIO_98, DN_20K, DEEP),
241 /* FST_SPI_MOSI_IO0 */
242 PAD_CFG_NF_IOSSTATE(GPIO_99, NATIVE, DEEP, NF1, IGNORE),
243 /* FST_SPI_MISO_IO1 */
244 PAD_CFG_NF_IOSSTATE(GPIO_100, NATIVE, DEEP, NF1, IGNORE),
245 /* FST_IO2 -- MEM_CONFIG0 */
246 PAD_CFG_NF(GPIO_101, NATIVE, DEEP, NF1),
247 /* FST_IO3 -- MEM_CONFIG1 */
248 PAD_CFG_NF(GPIO_102, NATIVE, DEEP, NF1),
249 /* FST_SPI_CLK */
250 PAD_CFG_NF_IOSSTATE(GPIO_103, NATIVE, DEEP, NF1, IGNORE),
251 /* FST_SPI_CLK_FB */
252 PAD_CFG_NF_IOSSTATE(FST_SPI_CLK_FB, NATIVE, DEEP, NF1, IGNORE),
253
254 /* SIO_SPI_0 -- unused */
255 PAD_CFG_GPI(GPIO_104, DN_20K, DEEP), /* GP_SSP_0_CLK */
256 PAD_CFG_GPI(GPIO_105, DN_20K, DEEP), /* GP_SSP_0_FS0 */
257 PAD_CFG_GPI(GPIO_106, UP_20K, DEEP), /* GP_SSP_0_FS1 */
258 PAD_CFG_GPI(GPIO_109, DN_20K, DEEP), /* GP_SSP_0_RXD */
259 PAD_CFG_GPI(GPIO_110, DN_20K, DEEP), /* GP_SSP_0_TXD */
260
261 /* SIO_SPI_1 -- unused */
262 PAD_CFG_GPI(GPIO_111, DN_20K, DEEP), /* GP_SSP_1_CLK */
263 PAD_CFG_GPI(GPIO_112, DN_20K, DEEP), /* GP_SSP_1_FS0 */
264 PAD_CFG_GPI(GPIO_113, DN_20K, DEEP), /* GP_SSP_1_FS1 */
265 PAD_CFG_GPI(GPIO_116, DN_20K, DEEP), /* GP_SSP_1_RXD */
266 PAD_CFG_GPI(GPIO_117, DN_20K, DEEP), /* GP_SSP_1_TXD */
267
268 /* SIO_SPI_2 -- unused */
269 PAD_CFG_GPI(GPIO_118, DN_20K, DEEP), /* GP_SSP_2_CLK */
270 PAD_CFG_GPI(GPIO_119, DN_20K, DEEP), /* GP_SSP_2_FS0 */
271 PAD_CFG_GPI(GPIO_120, DN_20K, DEEP), /* GP_SSP_2_FS1 */
272 PAD_CFG_GPI(GPIO_121, DN_20K, DEEP), /* GP_SSP_2_FS2 */
273 PAD_CFG_GPI(GPIO_122, DN_20K, DEEP), /* GP_SSP_2_RXD */
Mario Scheithauer0e1a5262018-08-22 14:43:24 +0200274 PAD_CFG_GPI(GPIO_123, NONE, DEEP), /* GP_SSP_2_TXD */
Mario Scheithauer2d981202017-03-27 13:25:57 +0200275
276 /* North Community */
277
278 /* Debug tracing. */
279 PAD_CFG_GPI(GPIO_0, DN_20K, DEEP), /* TRACE_0_CLK_VNN */
280 PAD_CFG_GPI(GPIO_1, DN_20K, DEEP), /* TRACE_0_DATA0_VNN */
281 PAD_CFG_GPI(GPIO_2, DN_20K, DEEP), /* TRACE_0_DATA1_VNN */
282 PAD_CFG_GPI(GPIO_3, DN_20K, DEEP), /* TRACE_0_DATA2_VNN */
283 PAD_CFG_GPI(GPIO_4, DN_20K, DEEP), /* TRACE_0_DATA3_VNN */
284 PAD_CFG_GPI(GPIO_5, DN_20K, DEEP), /* TRACE_0_DATA4_VNN */
285 PAD_CFG_GPI(GPIO_6, DN_20K, DEEP), /* TRACE_0_DATA5_VNN */
286 PAD_CFG_GPI(GPIO_7, DN_20K, DEEP), /* TRACE_0_DATA6_VNN */
287 PAD_CFG_GPI(GPIO_8, DN_20K, DEEP), /* TRACE_0_DATA7_VNN */
288
289 PAD_CFG_GPI(GPIO_9, DN_20K, DEEP), /* TRACE_1_CLK_VNN */
290 PAD_CFG_GPI(GPIO_10, DN_20K, DEEP), /* TRACE_1_DATA0_VNN */
291 PAD_CFG_GPI(GPIO_11, DN_20K, DEEP), /* TRACE_1_DATA1_VNN */
292 PAD_CFG_GPI(GPIO_12, DN_20K, DEEP), /* TRACE_1_DATA2_VNN */
293 PAD_CFG_GPI(GPIO_13, DN_20K, DEEP), /* TRACE_1_DATA3_VNN */
294 PAD_CFG_GPI(GPIO_14, DN_20K, DEEP), /* TRACE_1_DATA4_VNN */
295 PAD_CFG_GPI(GPIO_15, DN_20K, DEEP), /* TRACE_1_DATA5_VNN */
296 PAD_CFG_GPI(GPIO_16, DN_20K, DEEP), /* TRACE_1_DATA6_VNN */
297 PAD_CFG_GPI(GPIO_17, DN_20K, DEEP), /* TRACE_1_DATA7_VNN */
298
Mario Scheithauer0e1a5262018-08-22 14:43:24 +0200299 PAD_CFG_GPI(GPIO_18, DN_20K, DEEP), /* TRACE_2_CLK_VNN */
300 PAD_CFG_GPI(GPIO_19, DN_20K, DEEP), /* TRACE_2_DATA0_VNN */
Mario Scheithauer2d981202017-03-27 13:25:57 +0200301 PAD_CFG_GPI(GPIO_20, DN_20K, DEEP), /* TRACE_2_DATA1_VNN */
302 PAD_CFG_GPI(GPIO_21, DN_20K, DEEP), /* TRACE_2_DATA2_VNN */
303 PAD_CFG_GPI(GPIO_22, DN_20K, DEEP), /* TRACE_2_DATA3_VNN */
304 PAD_CFG_GPI(GPIO_23, DN_20K, DEEP), /* TRACE_2_DATA4_VNN */
305 PAD_CFG_GPI(GPIO_24, DN_20K, DEEP), /* TRACE_2_DATA5_VNN */
306 PAD_CFG_GPI(GPIO_25, DN_20K, DEEP), /* TRACE_2_DATA6_VNN */
307 PAD_CFG_GPI(GPIO_26, DN_20K, DEEP), /* TRACE_2_DATA7_VNN */
308
309 PAD_CFG_GPI(GPIO_27, DN_20K, DEEP), /* TRIGOUT_0 */
310 PAD_CFG_GPI(GPIO_28, DN_20K, DEEP), /* TRIGOUT_1 */
311 PAD_CFG_GPI(GPIO_29, DN_20K, DEEP), /* TRIGIN_0 */
312
313 PAD_CFG_GPI(GPIO_30, DN_20K, DEEP), /* ISH_GPIO_12 */
Mario Scheithauer0e1a5262018-08-22 14:43:24 +0200314 PAD_CFG_GPO(GPIO_31, 1, DEEP), /* ISH_GPIO_13 */
315 PAD_CFG_GPI(GPIO_32, NONE, DEEP), /* ISH_GPIO_14 */
Mario Scheithauer2d981202017-03-27 13:25:57 +0200316 PAD_CFG_GPI(GPIO_33, DN_20K, DEEP), /* ISH_GPIO_15 */
317
318 /* PWM[0:3] -- unused */
319 PAD_CFG_GPI(GPIO_34, DN_20K, DEEP),
320 PAD_CFG_GPI(GPIO_35, DN_20K, DEEP),
321 PAD_CFG_GPI(GPIO_36, DN_20K, DEEP),
322 PAD_CFG_GPI(GPIO_37, DN_20K, DEEP),
323
324 /* LPSS_UART[0:2] */
325 PAD_CFG_GPI(GPIO_38, UP_20K, DEEP), /* LPSS_UART0_RXD - unused */
326 PAD_CFG_GPI(GPIO_39, DN_20K, DEEP), /* LPSS_UART0_TXD - unused */
327 PAD_CFG_GPI(GPIO_40, DN_20K, DEEP), /* LPSS_UART0_RTS - unused */
328 PAD_CFG_GPI(GPIO_41, UP_20K, DEEP), /* LPSS_UART0_CTS - unused */
Mario Scheithauer0e1a5262018-08-22 14:43:24 +0200329 PAD_CFG_GPI(GPIO_42, NONE, DEEP), /* LPSS_UART1_RXD - unused */
Mario Scheithauer2d981202017-03-27 13:25:57 +0200330 PAD_CFG_GPI(GPIO_43, DN_20K, DEEP), /* LPSS_UART1_TXD - unused */
331 PAD_CFG_GPI(GPIO_44, UP_20K, DEEP), /* LPSS_UART1_RTS - unused */
332 PAD_CFG_GPI(GPIO_45, UP_20K, DEEP), /* LPSS_UART1_CTS - unused */
333 PAD_CFG_NF(GPIO_46, NATIVE, DEEP, NF1), /* LPSS_UART2_RXD */
334 /* LPSS_UART2_TXD */
Furquan Shaikh6bedbd62018-10-04 11:11:49 -0700335 PAD_CFG_NF_IOSSTATE(GPIO_47, NATIVE, DEEP, NF1, Tx1RxDCRx0),
Mario Scheithauer2d981202017-03-27 13:25:57 +0200336 PAD_CFG_GPI(GPIO_48, DN_20K, DEEP), /* LPSS_UART2_RTS - unused */
337 PAD_CFG_GPI(GPIO_49, UP_20K, DEEP), /* LPSS_UART2_CTS - unused */
338
339 /* Camera interface -- completely unused. */
340 PAD_CFG_GPI(GPIO_62, DN_20K, DEEP), /* GP_CAMERASB00 */
341 PAD_CFG_GPI(GPIO_63, DN_20K, DEEP), /* GP_CAMERASB01 */
342 PAD_CFG_GPI(GPIO_64, DN_20K, DEEP), /* GP_CAMERASB02 */
343 PAD_CFG_GPI(GPIO_65, DN_20K, DEEP), /* GP_CAMERASB03 */
344 PAD_CFG_GPI(GPIO_66, DN_20K, DEEP), /* GP_CAMERASB04 */
345 PAD_CFG_GPI(GPIO_67, DN_20K, DEEP), /* GP_CAMERASB05 */
346 PAD_CFG_GPI(GPIO_68, DN_20K, DEEP), /* GP_CAMERASB06 */
347 PAD_CFG_GPI(GPIO_69, DN_20K, DEEP), /* GP_CAMERASB07 */
348 PAD_CFG_GPI(GPIO_70, DN_20K, DEEP), /* GP_CAMERASB08 */
349 PAD_CFG_GPI(GPIO_71, DN_20K, DEEP), /* GP_CAMERASB09 */
350 PAD_CFG_GPI(GPIO_72, DN_20K, DEEP), /* GP_CAMERASB10 */
351 PAD_CFG_GPI(GPIO_73, DN_20K, DEEP), /* GP_CAMERASB11 */
352
Mario Scheithauer2d981202017-03-27 13:25:57 +0200353 /* CNV bridge described into IAFW Vol2. */
354 /* GPIO_[216:219] described into EDS Vol1. */
355 PAD_CFG_GPO(CNV_BRI_DT, 0, DEEP), /* Reserve of FPGA */
356 PAD_CFG_GPO(CNV_BRI_RSP, 0, DEEP), /* Reserve of FPGA */
357 PAD_CFG_GPO(CNV_RGI_DT, 0, DEEP), /* Reserve of FPGA */
358 PAD_CFG_NF(CNV_RGI_RSP, UP_20K, DEEP, NF1), /* eMMC */
359
360 /* Serial VID */
361 PAD_CFG_NF(SVID0_ALERT_B, NONE, DEEP, NF1), /* SVID0_ALERT_B */
362 PAD_CFG_NF(SVID0_DATA, UP_20K, DEEP, NF1), /* SVID0_DATA */
363 PAD_CFG_NF(SVID0_CLK, UP_20K, DEEP, NF1), /* SVID0_CLK */
364};
365
Mario Scheithauerd127be12018-04-23 10:55:39 +0200366const struct pad_config *__weak variant_gpio_table(size_t *num)
Mario Scheithauer2d981202017-03-27 13:25:57 +0200367{
368 *num = ARRAY_SIZE(gpio_table);
369 return gpio_table;
370}
371
372/* GPIOs needed prior to ramstage. */
373static const struct pad_config early_gpio_table[] = {
374
375 /* Debug tracing. */
376 PAD_CFG_GPI(GPIO_0, DN_20K, DEEP), /* TRACE_0_CLK_VNN */
377 PAD_CFG_GPI(GPIO_1, DN_20K, DEEP), /* TRACE_0_DATA0_VNN */
378 PAD_CFG_GPI(GPIO_2, DN_20K, DEEP), /* TRACE_0_DATA1_VNN */
379 PAD_CFG_GPI(GPIO_3, DN_20K, DEEP), /* TRACE_0_DATA2_VNN */
380 PAD_CFG_GPI(GPIO_4, DN_20K, DEEP), /* TRACE_0_DATA3_VNN */
381 PAD_CFG_GPI(GPIO_5, DN_20K, DEEP), /* TRACE_0_DATA4_VNN */
382 PAD_CFG_GPI(GPIO_6, DN_20K, DEEP), /* TRACE_0_DATA5_VNN */
383 PAD_CFG_GPI(GPIO_7, DN_20K, DEEP), /* TRACE_0_DATA6_VNN */
384 PAD_CFG_GPI(GPIO_8, DN_20K, DEEP), /* TRACE_0_DATA7_VNN */
385
386 PAD_CFG_GPO(GPIO_13, 0, DEEP), /* PERST# */
387 PAD_CFG_GPO(GPIO_15, 0, DEEP), /* PERST# */
388 PAD_CFG_GPO(GPIO_17, 1, DEEP), /* PFET */
389 PAD_CFG_GPO(GPIO_19, 1, DEEP), /* PFET */
390 PAD_CFG_GPO(GPIO_152, 0, DEEP), /* PERST# */
391
392 /* SMBus */
Mario Scheithauer0e1a5262018-08-22 14:43:24 +0200393 PAD_CFG_NF(SMB_CLK, NONE, DEEP, NF1), /* SMB_CLK */
394 PAD_CFG_NF(SMB_DATA, NONE, DEEP, NF1), /* SMB_DATA */
Mario Scheithauer2d981202017-03-27 13:25:57 +0200395
396 /* LPC */
Mario Scheithauer0e1a5262018-08-22 14:43:24 +0200397 PAD_CFG_NF(LPC_ILB_SERIRQ, NONE, DEEP, NF1), /* LPC_SERIRQ */
398 PAD_CFG_NF(LPC_CLKOUT0, NONE, DEEP, NF1), /* LPC_CLKOUT0 */
Mario Scheithauer2d981202017-03-27 13:25:57 +0200399 /* LPC_CLKOUT1 - unused */
400 PAD_CFG_GPI(LPC_CLKOUT1, DN_20K, DEEP),
Mario Scheithauer0e1a5262018-08-22 14:43:24 +0200401 PAD_CFG_NF(LPC_AD0, NONE, DEEP, NF1), /* LPC_AD0 */
402 PAD_CFG_NF(LPC_AD1, NONE, DEEP, NF1), /* LPC_AD1 */
403 PAD_CFG_NF(LPC_AD2, NONE, DEEP, NF1), /* LPC_AD2 */
404 PAD_CFG_NF(LPC_AD3, NONE, DEEP, NF1), /* LPC_AD3 */
Mario Scheithauer403458e2018-08-22 13:03:55 +0200405 PAD_CFG_NF(LPC_CLKRUNB, NONE, DEEP, NF1), /* LPC_CLKRUN_N */
Mario Scheithauer0e1a5262018-08-22 14:43:24 +0200406 PAD_CFG_NF(LPC_FRAMEB, NONE, DEEP, NF1), /* LPC_FRAME_N */
Mario Scheithauer2d981202017-03-27 13:25:57 +0200407};
408
Aaron Durbin64031672018-04-21 14:45:32 -0600409const struct pad_config *__weak
Mario Scheithauerd127be12018-04-23 10:55:39 +0200410variant_early_gpio_table(size_t *num)
Mario Scheithauer2d981202017-03-27 13:25:57 +0200411{
412 *num = ARRAY_SIZE(early_gpio_table);
413 return early_gpio_table;
414}