Angel Pons | 381c4eb | 2020-04-03 01:22:06 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Kyösti Mälkki | e75deb6 | 2014-06-26 09:12:54 +0300 | [diff] [blame] | 2 | |
| 3 | #include <console/console.h> |
| 4 | #include <device/device.h> |
Kyösti Mälkki | f7ca672 | 2017-09-10 06:30:54 +0300 | [diff] [blame] | 5 | |
Stefan Reinauer | 13e4182 | 2015-04-27 14:02:36 -0700 | [diff] [blame] | 6 | #include <southbridge/amd/common/amd_pci_util.h> |
Dave Frodin | 83405a1 | 2014-06-05 11:49:04 -0600 | [diff] [blame] | 7 | #include <southbridge/amd/agesa/hudson/pci_devs.h> |
| 8 | #include <northbridge/amd/agesa/family16kb/pci_devs.h> |
| 9 | |
Dave Frodin | 83405a1 | 2014-06-05 11:49:04 -0600 | [diff] [blame] | 10 | /*********************************************************** |
| 11 | * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01. |
| 12 | * This table is responsible for physically routing the PIC and |
| 13 | * IOAPIC IRQs to the different PCI devices on the system. It |
| 14 | * is read and written via registers 0xC00/0xC01 as an |
| 15 | * Index/Data pair. These values are chipset and mainboard |
| 16 | * dependent and should be updated accordingly. |
| 17 | * |
| 18 | * These values are used by the PCI configuration space, |
| 19 | * MP Tables. TODO: Make ACPI use these values too. |
| 20 | */ |
| 21 | static const u8 mainboard_picr_data[FCH_INT_TABLE_SIZE] = { |
| 22 | [0x00] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,0x0A,0x0B, /* INTA# - INTH# */ |
| 23 | [0x08] = 0x00,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */ |
| 24 | [0x10] = 0x1F,0x1F,0x1F,0x0A,0x1F,0x1F,0x1F,0x0A, /* SCI, SMBUS0, ASF, HDA, FC, GEC, PerfMon, SD */ |
| 25 | [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, /* IMC INT0 - 5 */ |
| 26 | [0x30] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,0x0A, /* USB Devs 18/19/20/22 INTA-C */ |
| 27 | [0x40] = 0x0B,0x0B, /* IDE, SATA */ |
| 28 | }; |
| 29 | |
| 30 | static const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE] = { |
| 31 | [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */ |
| 32 | [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */ |
| 33 | [0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x12,0x1F,0x10, /* SCI, SMBUS0, ASF, HDA, FC, GEC, PerMon, SD */ |
| 34 | [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, /* IMC INT0 - 5 */ |
| 35 | [0x30] = 0x12,0x11,0x12,0x11,0x12,0x11,0x12, /* USB Devs 18/19/22/20 INTA-C */ |
| 36 | [0x40] = 0x11,0x13, /* IDE, SATA */ |
| 37 | }; |
| 38 | |
| 39 | /* |
| 40 | * This table defines the index into the picr/intr_data |
| 41 | * tables for each device. Any enabled device and slot |
| 42 | * that uses hardware interrupts should have an entry |
| 43 | * in this table to define its index into the FCH |
| 44 | * PCI_INTR register 0xC00/0xC01. This index will define |
| 45 | * the interrupt that it should use. Putting PIRQ_A into |
| 46 | * the PIN A index for a device will tell that device to |
| 47 | * use PIC IRQ 10 if it uses PIN A for its hardware INT. |
| 48 | */ |
| 49 | static const struct pirq_struct mainboard_pirq_data[] = { |
| 50 | /* {PCI_devfn, {PIN A, PIN B, PIN C, PIN D}}, */ |
| 51 | {GFX_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_NC, PIRQ_NC}}, /* VGA: 01.0 */ |
| 52 | {NB_PCIE_PORT2_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* NIC: 02.2 */ |
| 53 | {NB_PCIE_PORT3_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* NIC: 02.3 */ |
| 54 | {NB_PCIE_PORT4_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* NIC: 02.4 */ |
| 55 | {NB_PCIE_PORT5_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* NIC: 02.5 */ |
| 56 | {SATA_DEVFN, {PIRQ_SATA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SATA: 11.0 */ |
| 57 | {OHCI1_DEVFN, {PIRQ_OHCI1, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI1: 12.0 */ |
| 58 | {EHCI1_DEVFN, {PIRQ_NC, PIRQ_EHCI1, PIRQ_NC, PIRQ_NC}}, /* EHCI1: 12.2 */ |
| 59 | {OHCI2_DEVFN, {PIRQ_OHCI2, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI2: 13.0 */ |
| 60 | {EHCI2_DEVFN, {PIRQ_NC, PIRQ_EHCI2, PIRQ_NC, PIRQ_NC}}, /* EHCI2: 13.2 */ |
| 61 | {SMBUS_DEVFN, {PIRQ_SMBUS, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SMBUS: 14.0 */ |
| 62 | {HDA_DEVFN, {PIRQ_HDA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* HDA: 14.2 */ |
| 63 | {SB_PCI_PORT_DEVFN, {PIRQ_H, PIRQ_E, PIRQ_F, PIRQ_G}}, /* PCIB: 14.4 */ |
| 64 | {SD_DEVFN, {PIRQ_SD, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SD: 14.7 */ |
| 65 | {OHCI3_DEVFN, {PIRQ_OHCI3, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI3: 16.0 */ |
| 66 | {EHCI3_DEVFN, {PIRQ_NC, PIRQ_EHCI3, PIRQ_NC, PIRQ_NC}}, /* EHCI3: 16.2 */ |
| 67 | }; |
| 68 | |
| 69 | /* PIRQ Setup */ |
| 70 | static void pirq_setup(void) |
| 71 | { |
| 72 | pirq_data_ptr = mainboard_pirq_data; |
| 73 | pirq_data_size = sizeof(mainboard_pirq_data) / sizeof(struct pirq_struct); |
| 74 | intr_data_ptr = mainboard_intr_data; |
| 75 | picr_data_ptr = mainboard_picr_data; |
| 76 | } |
| 77 | |
Kyösti Mälkki | e75deb6 | 2014-06-26 09:12:54 +0300 | [diff] [blame] | 78 | /********************************************** |
Dave Frodin | 83405a1 | 2014-06-05 11:49:04 -0600 | [diff] [blame] | 79 | * Enable the dedicated functions of the board. |
Kyösti Mälkki | e75deb6 | 2014-06-26 09:12:54 +0300 | [diff] [blame] | 80 | **********************************************/ |
Elyes HAOUAS | 56f172d | 2018-05-04 20:41:40 +0200 | [diff] [blame] | 81 | static void mainboard_enable(struct device *dev) |
Kyösti Mälkki | e75deb6 | 2014-06-26 09:12:54 +0300 | [diff] [blame] | 82 | { |
| 83 | printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); |
| 84 | |
Dave Frodin | 83405a1 | 2014-06-05 11:49:04 -0600 | [diff] [blame] | 85 | /* Initialize the PIRQ data structures for consumption */ |
| 86 | pirq_setup(); |
Kyösti Mälkki | e75deb6 | 2014-06-26 09:12:54 +0300 | [diff] [blame] | 87 | } |
| 88 | |
| 89 | struct chip_operations mainboard_ops = { |
| 90 | .enable_dev = mainboard_enable, |
| 91 | }; |