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Subrata Banikfa7cc782017-11-27 18:23:36 +05301/*
2 * This file is part of the coreboot project.
3 *
praveen hodagatta praneshe26c4a42018-09-20 03:49:45 +08004 * Copyright (C) 2017-2018 Intel Corp.
Subrata Banikfa7cc782017-11-27 18:23:36 +05305 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
John Zhaoeac84ca2018-08-13 09:45:37 -070017#include <assert.h>
Subrata Banikfa7cc782017-11-27 18:23:36 +053018#include <console/console.h>
Kyösti Mälkki13f66502019-03-03 08:01:05 +020019#include <device/mmio.h>
Subrata Banikfa7cc782017-11-27 18:23:36 +053020#include <device/pci.h>
21#include <device/pci_ids.h>
22#include <intelblocks/graphics.h>
23#include <soc/pci_devs.h>
24
25/* SoC Overrides */
Aaron Durbin64031672018-04-21 14:45:32 -060026__weak void graphics_soc_init(struct device *dev)
Subrata Banikfa7cc782017-11-27 18:23:36 +053027{
28 /*
Jonathan Neuschäfer5268b762018-02-12 12:24:25 +010029 * User needs to implement SoC override in case wishes
Subrata Banikfa7cc782017-11-27 18:23:36 +053030 * to perform certain specific graphics initialization
31 * along with pci_dev_init(dev)
32 */
33 pci_dev_init(dev);
34}
35
Subrata Banik64e66802019-06-13 22:11:46 +053036static int is_graphics_disabled(struct device *dev)
Subrata Banikfa7cc782017-11-27 18:23:36 +053037{
Subrata Banikfa7cc782017-11-27 18:23:36 +053038 /* Check if Graphics PCI device is disabled */
John Zhaoeac84ca2018-08-13 09:45:37 -070039 if (!dev || !dev->enabled)
Subrata Banik64e66802019-06-13 22:11:46 +053040 return 1;
41
42 return 0;
43}
44
45static uintptr_t graphics_get_bar(struct device *dev, unsigned long index)
46{
47 struct resource *gm_res;
Subrata Banikfa7cc782017-11-27 18:23:36 +053048
49 gm_res = find_resource(dev, index);
50 if (!gm_res)
51 return 0;
52
53 return gm_res->base;
54}
55
56uintptr_t graphics_get_memory_base(void)
57{
Subrata Banik64e66802019-06-13 22:11:46 +053058 uintptr_t memory_base;
Kyösti Mälkki71756c212019-07-12 13:10:19 +030059 struct device *dev = pcidev_path_on_root(SA_DEVFN_IGD);
Subrata Banik64e66802019-06-13 22:11:46 +053060
61 if (is_graphics_disabled(dev))
62 return 0;
Subrata Banikfa7cc782017-11-27 18:23:36 +053063 /*
64 * GFX PCI config space offset 0x18 know as Graphics
65 * Memory Range Address (GMADR)
66 */
Subrata Banik64e66802019-06-13 22:11:46 +053067 memory_base = graphics_get_bar(dev, PCI_BASE_ADDRESS_2);
Subrata Banikfa7cc782017-11-27 18:23:36 +053068 if (!memory_base)
Keith Short15588b02019-05-09 11:40:34 -060069 die_with_post_code(POST_HW_INIT_FAILURE,
70 "GMADR is not programmed!");
Subrata Banikfa7cc782017-11-27 18:23:36 +053071
72 return memory_base;
73}
74
75static uintptr_t graphics_get_gtt_base(void)
76{
Subrata Banik64e66802019-06-13 22:11:46 +053077 static uintptr_t gtt_base;
Kyösti Mälkki71756c212019-07-12 13:10:19 +030078 struct device *dev = pcidev_path_on_root(SA_DEVFN_IGD);
Subrata Banik64e66802019-06-13 22:11:46 +053079
80 if (is_graphics_disabled(dev))
81 die("IGD is disabled!");
Subrata Banikfa7cc782017-11-27 18:23:36 +053082 /*
83 * GFX PCI config space offset 0x10 know as Graphics
84 * Translation Table Memory Mapped Range Address
85 * (GTTMMADR)
86 */
Subrata Banikfa7cc782017-11-27 18:23:36 +053087 if (!gtt_base) {
Subrata Banik64e66802019-06-13 22:11:46 +053088 gtt_base = graphics_get_bar(dev, PCI_BASE_ADDRESS_0);
Subrata Banikfa7cc782017-11-27 18:23:36 +053089 if (!gtt_base)
Keith Short15588b02019-05-09 11:40:34 -060090 die_with_post_code(POST_HW_INIT_FAILURE,
91 "GTTMMADR is not programmed!");
Subrata Banikfa7cc782017-11-27 18:23:36 +053092 }
93 return gtt_base;
94}
95
96uint32_t graphics_gtt_read(unsigned long reg)
97{
98 return read32((void *)(graphics_get_gtt_base() + reg));
99}
100
101void graphics_gtt_write(unsigned long reg, uint32_t data)
102{
103 write32((void *)(graphics_get_gtt_base() + reg), data);
104}
105
106void graphics_gtt_rmw(unsigned long reg, uint32_t andmask, uint32_t ormask)
107{
108 uint32_t val = graphics_gtt_read(reg);
109 val &= andmask;
110 val |= ormask;
111 graphics_gtt_write(reg, val);
112}
113
114static const struct device_operations graphics_ops = {
115 .read_resources = pci_dev_read_resources,
116 .set_resources = pci_dev_set_resources,
117 .enable_resources = pci_dev_enable_resources,
118 .init = graphics_soc_init,
Subrata Banik6bbc91a2017-12-07 14:55:51 +0530119 .ops_pci = &pci_dev_ops_pci,
Subrata Banikfa7cc782017-11-27 18:23:36 +0530120 .write_acpi_tables = graphics_soc_write_acpi_opregion,
121};
122
123static const unsigned short pci_device_ids[] = {
124 PCI_DEVICE_ID_INTEL_APL_IGD_HD_505,
125 PCI_DEVICE_ID_INTEL_APL_IGD_HD_500,
126 PCI_DEVICE_ID_INTEL_CNL_GT2_ULX_1,
127 PCI_DEVICE_ID_INTEL_CNL_GT2_ULX_2,
128 PCI_DEVICE_ID_INTEL_CNL_GT2_ULX_3,
129 PCI_DEVICE_ID_INTEL_CNL_GT2_ULX_4,
130 PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_1,
131 PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_2,
132 PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_3,
133 PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_4,
134 PCI_DEVICE_ID_INTEL_GLK_IGD,
135 PCI_DEVICE_ID_INTEL_GLK_IGD_EU12,
Lijian Zhao34745f62019-02-15 05:36:50 -0800136 PCI_DEVICE_ID_INTEL_WHL_GT1_ULT_1,
Krzysztof Sywulabf7ad372018-07-17 10:45:21 -0700137 PCI_DEVICE_ID_INTEL_WHL_GT2_ULT_1,
Subrata Banikfa7cc782017-11-27 18:23:36 +0530138 PCI_DEVICE_ID_INTEL_KBL_GT1_SULTM,
Maxim Polyakov85954692019-09-23 16:08:41 +0300139 PCI_DEVICE_ID_INTEL_KBL_GT1_SHALM_1,
140 PCI_DEVICE_ID_INTEL_KBL_GT1_SHALM_2,
141 PCI_DEVICE_ID_INTEL_KBL_GT1_SSRVM,
142 PCI_DEVICE_ID_INTEL_KBL_GT1F_DT2,
Subrata Banikfa7cc782017-11-27 18:23:36 +0530143 PCI_DEVICE_ID_INTEL_KBL_GT2_SULXM,
144 PCI_DEVICE_ID_INTEL_KBL_GT2_SULTM,
145 PCI_DEVICE_ID_INTEL_KBL_GT2_SULTMR,
Maxim Polyakov85954692019-09-23 16:08:41 +0300146 PCI_DEVICE_ID_INTEL_KBL_GT2_SSRVM,
147 PCI_DEVICE_ID_INTEL_KBL_GT2_SWSTM,
Subrata Banikfa7cc782017-11-27 18:23:36 +0530148 PCI_DEVICE_ID_INTEL_KBL_GT2_SHALM,
V Sowmyaacc2a482018-01-23 15:27:23 +0530149 PCI_DEVICE_ID_INTEL_KBL_GT2_DT2P2,
Maxim Polyakov85954692019-09-23 16:08:41 +0300150 PCI_DEVICE_ID_INTEL_KBL_GT2F_SULTM,
151 PCI_DEVICE_ID_INTEL_KBL_GT3E_SULTM_1,
152 PCI_DEVICE_ID_INTEL_KBL_GT3E_SULTM_2,
153 PCI_DEVICE_ID_INTEL_KBL_GT4_SHALM,
Gaggery Tsai8aee7f72018-08-03 11:40:55 -0700154 PCI_DEVICE_ID_INTEL_AML_GT2_ULX,
Maxim Polyakov95636812019-09-20 22:06:57 +0300155 PCI_DEVICE_ID_INTEL_SKL_GT1F_DT2,
Subrata Banikfa7cc782017-11-27 18:23:36 +0530156 PCI_DEVICE_ID_INTEL_SKL_GT1_SULTM,
Maxim Polyakov46e68522019-02-25 10:46:18 +0300157 PCI_DEVICE_ID_INTEL_SKL_GT2_DT2P1,
Subrata Banikfa7cc782017-11-27 18:23:36 +0530158 PCI_DEVICE_ID_INTEL_SKL_GT2_SULXM,
159 PCI_DEVICE_ID_INTEL_SKL_GT2_SULTM,
160 PCI_DEVICE_ID_INTEL_SKL_GT2_SHALM,
161 PCI_DEVICE_ID_INTEL_SKL_GT2_SWKSM,
Maxim Polyakov95636812019-09-20 22:06:57 +0300162 PCI_DEVICE_ID_INTEL_SKL_GT3_SULTM,
163 PCI_DEVICE_ID_INTEL_SKL_GT3E_SULTM_1,
164 PCI_DEVICE_ID_INTEL_SKL_GT3E_SULTM_2,
165 PCI_DEVICE_ID_INTEL_SKL_GT3FE_SSRVM,
Subrata Banikfa7cc782017-11-27 18:23:36 +0530166 PCI_DEVICE_ID_INTEL_SKL_GT4_SHALM,
Maxim Polyakov95636812019-09-20 22:06:57 +0300167 PCI_DEVICE_ID_INTEL_SKL_GT4E_SWSTM,
praveen hodagatta praneshe26c4a42018-09-20 03:49:45 +0800168 PCI_DEVICE_ID_INTEL_CFL_H_GT2,
Nico Huberff3c9642019-05-14 13:18:05 +0200169 PCI_DEVICE_ID_INTEL_CFL_H_XEON_GT2,
Lean Sheng Tan38c3ff72019-05-27 13:06:35 +0800170 PCI_DEVICE_ID_INTEL_CFL_S_GT2_1,
171 PCI_DEVICE_ID_INTEL_CFL_S_GT2_2,
172 PCI_DEVICE_ID_INTEL_CFL_S_GT2_3,
Felix Singerd298ffe2019-07-28 13:27:11 +0200173 PCI_DEVICE_ID_INTEL_CFL_S_GT2_4,
Aamir Bohra9eac0392018-06-30 12:07:04 +0530174 PCI_DEVICE_ID_INTEL_ICL_GT0_ULT,
175 PCI_DEVICE_ID_INTEL_ICL_GT0_5_ULT,
176 PCI_DEVICE_ID_INTEL_ICL_GT1_ULT,
177 PCI_DEVICE_ID_INTEL_ICL_GT2_ULX_0,
178 PCI_DEVICE_ID_INTEL_ICL_GT2_ULX_1,
179 PCI_DEVICE_ID_INTEL_ICL_GT2_ULT_1,
180 PCI_DEVICE_ID_INTEL_ICL_GT2_ULX_2,
181 PCI_DEVICE_ID_INTEL_ICL_GT2_ULT_2,
182 PCI_DEVICE_ID_INTEL_ICL_GT2_ULX_3,
183 PCI_DEVICE_ID_INTEL_ICL_GT2_ULT_3,
184 PCI_DEVICE_ID_INTEL_ICL_GT2_ULX_4,
185 PCI_DEVICE_ID_INTEL_ICL_GT2_ULT_4,
186 PCI_DEVICE_ID_INTEL_ICL_GT2_ULX_5,
187 PCI_DEVICE_ID_INTEL_ICL_GT2_ULT_5,
188 PCI_DEVICE_ID_INTEL_ICL_GT2_ULX_6,
189 PCI_DEVICE_ID_INTEL_ICL_GT3_ULT,
Ronak Kanabarf606a2f2019-02-04 16:06:50 +0530190 PCI_DEVICE_ID_INTEL_CML_GT1_ULT_1,
191 PCI_DEVICE_ID_INTEL_CML_GT1_ULT_2,
192 PCI_DEVICE_ID_INTEL_CML_GT2_ULT_1,
193 PCI_DEVICE_ID_INTEL_CML_GT2_ULT_2,
194 PCI_DEVICE_ID_INTEL_CML_GT1_ULT_3,
195 PCI_DEVICE_ID_INTEL_CML_GT1_ULT_4,
Meera Ravindranath970f1a42019-08-27 16:16:56 +0530196 PCI_DEVICE_ID_INTEL_CML_GT2_ULT_5,
197 PCI_DEVICE_ID_INTEL_CML_GT2_ULT_6,
Ronak Kanabarf606a2f2019-02-04 16:06:50 +0530198 PCI_DEVICE_ID_INTEL_CML_GT2_ULT_3,
199 PCI_DEVICE_ID_INTEL_CML_GT2_ULT_4,
200 PCI_DEVICE_ID_INTEL_CML_GT1_ULX_1,
201 PCI_DEVICE_ID_INTEL_CML_GT2_ULX_1,
202 PCI_DEVICE_ID_INTEL_CML_GT1_S_1,
203 PCI_DEVICE_ID_INTEL_CML_GT1_S_2,
204 PCI_DEVICE_ID_INTEL_CML_GT2_S_1,
205 PCI_DEVICE_ID_INTEL_CML_GT2_S_2,
206 PCI_DEVICE_ID_INTEL_CML_GT1_H_1,
207 PCI_DEVICE_ID_INTEL_CML_GT1_H_2,
208 PCI_DEVICE_ID_INTEL_CML_GT2_H_1,
209 PCI_DEVICE_ID_INTEL_CML_GT2_H_2,
Ravi Sarawadi6b5bf402019-10-21 22:25:04 -0700210 PCI_DEVICE_ID_INTEL_TGL_GT1,
211 PCI_DEVICE_ID_INTEL_TGL_GT2_UY,
212 PCI_DEVICE_ID_INTEL_TGL_GT2,
213 PCI_DEVICE_ID_INTEL_TGL_GT2_Y,
Subrata Banikfa7cc782017-11-27 18:23:36 +0530214 0,
215};
216
217static const struct pci_driver graphics_driver __pci_driver = {
218 .ops = &graphics_ops,
219 .vendor = PCI_VENDOR_ID_INTEL,
220 .devices = pci_device_ids,
221};