Werner Zeh | 0dc87ef | 2019-10-22 15:08:19 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
Werner Zeh | 0dc87ef | 2019-10-22 15:08:19 +0200 | [diff] [blame] | 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify |
| 6 | * it under the terms of the GNU General Public License as published by |
| 7 | * the Free Software Foundation; version 2 of the License. |
| 8 | * |
| 9 | * This program is distributed in the hope that it will be useful, |
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the |
| 12 | * GNU General Public License for more details. |
| 13 | */ |
| 14 | |
| 15 | #include <commonlib/helpers.h> |
| 16 | #include <baseboard/variants.h> |
| 17 | |
| 18 | /* |
| 19 | * Pad configuration in ramstage. The order largely follows the 'GPIO Muxing' |
| 20 | * table found in EDS vol 1, but some pins aren't grouped functionally in |
| 21 | * the table so those were moved for more logical grouping. |
| 22 | */ |
| 23 | static const struct pad_config gpio_table[] = { |
| 24 | |
| 25 | /* Southwest Community */ |
| 26 | |
| 27 | /* PCIE_WAKE[0:3]_N */ |
| 28 | PAD_CFG_NF(GPIO_205, NONE, DEEP, NF1), /* PCIE_WAKE0_N */ |
| 29 | PAD_CFG_NF(GPIO_206, NONE, DEEP, NF1), /* PCIE_WAKE1_N */ |
| 30 | PAD_CFG_NF(GPIO_207, NONE, DEEP, NF1), /* PCIE_WAKE2_N */ |
| 31 | PAD_CFG_NF(GPIO_208, NONE, DEEP, NF1), /* PCIE_WAKE3_N */ |
| 32 | |
| 33 | /* EMMC interface. */ |
| 34 | PAD_CFG_NF(GPIO_156, DN_20K, DEEP, NF1), /* EMMC_CLK */ |
| 35 | PAD_CFG_NF(GPIO_157, UP_20K, DEEP, NF1), /* EMMC_D0 */ |
| 36 | PAD_CFG_NF(GPIO_158, UP_20K, DEEP, NF1), /* EMMC_D1 */ |
| 37 | PAD_CFG_NF(GPIO_159, UP_20K, DEEP, NF1), /* EMMC_D2 */ |
| 38 | PAD_CFG_NF(GPIO_160, UP_20K, DEEP, NF1), /* EMMC_D3 */ |
| 39 | PAD_CFG_NF(GPIO_161, UP_20K, DEEP, NF1), /* EMMC_D4 */ |
| 40 | PAD_CFG_NF(GPIO_162, UP_20K, DEEP, NF1), /* EMMC_D5 */ |
| 41 | PAD_CFG_NF(GPIO_163, UP_20K, DEEP, NF1), /* EMMC_D6 */ |
| 42 | PAD_CFG_NF(GPIO_164, UP_20K, DEEP, NF1), /* EMMC_D7 */ |
| 43 | PAD_CFG_NF(GPIO_165, UP_20K, DEEP, NF1), /* EMMC_CMD */ |
| 44 | PAD_CFG_NF(GPIO_182, DN_20K, DEEP, NF1), /* EMMC_RCLK */ |
| 45 | |
| 46 | /* SDIO -- unused */ |
| 47 | PAD_CFG_GPI(GPIO_166, DN_20K, DEEP), /* SDIO_CLK */ |
| 48 | PAD_CFG_GPI(GPIO_167, UP_20K, DEEP), /* SDIO_D0 */ |
| 49 | /* Configure SDIO to enable power gating. */ |
| 50 | PAD_CFG_NF(GPIO_168, UP_20K, DEEP, NF1), /* SDIO_D1 */ |
| 51 | PAD_CFG_GPI(GPIO_169, UP_20K, DEEP), /* SDIO_D2 */ |
| 52 | PAD_CFG_GPI(GPIO_170, UP_20K, DEEP), /* SDIO_D3 */ |
| 53 | PAD_CFG_GPI(GPIO_171, UP_20K, DEEP), /* SDIO_CMD */ |
| 54 | |
| 55 | /* SDCARD */ |
| 56 | /* Pull down clock by 20K. */ |
| 57 | PAD_CFG_NF(GPIO_172, DN_20K, DEEP, NF1), /* SDCARD_CLK */ |
| 58 | PAD_CFG_NF(GPIO_173, UP_20K, DEEP, NF1), /* SDCARD_D0 */ |
| 59 | PAD_CFG_NF(GPIO_174, UP_20K, DEEP, NF1), /* SDCARD_D1 */ |
| 60 | PAD_CFG_NF(GPIO_175, UP_20K, DEEP, NF1), /* SDCARD_D2 */ |
| 61 | PAD_CFG_NF(GPIO_176, UP_20K, DEEP, NF1), /* SDCARD_D3 */ |
| 62 | /* Card detect is active LOW with external pull up. */ |
| 63 | PAD_CFG_NF(GPIO_177, UP_20K, DEEP, NF1), /* SDCARD_CD_N */ |
| 64 | PAD_CFG_NF(GPIO_178, UP_20K, DEEP, NF1), /* SDCARD_CMD */ |
| 65 | /* CLK feedback, internal signal, needs 20K pull down. */ |
| 66 | PAD_CFG_NF(GPIO_179, DN_20K, DEEP, NF1), /* SDCARD_CLK_FB */ |
| 67 | PAD_CFG_GPI(GPIO_186, UP_20K, DEEP), /* SDCARD_LVL_WP */ |
| 68 | /* EN_SD_SOCKET_PWR_L for SD slot power control. Default on. */ |
| 69 | PAD_CFG_TERM_GPO(GPIO_183, 1, DN_20K, DEEP), /* SDIO_PWR_DOWN_N */ |
| 70 | |
| 71 | /* SMBus */ |
| 72 | PAD_CFG_GPI(SMB_ALERTB, UP_20K, DEEP), /* SMB_ALERT _N */ |
| 73 | PAD_CFG_NF(SMB_CLK, NONE, DEEP, NF1), /* SMB_CLK */ |
| 74 | PAD_CFG_NF(SMB_DATA, NONE, DEEP, NF1), /* SMB_DATA */ |
| 75 | |
| 76 | /* LPC */ |
| 77 | PAD_CFG_NF(LPC_ILB_SERIRQ, NONE, DEEP, NF1), /* LPC_SERIRQ */ |
| 78 | PAD_CFG_NF(LPC_CLKOUT0, DN_20K, DEEP, NF1), /* LPC_CLKOUT0 */ |
| 79 | PAD_CFG_GPI(LPC_CLKOUT1, UP_20K, DEEP), /* LPC_CLKOUT1 */ |
| 80 | PAD_CFG_NF(LPC_AD0, NONE, DEEP, NF1), /* LPC_AD0 */ |
| 81 | PAD_CFG_NF(LPC_AD1, NONE, DEEP, NF1), /* LPC_AD1 */ |
| 82 | PAD_CFG_NF(LPC_AD2, NONE, DEEP, NF1), /* LPC_AD2 */ |
| 83 | PAD_CFG_NF(LPC_AD3, NONE, DEEP, NF1), /* LPC_AD3 */ |
| 84 | PAD_CFG_NF(LPC_CLKRUNB, NONE, DEEP, NF1), /* LPC_CLKRUN_N */ |
| 85 | PAD_CFG_NF(LPC_FRAMEB, NONE, DEEP, NF1), /* LPC_FRAME_N */ |
| 86 | |
| 87 | /* West Community */ |
| 88 | |
| 89 | /* I2C0 - I2C Level Shifter */ |
| 90 | PAD_CFG_NF(GPIO_124, NONE, DEEP, NF1), /* LPSS_I2C0_SDA */ |
| 91 | PAD_CFG_NF(GPIO_125, NONE, DEEP, NF1), /* LPSS_I2C0_SCL */ |
| 92 | |
| 93 | /* I2C[1:7] -- unused */ |
| 94 | PAD_CFG_GPI(GPIO_126, UP_20K, DEEP), /* LPSS_I2C1_SDA */ |
| 95 | PAD_CFG_GPI(GPIO_127, UP_20K, DEEP), /* LPSS_I2C1_SCL */ |
| 96 | PAD_CFG_GPI(GPIO_128, UP_20K, DEEP), /* LPSS_I2C2_SDA */ |
| 97 | PAD_CFG_GPI(GPIO_129, UP_20K, DEEP), /* LPSS_I2C2_SCL */ |
| 98 | PAD_CFG_GPI(GPIO_130, UP_20K, DEEP), /* LPSS_I2C3_SDA */ |
| 99 | PAD_CFG_GPI(GPIO_131, UP_20K, DEEP), /* LPSS_I2C3_SCL */ |
| 100 | PAD_CFG_GPI(GPIO_132, UP_20K, DEEP), /* LPSS_I2C4_SDA */ |
| 101 | PAD_CFG_GPI(GPIO_133, UP_20K, DEEP), /* LPSS_I2C4_SCL */ |
| 102 | PAD_CFG_GPI(GPIO_134, UP_20K, DEEP), /* LPSS_I2C5_SDA */ |
| 103 | PAD_CFG_GPI(GPIO_135, UP_20K, DEEP), /* LPSS_I2C5_SCL */ |
| 104 | PAD_CFG_GPI(GPIO_136, UP_20K, DEEP), /* LPSS_I2C6_SDA */ |
| 105 | PAD_CFG_GPI(GPIO_137, UP_20K, DEEP), /* LPSS_I2C6_SCL */ |
| 106 | PAD_CFG_GPI(GPIO_138, UP_20K, DEEP), /* LPSS_I2C7_SDA */ |
| 107 | PAD_CFG_GPI(GPIO_139, UP_20K, DEEP), /* LPSS_I2C7_SCL */ |
| 108 | |
| 109 | /* ISH_GPIO_[0:9] -- unused */ |
| 110 | PAD_CFG_GPI(GPIO_146, DN_20K, DEEP), /* ISH_GPIO_0 */ |
| 111 | PAD_CFG_GPI(GPIO_147, DN_20K, DEEP), /* ISH_GPIO_1 */ |
| 112 | PAD_CFG_GPI(GPIO_148, DN_20K, DEEP), /* ISH_GPIO_2 */ |
| 113 | PAD_CFG_GPI(GPIO_149, DN_20K, DEEP), /* ISH_GPIO_3 */ |
| 114 | PAD_CFG_GPI(GPIO_150, DN_20K, DEEP), /* ISH_GPIO_4 */ |
| 115 | PAD_CFG_GPI(GPIO_151, DN_20K, DEEP), /* ISH_GPIO_5 */ |
| 116 | PAD_CFG_GPI(GPIO_152, DN_20K, DEEP), /* ISH_GPIO_6 */ |
| 117 | PAD_CFG_GPI(GPIO_153, DN_20K, DEEP), /* ISH_GPIO_7 */ |
| 118 | PAD_CFG_GPI(GPIO_154, DN_20K, DEEP), /* ISH_GPIO_8 */ |
| 119 | PAD_CFG_GPI(GPIO_155, DN_20K, DEEP), /* ISH_GPIO_9 */ |
| 120 | |
| 121 | /* PCIE_CLKREQ[0:3]_N */ |
| 122 | PAD_CFG_NF(GPIO_209, NONE, DEEP, NF1), |
| 123 | PAD_CFG_NF(GPIO_210, NONE, DEEP, NF1), |
| 124 | PAD_CFG_NF(GPIO_211, NONE, DEEP, NF1), |
| 125 | PAD_CFG_NF(GPIO_212, NONE, DEEP, NF1), |
| 126 | |
| 127 | /* OSC_CLK_OUT_0 - RES_CLK_CPU_FPGA */ |
| 128 | PAD_CFG_NF(OSC_CLK_OUT_0, DN_20K, DEEP, NF1), |
| 129 | /* OSC_CLK_OUT_[1:4] -- unused */ |
| 130 | PAD_CFG_GPI(OSC_CLK_OUT_1, DN_20K, DEEP), |
| 131 | PAD_CFG_GPI(OSC_CLK_OUT_2, DN_20K, DEEP), |
| 132 | PAD_CFG_GPI(OSC_CLK_OUT_3, DN_20K, DEEP), |
| 133 | PAD_CFG_GPI(OSC_CLK_OUT_4, DN_20K, DEEP), |
| 134 | |
| 135 | /* PMU Signals */ |
| 136 | PAD_CFG_GPI(PMU_AC_PRESENT, NONE, DEEP), /* PMU_AC_PRESENT */ |
| 137 | PAD_CFG_NF(PMU_BATLOW_B, UP_20K, DEEP, NF1), /* PMU_BATLOW_N */ |
| 138 | PAD_CFG_NF(PMU_PLTRST_B, NONE, DEEP, NF1), /* PMU_PLTRST_N */ |
| 139 | PAD_CFG_NF(PMU_PWRBTN_B, UP_20K, DEEP, NF1), /* PMU_PWRBTN_N */ |
| 140 | PAD_CFG_NF(PMU_RESETBUTTON_B, NONE, DEEP, NF1), /* PMU_RSTBTN_N */ |
| 141 | /* PMU_SLP_S0_N */ |
| 142 | PAD_CFG_NF_IOSSTATE(PMU_SLP_S0_B, NONE, DEEP, NF1, IGNORE), |
| 143 | PAD_CFG_NF(PMU_SLP_S3_B, NONE, DEEP, NF1), /* PMU_SLP_S3_N */ |
| 144 | PAD_CFG_NF(PMU_SLP_S4_B, NONE, DEEP, NF1), /* PMU_SLP_S4_N */ |
| 145 | PAD_CFG_NF(PMU_SUSCLK, NONE, DEEP, NF1), /* PMU_SUSCLK */ |
| 146 | PAD_CFG_TERM_GPO(PMU_WAKE_B, 1, UP_20K, DEEP), /* EN_PP3300_EMMC */ |
| 147 | PAD_CFG_NF(SUS_STAT_B, NONE, DEEP, NF1), /* SUS_STAT_N */ |
| 148 | PAD_CFG_NF(SUSPWRDNACK, NONE, DEEP, NF1), /* SUSPWRDNACK */ |
| 149 | |
| 150 | /* Northwest Community */ |
| 151 | |
| 152 | /* DDI0 SDA and SCL -- unused */ |
| 153 | PAD_CFG_GPI(GPIO_187, DN_20K, DEEP), /* HV_DDI0_DDC_SDA */ |
| 154 | PAD_CFG_GPI(GPIO_188, DN_20K, DEEP), /* HV_DDI0_DDC_SCL */ |
| 155 | /* DDI1 SDA and SCL - Display-Port */ |
| 156 | PAD_CFG_NF(GPIO_189, NONE, DEEP, NF1), /* HV_DDI1_DDC_SDA */ |
| 157 | PAD_CFG_NF(GPIO_190, NONE, DEEP, NF1), /* HV_DDI1_DDC_SCL */ |
| 158 | |
| 159 | /* MIPI I2C -- unused */ |
| 160 | PAD_CFG_GPI(GPIO_191, DN_20K, DEEP), /* MIPI_I2C_SDA */ |
| 161 | PAD_CFG_GPI(GPIO_192, DN_20K, DEEP), /* MIPI_I2C_SCL */ |
| 162 | |
| 163 | /* Panel 0 control -- unused */ |
| 164 | PAD_CFG_TERM_GPO(GPIO_193, 0, DN_20K, DEEP), /* PNL0_VDDEN */ |
| 165 | PAD_CFG_TERM_GPO(GPIO_194, 0, DN_20K, DEEP), /* PNL0_BKLTEN */ |
| 166 | PAD_CFG_TERM_GPO(GPIO_195, 0, DN_20K, DEEP), /* PNL0_BKLTCTL */ |
| 167 | |
| 168 | /* Panel 1 control -- unused */ |
| 169 | PAD_CFG_GPI(GPIO_196, DN_20K, DEEP), /* PNL1_VDDEN */ |
| 170 | PAD_CFG_GPI(GPIO_197, DN_20K, DEEP), /* PNL1_BKLTEN */ |
| 171 | PAD_CFG_GPI(GPIO_198, DN_20K, DEEP), /* PNL1_BKLTCTL */ |
| 172 | |
| 173 | /* DDI[0:1]_HPD -- unused */ |
| 174 | PAD_CFG_GPI(GPIO_199, NONE, DEEP), /* XHPD_DP */ |
| 175 | PAD_CFG_GPI(GPIO_200, DN_20K, DEEP), /* unused */ |
| 176 | |
| 177 | /* MDSI signals -- unused */ |
| 178 | PAD_CFG_GPI(GPIO_201, DN_20K, DEEP), /* MDSI_A_TE */ |
| 179 | PAD_CFG_GPI(GPIO_202, DN_20K, DEEP), /* MDSI_C_TE */ |
| 180 | |
| 181 | /* USB overcurrent pins. */ |
| 182 | PAD_CFG_NF(GPIO_203, NONE, DEEP, NF1), /* USB_OC0_N */ |
| 183 | PAD_CFG_NF(GPIO_204, NONE, DEEP, NF1), /* USB_OC1_N */ |
| 184 | |
| 185 | /* PMC SPI -- almost entirely unused. */ |
| 186 | PAD_CFG_GPI(PMC_SPI_FS0, UP_20K, DEEP), /* CLP_NC */ |
| 187 | PAD_CFG_NF(PMC_SPI_FS1, UP_20K, DEEP, NF2), /* XHPD_EDP_APL */ |
| 188 | PAD_CFG_GPI(PMC_SPI_FS2, UP_20K, DEEP), |
| 189 | PAD_CFG_GPI(PMC_SPI_RXD, DN_20K, DEEP), |
| 190 | PAD_CFG_GPI(PMC_SPI_TXD, DN_20K, DEEP), |
| 191 | PAD_CFG_GPI(PMC_SPI_CLK, DN_20K, DEEP), |
| 192 | |
| 193 | /* PMIC Signals unused signals related to an old PMIC interface. */ |
| 194 | PAD_CFG_NF(PMIC_PWRGOOD, UP_20K, DEEP, NF1), /* PMIC_PWRGOOD */ |
| 195 | PAD_CFG_GPI(PMIC_RESET_B, DN_20K, DEEP), /* PMIC_RESET_B */ |
| 196 | PAD_CFG_TERM_GPO(GPIO_213, 0, DN_20K, DEEP), /* NFC_OUT_RESERVE */ |
| 197 | PAD_CFG_TERM_GPO(GPIO_214, 0, DN_20K, DEEP), /* NFC_EN */ |
| 198 | PAD_CFG_GPI(GPIO_215, DN_20K, DEEP), /* NFC_IN_RESERVE */ |
| 199 | /* THERMTRIP_N */ |
| 200 | PAD_CFG_NF(PMIC_THERMTRIP_B, UP_20K, DEEP, NF1), |
| 201 | PAD_CFG_TERM_GPO(PMIC_STDBY, 0, DN_20K, DEEP), /* unused */ |
| 202 | PAD_CFG_NF(PROCHOT_B, NONE, DEEP, NF1), /* PROCHOT_N */ |
| 203 | PAD_CFG_NF(PMIC_I2C_SCL, NONE, DEEP, NF1), /* PMIC_I2C_SCL */ |
| 204 | PAD_CFG_NF(PMIC_I2C_SDA, NONE, DEEP, NF1), /* PMIC_I2C_SDA */ |
| 205 | |
| 206 | /* I2S1 -- unused */ |
| 207 | PAD_CFG_GPI(GPIO_74, DN_20K, DEEP), /* I2S1_MCLK */ |
| 208 | PAD_CFG_GPI(GPIO_75, DN_20K, DEEP), /* I2S1_BCLK */ |
| 209 | PAD_CFG_GPI(GPIO_76, DN_20K, DEEP), /* I2S1_WS_SYNC */ |
| 210 | PAD_CFG_GPI(GPIO_77, DN_20K, DEEP), /* I2S1_SDI */ |
| 211 | PAD_CFG_GPI(GPIO_78, DN_20K, DEEP), /* I2S1_SDO */ |
| 212 | |
| 213 | /* DMIC or I2S4 -- unused */ |
| 214 | PAD_CFG_GPI(GPIO_79, DN_20K, DEEP), /* AVS_M_CLK_A1 */ |
| 215 | PAD_CFG_GPI(GPIO_80, DN_20K, DEEP), /* AVS_M_CLK_B1 */ |
| 216 | PAD_CFG_GPI(GPIO_81, DN_20K, DEEP), /* AVS_M_DATA_1 */ |
| 217 | PAD_CFG_GPI(GPIO_82, DN_20K, DEEP), /* AVS_M_CLK_AB2 */ |
| 218 | PAD_CFG_GPI(GPIO_83, DN_20K, DEEP), /* AVS_M_DATA_2 */ |
| 219 | |
| 220 | /* I2S2 -- unused */ |
| 221 | PAD_CFG_GPI(GPIO_84, DN_20K, DEEP), /* AVS_I2S2_MCLK */ |
| 222 | PAD_CFG_GPI(GPIO_85, DN_20K, DEEP), /* AVS_I2S2_BCLK */ |
| 223 | PAD_CFG_GPI(GPIO_86, DN_20K, DEEP), /* AVS_I2S2_WS_SYNC */ |
| 224 | PAD_CFG_GPI(GPIO_87, DN_20K, DEEP), /* AVS_I2S2_SDI */ |
| 225 | PAD_CFG_GPI(GPIO_88, DN_20K, DEEP), /* AVS_I2S2_SDO */ |
| 226 | |
| 227 | /* I2S3 -- unused */ |
| 228 | PAD_CFG_GPI(GPIO_89, DN_20K, DEEP), /* AVS_I2S3_BCLK */ |
| 229 | PAD_CFG_GPI(GPIO_90, DN_20K, DEEP), /* AVS_I2S3_WS_SYNC */ |
| 230 | PAD_CFG_GPI(GPIO_91, DN_20K, DEEP), /* AVS_I2S3_SDI */ |
| 231 | PAD_CFG_GPI(GPIO_92, DN_20K, DEEP), /* AVS_I2S3_SDO */ |
| 232 | |
| 233 | /* Fast SPI */ |
| 234 | /* FST_SPI_CS0_B */ |
| 235 | PAD_CFG_NF_IOSSTATE(GPIO_97, NATIVE, DEEP, NF1, IGNORE), |
| 236 | /* FST_SPI_CS1_B -- unused */ |
| 237 | PAD_CFG_GPI(GPIO_98, DN_20K, DEEP), |
| 238 | /* FST_SPI_MOSI_IO0 */ |
| 239 | PAD_CFG_NF_IOSSTATE(GPIO_99, NATIVE, DEEP, NF1, IGNORE), |
| 240 | /* FST_SPI_MISO_IO1 */ |
| 241 | PAD_CFG_NF_IOSSTATE(GPIO_100, NATIVE, DEEP, NF1, IGNORE), |
| 242 | /* FST_IO2 -- MEM_CONFIG0 */ |
| 243 | PAD_CFG_NF(GPIO_101, NATIVE, DEEP, NF1), |
| 244 | /* FST_IO3 -- MEM_CONFIG1 */ |
| 245 | PAD_CFG_NF(GPIO_102, NATIVE, DEEP, NF1), |
| 246 | /* FST_SPI_CLK */ |
| 247 | PAD_CFG_NF_IOSSTATE(GPIO_103, NATIVE, DEEP, NF1, IGNORE), |
| 248 | /* FST_SPI_CLK_FB */ |
| 249 | PAD_CFG_NF_IOSSTATE(FST_SPI_CLK_FB, NATIVE, DEEP, NF1, IGNORE), |
| 250 | |
| 251 | /* SIO_SPI_0 -- unused */ |
| 252 | PAD_CFG_GPI(GPIO_104, DN_20K, DEEP), /* GP_SSP_0_CLK */ |
| 253 | PAD_CFG_GPI(GPIO_105, DN_20K, DEEP), /* GP_SSP_0_FS0 */ |
Werner Zeh | 7c276c0 | 2019-10-22 15:22:21 +0200 | [diff] [blame] | 254 | PAD_CFG_NF(GPIO_106, NATIVE, DEEP, NF3), /* FST_SPI_CS2_N */ |
Werner Zeh | 0dc87ef | 2019-10-22 15:08:19 +0200 | [diff] [blame] | 255 | PAD_CFG_GPI(GPIO_109, DN_20K, DEEP), /* GP_SSP_0_RXD */ |
| 256 | PAD_CFG_GPI(GPIO_110, DN_20K, DEEP), /* GP_SSP_0_TXD */ |
| 257 | |
| 258 | /* SIO_SPI_1 -- unused */ |
| 259 | PAD_CFG_GPI(GPIO_111, DN_20K, DEEP), /* GP_SSP_1_CLK */ |
| 260 | PAD_CFG_GPI(GPIO_112, DN_20K, DEEP), /* GP_SSP_1_FS0 */ |
| 261 | PAD_CFG_GPI(GPIO_113, DN_20K, DEEP), /* GP_SSP_1_FS1 */ |
| 262 | PAD_CFG_GPI(GPIO_116, DN_20K, DEEP), /* GP_SSP_1_RXD */ |
| 263 | PAD_CFG_GPI(GPIO_117, DN_20K, DEEP), /* GP_SSP_1_TXD */ |
| 264 | |
| 265 | /* SIO_SPI_2 -- unused */ |
| 266 | PAD_CFG_GPI(GPIO_118, DN_20K, DEEP), /* GP_SSP_2_CLK */ |
| 267 | PAD_CFG_GPI(GPIO_119, DN_20K, DEEP), /* GP_SSP_2_FS0 */ |
| 268 | PAD_CFG_GPI(GPIO_120, DN_20K, DEEP), /* GP_SSP_2_FS1 */ |
| 269 | PAD_CFG_GPI(GPIO_121, DN_20K, DEEP), /* GP_SSP_2_FS2 */ |
| 270 | PAD_CFG_GPI(GPIO_122, DN_20K, DEEP), /* GP_SSP_2_RXD */ |
| 271 | PAD_CFG_GPI(GPIO_123, NONE, DEEP), /* GP_SSP_2_TXD */ |
| 272 | |
| 273 | /* North Community */ |
| 274 | |
| 275 | /* Debug tracing. */ |
| 276 | PAD_CFG_GPI(GPIO_0, DN_20K, DEEP), /* TRACE_0_CLK_VNN */ |
| 277 | PAD_CFG_GPI(GPIO_1, DN_20K, DEEP), /* TRACE_0_DATA0_VNN */ |
| 278 | PAD_CFG_GPI(GPIO_2, DN_20K, DEEP), /* TRACE_0_DATA1_VNN */ |
| 279 | PAD_CFG_GPI(GPIO_3, DN_20K, DEEP), /* TRACE_0_DATA2_VNN */ |
| 280 | PAD_CFG_GPI(GPIO_4, DN_20K, DEEP), /* TRACE_0_DATA3_VNN */ |
| 281 | PAD_CFG_GPI(GPIO_5, DN_20K, DEEP), /* TRACE_0_DATA4_VNN */ |
| 282 | PAD_CFG_GPI(GPIO_6, DN_20K, DEEP), /* TRACE_0_DATA5_VNN */ |
| 283 | PAD_CFG_GPI(GPIO_7, DN_20K, DEEP), /* TRACE_0_DATA6_VNN */ |
| 284 | PAD_CFG_GPI(GPIO_8, DN_20K, DEEP), /* TRACE_0_DATA7_VNN */ |
| 285 | |
| 286 | PAD_CFG_GPI(GPIO_9, DN_20K, DEEP), /* TRACE_1_CLK_VNN */ |
| 287 | PAD_CFG_GPI(GPIO_10, DN_20K, DEEP), /* TRACE_1_DATA0_VNN */ |
| 288 | PAD_CFG_GPI(GPIO_11, DN_20K, DEEP), /* TRACE_1_DATA1_VNN */ |
| 289 | PAD_CFG_GPI(GPIO_12, DN_20K, DEEP), /* TRACE_1_DATA2_VNN */ |
| 290 | PAD_CFG_GPI(GPIO_13, DN_20K, DEEP), /* TRACE_1_DATA3_VNN */ |
| 291 | PAD_CFG_GPI(GPIO_14, DN_20K, DEEP), /* TRACE_1_DATA4_VNN */ |
| 292 | PAD_CFG_GPI(GPIO_15, DN_20K, DEEP), /* TRACE_1_DATA5_VNN */ |
| 293 | PAD_CFG_GPI(GPIO_16, DN_20K, DEEP), /* TRACE_1_DATA6_VNN */ |
| 294 | PAD_CFG_GPI(GPIO_17, DN_20K, DEEP), /* TRACE_1_DATA7_VNN */ |
| 295 | |
| 296 | PAD_CFG_GPI(GPIO_18, DN_20K, DEEP), /* TRACE_2_CLK_VNN */ |
| 297 | PAD_CFG_GPI(GPIO_19, DN_20K, DEEP), /* TRACE_2_DATA0_VNN */ |
| 298 | PAD_CFG_GPI(GPIO_20, DN_20K, DEEP), /* TRACE_2_DATA1_VNN */ |
| 299 | PAD_CFG_GPI(GPIO_21, DN_20K, DEEP), /* TRACE_2_DATA2_VNN */ |
| 300 | PAD_CFG_GPI(GPIO_22, DN_20K, DEEP), /* TRACE_2_DATA3_VNN */ |
| 301 | PAD_CFG_GPI(GPIO_23, DN_20K, DEEP), /* TRACE_2_DATA4_VNN */ |
| 302 | PAD_CFG_GPI(GPIO_24, DN_20K, DEEP), /* TRACE_2_DATA5_VNN */ |
| 303 | PAD_CFG_GPI(GPIO_25, DN_20K, DEEP), /* TRACE_2_DATA6_VNN */ |
| 304 | PAD_CFG_GPI(GPIO_26, DN_20K, DEEP), /* TRACE_2_DATA7_VNN */ |
| 305 | |
| 306 | PAD_CFG_GPI(GPIO_27, DN_20K, DEEP), /* TRIGOUT_0 */ |
| 307 | PAD_CFG_GPI(GPIO_28, DN_20K, DEEP), /* TRIGOUT_1 */ |
| 308 | PAD_CFG_GPI(GPIO_29, DN_20K, DEEP), /* TRIGIN_0 */ |
| 309 | |
| 310 | PAD_CFG_GPI(GPIO_30, DN_20K, DEEP), /* ISH_GPIO_12 */ |
| 311 | PAD_CFG_TERM_GPO(GPIO_31, 1, UP_20K, DEEP), /* ISH_GPIO_13 */ |
| 312 | PAD_CFG_GPI(GPIO_32, UP_20K, DEEP), /* ISH_GPIO_14 */ |
| 313 | PAD_CFG_GPI(GPIO_33, DN_20K, DEEP), /* ISH_GPIO_15 */ |
| 314 | |
| 315 | /* PWM[0:3] -- unused */ |
| 316 | PAD_CFG_GPI(GPIO_34, DN_20K, DEEP), |
| 317 | PAD_CFG_GPI(GPIO_35, DN_20K, DEEP), |
| 318 | PAD_CFG_GPI(GPIO_36, DN_20K, DEEP), |
| 319 | PAD_CFG_GPI(GPIO_37, DN_20K, DEEP), |
| 320 | |
| 321 | /* LPSS_UART[0:2] */ |
| 322 | PAD_CFG_GPI(GPIO_38, UP_20K, DEEP), /* LPSS_UART0_RXD - unused */ |
| 323 | PAD_CFG_GPI(GPIO_39, DN_20K, DEEP), /* LPSS_UART0_TXD - unused */ |
| 324 | PAD_CFG_GPI(GPIO_40, DN_20K, DEEP), /* LPSS_UART0_RTS - unused */ |
| 325 | PAD_CFG_GPI(GPIO_41, UP_20K, DEEP), /* LPSS_UART0_CTS - unused */ |
| 326 | PAD_CFG_NF(GPIO_42, UP_20K, DEEP, NF1), /* LPSS_UART1_RXD */ |
| 327 | /* LPSS_UART1_TXD */ |
| 328 | PAD_CFG_NF_IOSSTATE(GPIO_43, NATIVE, DEEP, NF1, Tx1RxDCRx0), |
| 329 | PAD_CFG_GPI(GPIO_44, UP_20K, DEEP), /* LPSS_UART1_RTS - unused */ |
| 330 | PAD_CFG_GPI(GPIO_45, UP_20K, DEEP), /* LPSS_UART1_CTS - unused */ |
| 331 | PAD_CFG_NF(GPIO_46, UP_20K, DEEP, NF1), /* LPSS_UART2_RXD */ |
| 332 | /* LPSS_UART2_TXD */ |
| 333 | PAD_CFG_NF_IOSSTATE(GPIO_47, NATIVE, DEEP, NF1, Tx1RxDCRx0), |
| 334 | PAD_CFG_GPI(GPIO_48, DN_20K, DEEP), /* LPSS_UART2_RTS - unused */ |
| 335 | PAD_CFG_GPI(GPIO_49, UP_20K, DEEP), /* LPSS_UART2_CTS - unused */ |
| 336 | |
| 337 | /* Camera interface -- completely unused. */ |
| 338 | PAD_CFG_GPI(GPIO_62, DN_20K, DEEP), /* GP_CAMERASB00 */ |
| 339 | PAD_CFG_GPI(GPIO_63, DN_20K, DEEP), /* GP_CAMERASB01 */ |
| 340 | PAD_CFG_GPI(GPIO_64, DN_20K, DEEP), /* GP_CAMERASB02 */ |
| 341 | PAD_CFG_GPI(GPIO_65, DN_20K, DEEP), /* GP_CAMERASB03 */ |
| 342 | PAD_CFG_GPI(GPIO_66, DN_20K, DEEP), /* GP_CAMERASB04 */ |
| 343 | PAD_CFG_GPI(GPIO_67, DN_20K, DEEP), /* GP_CAMERASB05 */ |
| 344 | PAD_CFG_GPI(GPIO_68, DN_20K, DEEP), /* GP_CAMERASB06 */ |
| 345 | PAD_CFG_GPI(GPIO_69, DN_20K, DEEP), /* GP_CAMERASB07 */ |
| 346 | PAD_CFG_GPI(GPIO_70, UP_20K, DEEP), /* GP_CAMERASB08 */ |
| 347 | PAD_CFG_GPI(GPIO_71, UP_20K, DEEP), /* GP_CAMERASB09 */ |
| 348 | PAD_CFG_GPI(GPIO_72, UP_20K, DEEP), /* GP_CAMERASB10 */ |
| 349 | PAD_CFG_GPI(GPIO_73, UP_20K, DEEP), /* GP_CAMERASB11 */ |
| 350 | |
| 351 | /* CNV bridge described into IAFW Vol2. */ |
| 352 | /* GPIO_[216:219] described into EDS Vol1. */ |
| 353 | PAD_CFG_TERM_GPO(CNV_BRI_DT, 0, DN_20K, DEEP), /* Reserve of FPGA */ |
| 354 | PAD_CFG_TERM_GPO(CNV_BRI_RSP, 0, DN_20K, DEEP), /* Reserve of FPGA */ |
| 355 | PAD_CFG_TERM_GPO(CNV_RGI_DT, 0, DN_20K, DEEP), /* Reserve of FPGA */ |
| 356 | PAD_CFG_NF(CNV_RGI_RSP, UP_20K, DEEP, NF1), /* eMMC */ |
| 357 | |
| 358 | /* Serial VID */ |
| 359 | PAD_CFG_NF(SVID0_ALERT_B, NONE, DEEP, NF1), /* SVID0_ALERT_B */ |
| 360 | PAD_CFG_NF(SVID0_DATA, UP_20K, DEEP, NF1), /* SVID0_DATA */ |
| 361 | PAD_CFG_NF(SVID0_CLK, UP_20K, DEEP, NF1), /* SVID0_CLK */ |
| 362 | }; |
| 363 | |
| 364 | const struct pad_config *variant_gpio_table(size_t *num) |
| 365 | { |
| 366 | *num = ARRAY_SIZE(gpio_table); |
| 367 | return gpio_table; |
| 368 | } |
| 369 | |
| 370 | /* GPIOs needed prior to ramstage. */ |
| 371 | static const struct pad_config early_gpio_table[] = { |
| 372 | |
| 373 | /* Debug tracing. */ |
| 374 | PAD_CFG_GPI(GPIO_0, DN_20K, DEEP), /* TRACE_0_CLK_VNN */ |
| 375 | PAD_CFG_GPI(GPIO_1, DN_20K, DEEP), /* TRACE_0_DATA0_VNN */ |
| 376 | PAD_CFG_GPI(GPIO_2, DN_20K, DEEP), /* TRACE_0_DATA1_VNN */ |
| 377 | PAD_CFG_GPI(GPIO_3, DN_20K, DEEP), /* TRACE_0_DATA2_VNN */ |
| 378 | PAD_CFG_GPI(GPIO_4, DN_20K, DEEP), /* TRACE_0_DATA3_VNN */ |
| 379 | PAD_CFG_GPI(GPIO_5, DN_20K, DEEP), /* TRACE_0_DATA4_VNN */ |
| 380 | PAD_CFG_GPI(GPIO_6, DN_20K, DEEP), /* TRACE_0_DATA5_VNN */ |
| 381 | PAD_CFG_GPI(GPIO_7, DN_20K, DEEP), /* TRACE_0_DATA6_VNN */ |
| 382 | PAD_CFG_GPI(GPIO_8, DN_20K, DEEP), /* TRACE_0_DATA7_VNN */ |
| 383 | |
| 384 | PAD_CFG_GPO(GPIO_13, 0, DEEP), /* PERST# */ |
| 385 | PAD_CFG_GPO(GPIO_15, 0, DEEP), /* PERST# */ |
| 386 | PAD_CFG_GPO(GPIO_17, 1, DEEP), /* PFET */ |
| 387 | PAD_CFG_GPO(GPIO_19, 1, DEEP), /* PFET */ |
| 388 | PAD_CFG_GPO(GPIO_152, 0, DEEP), /* PERST# */ |
| 389 | |
| 390 | /* SMBus */ |
| 391 | PAD_CFG_NF(SMB_CLK, NONE, DEEP, NF1), /* SMB_CLK */ |
| 392 | PAD_CFG_NF(SMB_DATA, NONE, DEEP, NF1), /* SMB_DATA */ |
| 393 | |
| 394 | /* LPC */ |
| 395 | PAD_CFG_NF(LPC_ILB_SERIRQ, NONE, DEEP, NF1), /* LPC_SERIRQ */ |
| 396 | PAD_CFG_NF(LPC_CLKOUT0, DN_20K, DEEP, NF1), /* LPC_CLKOUT0 */ |
| 397 | /* LPC_CLKOUT1 - unused */ |
| 398 | PAD_CFG_GPI(LPC_CLKOUT1, DN_20K, DEEP), |
| 399 | PAD_CFG_NF(LPC_AD0, NONE, DEEP, NF1), /* LPC_AD0 */ |
| 400 | PAD_CFG_NF(LPC_AD1, NONE, DEEP, NF1), /* LPC_AD1 */ |
| 401 | PAD_CFG_NF(LPC_AD2, NONE, DEEP, NF1), /* LPC_AD2 */ |
| 402 | PAD_CFG_NF(LPC_AD3, NONE, DEEP, NF1), /* LPC_AD3 */ |
| 403 | PAD_CFG_NF(LPC_CLKRUNB, NONE, DEEP, NF1), /* LPC_CLKRUN_N */ |
| 404 | PAD_CFG_NF(LPC_FRAMEB, NONE, DEEP, NF1), /* LPC_FRAME_N */ |
| 405 | }; |
| 406 | |
| 407 | const struct pad_config *variant_early_gpio_table(size_t *num) |
| 408 | { |
| 409 | *num = ARRAY_SIZE(early_gpio_table); |
| 410 | return early_gpio_table; |
| 411 | } |