Mario Scheithauer | 092db95 | 2017-01-31 15:45:13 +0100 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
Mario Scheithauer | 092db95 | 2017-01-31 15:45:13 +0100 | [diff] [blame] | 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify |
| 6 | * it under the terms of the GNU General Public License as published by |
| 7 | * the Free Software Foundation; version 2 of the License. |
| 8 | * |
| 9 | * This program is distributed in the hope that it will be useful, |
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 12 | * GNU General Public License for more details. |
| 13 | */ |
| 14 | |
Ravi Sarawadi | efa606b | 2017-08-04 16:26:09 -0700 | [diff] [blame] | 15 | #include <console/console.h> |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 16 | #include <device/mmio.h> |
Mario Scheithauer | 092db95 | 2017-01-31 15:45:13 +0100 | [diff] [blame] | 17 | #include <device/device.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 18 | #include <device/pci_ops.h> |
Mario Scheithauer | b83858a | 2017-09-05 15:32:49 +0200 | [diff] [blame] | 19 | #include <device/pci_ids.h> |
Mario Scheithauer | 480eab0 | 2017-02-16 13:39:16 +0100 | [diff] [blame] | 20 | #include <hwilib.h> |
| 21 | #include <i210.h> |
Mario Scheithauer | 0af272c | 2018-04-10 12:40:11 +0200 | [diff] [blame] | 22 | #include <intelblocks/cpulib.h> |
Mario Scheithauer | 0af272c | 2018-04-10 12:40:11 +0200 | [diff] [blame] | 23 | #include <intelblocks/systemagent.h> |
Ravi Sarawadi | efa606b | 2017-08-04 16:26:09 -0700 | [diff] [blame] | 24 | #include <soc/pci_devs.h> |
| 25 | #include <string.h> |
Werner Zeh | efd0eb3 | 2017-09-12 08:58:44 +0200 | [diff] [blame] | 26 | #include <timer.h> |
Mario Scheithauer | d127be1 | 2018-04-23 10:55:39 +0200 | [diff] [blame] | 27 | #include <baseboard/variants.h> |
Elyes HAOUAS | e39db68 | 2019-05-15 21:12:31 +0200 | [diff] [blame] | 28 | #include <types.h> |
Mario Scheithauer | 480eab0 | 2017-02-16 13:39:16 +0100 | [diff] [blame] | 29 | |
| 30 | #define MAX_PATH_DEPTH 12 |
| 31 | #define MAX_NUM_MAPPINGS 10 |
| 32 | |
Mario Scheithauer | 0af272c | 2018-04-10 12:40:11 +0200 | [diff] [blame] | 33 | #define BIOS_MAILBOX_WAIT_MAX_MS 1000 |
| 34 | #define BIOS_MAILBOX_DATA 0x7080 |
| 35 | #define BIOS_MAILBOX_INTERFACE 0x7084 |
| 36 | #define RUN_BUSY_STS (1 << 31) |
| 37 | |
Werner Zeh | d5de063 | 2018-09-19 11:06:22 +0200 | [diff] [blame] | 38 | /* |
| 39 | * SPI Opcode Menu setup for SPIBAR lock down |
| 40 | * should support most common flash chips. |
| 41 | */ |
| 42 | #define SPI_OPMENU_0 0x01 /* WRSR: Write Status Register */ |
| 43 | #define SPI_OPTYPE_0 0x01 /* Write, no address */ |
| 44 | |
| 45 | #define SPI_OPMENU_1 0x02 /* PP: Page Program */ |
| 46 | #define SPI_OPTYPE_1 0x03 /* Write, address required */ |
| 47 | |
| 48 | #define SPI_OPMENU_2 0x03 /* READ: Read Data */ |
| 49 | #define SPI_OPTYPE_2 0x02 /* Read, address required */ |
| 50 | |
| 51 | #define SPI_OPMENU_3 0x05 /* RDSR: Read Status Register */ |
| 52 | #define SPI_OPTYPE_3 0x00 /* Read, no address */ |
| 53 | |
| 54 | #define SPI_OPMENU_4 0x20 /* SE20: Sector Erase 0x20 */ |
| 55 | #define SPI_OPTYPE_4 0x03 /* Write, address required */ |
| 56 | |
| 57 | #define SPI_OPMENU_5 0x9f /* RDID: Read ID */ |
| 58 | #define SPI_OPTYPE_5 0x00 /* Read, no address */ |
| 59 | |
| 60 | #define SPI_OPMENU_6 0xd8 /* BED8: Block Erase 0xd8 */ |
| 61 | #define SPI_OPTYPE_6 0x03 /* Write, address required */ |
| 62 | |
| 63 | #define SPI_OPMENU_7 0x0b /* FAST: Fast Read */ |
| 64 | #define SPI_OPTYPE_7 0x02 /* Read, address required */ |
| 65 | |
| 66 | #define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \ |
| 67 | (SPI_OPMENU_5 << 8) | SPI_OPMENU_4) |
| 68 | #define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \ |
| 69 | (SPI_OPMENU_1 << 8) | SPI_OPMENU_0) |
| 70 | |
| 71 | #define SPI_OPTYPE ((SPI_OPTYPE_7 << 14) | (SPI_OPTYPE_6 << 12) | \ |
| 72 | (SPI_OPTYPE_5 << 10) | (SPI_OPTYPE_4 << 8) | \ |
| 73 | (SPI_OPTYPE_3 << 6) | (SPI_OPTYPE_2 << 4) | \ |
| 74 | (SPI_OPTYPE_1 << 2) | (SPI_OPTYPE_0)) |
| 75 | |
| 76 | #define SPI_OPPREFIX ((0x50 << 8) | 0x06) /* EWSR and WREN */ |
| 77 | |
| 78 | #define SPIBAR_OFFSET 0x3800 |
| 79 | #define SPI_REG_PREOP_OPTYPE 0xa4 |
| 80 | #define SPI_REG_OPMENU_L 0xa8 |
| 81 | #define SPI_REG_OPMENU_H 0xac |
| 82 | |
Mario Scheithauer | 7815c07 | 2019-07-17 09:40:33 +0200 | [diff] [blame] | 83 | #define SD_CAP_BYP 0x810 |
| 84 | #define SD_CAP_BYP_EN 0x5A |
| 85 | #define SD_CAP_BYP_REG1 0x814 |
| 86 | |
Mario Scheithauer | 480eab0 | 2017-02-16 13:39:16 +0100 | [diff] [blame] | 87 | /** \brief This function can decide if a given MAC address is valid or not. |
| 88 | * Currently, addresses filled with 0xff or 0x00 are not valid. |
| 89 | * @param mac Buffer to the MAC address to check |
| 90 | * @return 0 if address is not valid, otherwise 1 |
| 91 | */ |
| 92 | static uint8_t is_mac_adr_valid(uint8_t mac[6]) |
| 93 | { |
| 94 | uint8_t buf[6]; |
| 95 | |
| 96 | memset(buf, 0, sizeof(buf)); |
| 97 | if (!memcmp(buf, mac, sizeof(buf))) |
| 98 | return 0; |
| 99 | memset(buf, 0xff, sizeof(buf)); |
| 100 | if (!memcmp(buf, mac, sizeof(buf))) |
| 101 | return 0; |
| 102 | return 1; |
| 103 | } |
| 104 | |
| 105 | /** \brief This function will search for a MAC address which can be assigned |
| 106 | * to a MACPHY. |
| 107 | * @param dev pointer to PCI device |
| 108 | * @param mac buffer where to store the MAC address |
| 109 | * @return cb_err CB_ERR or CB_SUCCESS |
| 110 | */ |
| 111 | enum cb_err mainboard_get_mac_address(struct device *dev, uint8_t mac[6]) |
| 112 | { |
| 113 | struct bus *parent = dev->bus; |
| 114 | uint8_t buf[16], mapping[16], i = 0, chain_len = 0; |
| 115 | |
| 116 | memset(buf, 0, sizeof(buf)); |
| 117 | memset(mapping, 0, sizeof(mapping)); |
| 118 | |
| 119 | /* The first entry in the tree is the device itself. */ |
| 120 | buf[0] = dev->path.pci.devfn; |
| 121 | chain_len = 1; |
| 122 | for (i = 1; i < MAX_PATH_DEPTH && parent->dev->bus->subordinate; i++) { |
| 123 | buf[i] = parent->dev->path.pci.devfn; |
| 124 | chain_len++; |
| 125 | parent = parent->dev->bus; |
| 126 | } |
| 127 | if (i == MAX_PATH_DEPTH) { |
| 128 | /* The path is deeper than MAX_PATH_DEPTH devices, error. */ |
| 129 | printk(BIOS_ERR, "Too many bridges for %s\n", dev_path(dev)); |
| 130 | return CB_ERR; |
| 131 | } |
| 132 | /* |
| 133 | * Now construct the mapping based on the device chain starting from |
| 134 | * root bridge device to the device itself. |
| 135 | */ |
| 136 | mapping[0] = 1; |
| 137 | mapping[1] = chain_len; |
| 138 | for (i = 0; i < chain_len; i++) |
| 139 | mapping[i + 4] = buf[chain_len - i - 1]; |
| 140 | |
| 141 | /* Open main hwinfo block */ |
| 142 | if (hwilib_find_blocks("hwinfo.hex") != CB_SUCCESS) |
| 143 | return CB_ERR; |
| 144 | /* Now try to find a valid MAC address in hwinfo for this mapping.*/ |
| 145 | for (i = 0; i < MAX_NUM_MAPPINGS; i++) { |
| 146 | if ((hwilib_get_field(XMac1Mapping + i, buf, 16) == 16) && |
| 147 | !(memcmp(buf, mapping, chain_len + 4))) { |
| 148 | /* There is a matching mapping available, get MAC address. */ |
| 149 | if ((hwilib_get_field(XMac1 + i, mac, 6) == 6) && |
| 150 | (is_mac_adr_valid(mac))) { |
| 151 | return CB_SUCCESS; |
| 152 | } else { |
| 153 | return CB_ERR; |
| 154 | } |
| 155 | } else |
| 156 | continue; |
| 157 | } |
| 158 | /* No MAC address found for */ |
| 159 | return CB_ERR; |
| 160 | } |
Mario Scheithauer | 092db95 | 2017-01-31 15:45:13 +0100 | [diff] [blame] | 161 | |
Mario Scheithauer | 0af272c | 2018-04-10 12:40:11 +0200 | [diff] [blame] | 162 | /** \brief This function fixes an accuracy issue with IDT PMIC. |
| 163 | * The current reported system power consumption is higher than the |
| 164 | * actual consumption. With a correction of slope and offset for Vcc |
| 165 | * and Vnn, the issue is solved. |
| 166 | */ |
| 167 | static void config_pmic_imon(void) |
| 168 | { |
| 169 | struct stopwatch sw; |
| 170 | uint32_t power_max; |
| 171 | |
| 172 | printk(BIOS_DEBUG, "PMIC: Configure PMIC IMON - Start\n"); |
| 173 | |
| 174 | /* Calculate CPU TDP in mW */ |
| 175 | power_max = cpu_get_power_max(); |
| 176 | printk(BIOS_INFO, "PMIC: CPU TDP %d mW.\n", power_max); |
| 177 | |
| 178 | /* |
| 179 | * Fix Vnn slope and offset value. |
| 180 | * slope = 0x4a4 # 2.32 |
| 181 | * offset = 0xfa0d # -2.975 |
| 182 | */ |
| 183 | stopwatch_init_msecs_expire(&sw, BIOS_MAILBOX_WAIT_MAX_MS); |
| 184 | /* Read P_CR_BIOS_MAILBOX_INTERFACE_0_0_0_MCHBAR and check RUN_BUSY. */ |
| 185 | while ((MCHBAR32(BIOS_MAILBOX_INTERFACE) & RUN_BUSY_STS)) { |
| 186 | if (stopwatch_expired(&sw)) { |
| 187 | printk(BIOS_ERR, "PMIC: Power consumption measurement " |
| 188 | "setup fails for Vnn.\n"); |
| 189 | return; |
| 190 | } |
| 191 | } |
| 192 | /* Set Vnn values into P_CR_BIOS_MAILBOX_DATA_0_0_0_MCHBAR. */ |
| 193 | MCHBAR32(BIOS_MAILBOX_DATA) = 0xfa0d04a4; |
| 194 | /* Set command, address and busy bit. */ |
| 195 | MCHBAR32(BIOS_MAILBOX_INTERFACE) = 0x8000011d; |
| 196 | printk(BIOS_DEBUG, "PMIC: Fix Vnn slope and offset value.\n"); |
| 197 | |
| 198 | /* |
| 199 | * Fix Vcc slope and offset value. |
| 200 | * Premium and High SKU: |
| 201 | * slope = 0x466 # 2.2 |
| 202 | * offset = 0xe833 # -11.9 |
| 203 | * Low and Intermediate SKU: |
| 204 | * slope = 0x3b3 # 1.85 |
| 205 | * offset = 0xed33 # -9.4 |
| 206 | */ |
| 207 | stopwatch_init_msecs_expire(&sw, BIOS_MAILBOX_WAIT_MAX_MS); |
| 208 | while ((MCHBAR32(BIOS_MAILBOX_INTERFACE) & RUN_BUSY_STS)) { |
| 209 | if (stopwatch_expired(&sw)) { |
| 210 | printk(BIOS_ERR, "PMIC: Power consumption measurement " |
| 211 | "setup fails for Vcc.\n"); |
| 212 | return; |
| 213 | } |
| 214 | } |
| 215 | |
| 216 | /* |
| 217 | * CPU TDP limit between Premium/High and Low/Intermediate SKU |
| 218 | * is 9010 mW. |
| 219 | */ |
| 220 | if (power_max > 9010) { |
| 221 | MCHBAR32(BIOS_MAILBOX_DATA) = 0xe8330466; |
| 222 | MCHBAR32(BIOS_MAILBOX_INTERFACE) = 0x8000001d; |
| 223 | printk(BIOS_INFO, "PMIC: Fix Vcc for Premium SKU.\n"); |
| 224 | } else { |
| 225 | MCHBAR32(BIOS_MAILBOX_DATA) = 0xed3303b3; |
| 226 | MCHBAR32(BIOS_MAILBOX_INTERFACE) = 0x8000001d; |
| 227 | printk(BIOS_INFO, "PMIC: Fix Vcc for Low SKU.\n"); |
| 228 | } |
| 229 | |
| 230 | printk(BIOS_DEBUG, "PMIC: Configure PMIC IMON - End\n"); |
| 231 | } |
| 232 | |
Mario Scheithauer | 092db95 | 2017-01-31 15:45:13 +0100 | [diff] [blame] | 233 | static void mainboard_init(void *chip_info) |
| 234 | { |
Mario Scheithauer | 2d98120 | 2017-03-27 13:25:57 +0200 | [diff] [blame] | 235 | const struct pad_config *pads; |
| 236 | size_t num; |
| 237 | |
Mario Scheithauer | d127be1 | 2018-04-23 10:55:39 +0200 | [diff] [blame] | 238 | pads = variant_gpio_table(&num); |
Mario Scheithauer | 2d98120 | 2017-03-27 13:25:57 +0200 | [diff] [blame] | 239 | gpio_configure_pads(pads, num); |
Mario Scheithauer | 0af272c | 2018-04-10 12:40:11 +0200 | [diff] [blame] | 240 | |
| 241 | config_pmic_imon(); |
Mario Scheithauer | 092db95 | 2017-01-31 15:45:13 +0100 | [diff] [blame] | 242 | } |
| 243 | |
Mario Scheithauer | 956a9f6 | 2017-03-29 17:09:37 +0200 | [diff] [blame] | 244 | static void mainboard_final(void *chip_info) |
| 245 | { |
Mario Scheithauer | b83858a | 2017-09-05 15:32:49 +0200 | [diff] [blame] | 246 | uint16_t cmd = 0; |
Elyes HAOUAS | 47503cd | 2018-05-04 21:58:51 +0200 | [diff] [blame] | 247 | struct device *dev = NULL; |
Werner Zeh | d5de063 | 2018-09-19 11:06:22 +0200 | [diff] [blame] | 248 | void *spi_base = NULL; |
Mario Scheithauer | 956a9f6 | 2017-03-29 17:09:37 +0200 | [diff] [blame] | 249 | |
Mario Scheithauer | 6141353 | 2018-04-25 14:05:09 +0200 | [diff] [blame] | 250 | /* Do board specific things */ |
| 251 | variant_mainboard_final(); |
Mario Scheithauer | b83858a | 2017-09-05 15:32:49 +0200 | [diff] [blame] | 252 | |
| 253 | /* Set Master Enable for on-board PCI device. */ |
| 254 | dev = dev_find_device(PCI_VENDOR_ID_SIEMENS, 0x403f, 0); |
| 255 | if (dev) { |
| 256 | cmd = pci_read_config16(dev, PCI_COMMAND); |
| 257 | cmd |= PCI_COMMAND_MASTER; |
| 258 | pci_write_config16(dev, PCI_COMMAND, cmd); |
| 259 | } |
Werner Zeh | d5de063 | 2018-09-19 11:06:22 +0200 | [diff] [blame] | 260 | /* Set up SPI OPCODE menu before the controller is locked. */ |
| 261 | dev = PCH_DEV_SPI; |
| 262 | spi_base = (void *)pci_read_config32(dev, PCI_BASE_ADDRESS_0); |
| 263 | if (!spi_base) |
| 264 | return; |
| 265 | write32((spi_base + SPI_REG_PREOP_OPTYPE), |
| 266 | ((SPI_OPTYPE << 16) | SPI_OPPREFIX)); |
| 267 | write32((spi_base + SPI_REG_OPMENU_L), SPI_OPMENU_LOWER); |
| 268 | write32((spi_base + SPI_REG_OPMENU_H), SPI_OPMENU_UPPER); |
Mario Scheithauer | 7815c07 | 2019-07-17 09:40:33 +0200 | [diff] [blame] | 269 | |
| 270 | /* Set SD-Card speed to HS mode only. */ |
| 271 | dev = pcidev_path_on_root(PCH_DEVFN_SDCARD); |
| 272 | if (dev) { |
| 273 | uint32_t reg; |
| 274 | struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0); |
| 275 | if (!res) |
| 276 | return; |
| 277 | |
| 278 | write32(res2mmio(res, SD_CAP_BYP, 0), SD_CAP_BYP_EN); |
| 279 | reg = read32(res2mmio(res, SD_CAP_BYP_REG1, 0)); |
| 280 | /* Disable all UHS-I SD-Card speed modes, keep only HS mode. */ |
| 281 | reg &= ~0x2000f800; |
| 282 | write32(res2mmio(res, SD_CAP_BYP_REG1, 0), reg); |
| 283 | } |
Mario Scheithauer | 956a9f6 | 2017-03-29 17:09:37 +0200 | [diff] [blame] | 284 | } |
| 285 | |
Mario Scheithauer | 6141353 | 2018-04-25 14:05:09 +0200 | [diff] [blame] | 286 | /* The following function performs board specific things. */ |
| 287 | void __weak variant_mainboard_final(void) |
Werner Zeh | efd0eb3 | 2017-09-12 08:58:44 +0200 | [diff] [blame] | 288 | { |
Werner Zeh | efd0eb3 | 2017-09-12 08:58:44 +0200 | [diff] [blame] | 289 | } |
| 290 | |
Mario Scheithauer | 092db95 | 2017-01-31 15:45:13 +0100 | [diff] [blame] | 291 | struct chip_operations mainboard_ops = { |
| 292 | .init = mainboard_init, |
Mario Scheithauer | 956a9f6 | 2017-03-29 17:09:37 +0200 | [diff] [blame] | 293 | .final = mainboard_final, |
Mario Scheithauer | 092db95 | 2017-01-31 15:45:13 +0100 | [diff] [blame] | 294 | }; |