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Bingxun Shifb1fddb2007-02-09 00:26:10 +00001/*
Stefan Reinauer7e61e452008-01-18 10:35:56 +00002 * This file is part of the coreboot project.
Bingxun Shifb1fddb2007-02-09 00:26:10 +00003 *
4 * Copyright (C) 2006 AMD
5 * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
6 *
7 * Copyright (C) 2006 MSI
8 * Written by Bingxun Shi <bingxunshi@gmail.com> for MSI.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
Paul Menzela46a7122013-02-23 18:37:27 +010022 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
Bingxun Shifb1fddb2007-02-09 00:26:10 +000023 */
24
25#include <console/console.h>
26#include <device/pci.h>
27#include <device/pci_ids.h>
28#include <string.h>
29#include <stdint.h>
Patrick Georgie1667822012-05-05 15:29:32 +020030#if CONFIG_LOGICAL_CPUS
Stefan Reinauer9a16e3e2010-03-29 14:45:36 +000031#include <cpu/amd/multicore.h>
Bingxun Shifb1fddb2007-02-09 00:26:10 +000032#endif
33
34#include <cpu/amd/amdk8_sysconf.h>
35
Carl-Daniel Hailfinger2ee67792008-10-01 12:52:52 +000036#include <stdlib.h>
Bingxun Shifb1fddb2007-02-09 00:26:10 +000037#include "mb_sysconf.h"
38
39// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
40struct mb_sysconf_t mb_sysconf;
41
Paul Menzel6a4e9b52013-10-18 09:42:55 +020042unsigned pci1234x[] = { //Here you only need to set value in pci1234 for HT-IO that could be installed or not
43 //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
44 0x0000ff0,
45 0x0000ff0,
46 0x0000ff0,
Bingxun Shifb1fddb2007-02-09 00:26:10 +000047// 0x0000ff0,
48// 0x0000ff0,
49// 0x0000ff0,
50// 0x0000ff0,
51// 0x0000ff0
52};
Paul Menzel6a4e9b52013-10-18 09:42:55 +020053
54unsigned hcdnx[] = { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most
55 0x20202020,
56 0x20202020,
57 0x20202020,
Bingxun Shifb1fddb2007-02-09 00:26:10 +000058// 0x20202020,
59// 0x20202020,
60// 0x20202020,
61// 0x20202020,
62// 0x20202020,
63};
64
Bingxun Shifb1fddb2007-02-09 00:26:10 +000065static unsigned get_bus_conf_done = 0;
66
Bingxun Shifb1fddb2007-02-09 00:26:10 +000067void get_bus_conf(void)
68{
69
Paul Menzel6a4e9b52013-10-18 09:42:55 +020070 unsigned apicid_base;
71 struct mb_sysconf_t *m;
Bingxun Shifb1fddb2007-02-09 00:26:10 +000072
Paul Menzel6a4e9b52013-10-18 09:42:55 +020073 device_t dev;
74 int i;
Bingxun Shifb1fddb2007-02-09 00:26:10 +000075
Paul Menzel6a4e9b52013-10-18 09:42:55 +020076 if (get_bus_conf_done == 1)
77 return; //do it only once
Bingxun Shifb1fddb2007-02-09 00:26:10 +000078
Paul Menzel6a4e9b52013-10-18 09:42:55 +020079 get_bus_conf_done = 1;
Bingxun Shifb1fddb2007-02-09 00:26:10 +000080
Paul Menzel6a4e9b52013-10-18 09:42:55 +020081 sysconf.mb = &mb_sysconf;
Bingxun Shifb1fddb2007-02-09 00:26:10 +000082
Paul Menzel6a4e9b52013-10-18 09:42:55 +020083 m = sysconf.mb;
84 memset(m, 0, sizeof(struct mb_sysconf_t));
Bingxun Shifb1fddb2007-02-09 00:26:10 +000085
Paul Menzel6a4e9b52013-10-18 09:42:55 +020086 sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
87 for (i = 0; i < sysconf.hc_possible_num; i++) {
88 sysconf.pci1234[i] = pci1234x[i];
89 sysconf.hcdn[i] = hcdnx[i];
90 }
Bingxun Shifb1fddb2007-02-09 00:26:10 +000091
Paul Menzel6a4e9b52013-10-18 09:42:55 +020092 get_sblk_pci1234();
Bingxun Shifb1fddb2007-02-09 00:26:10 +000093
Paul Menzel6a4e9b52013-10-18 09:42:55 +020094 sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain
Bingxun Shifb1fddb2007-02-09 00:26:10 +000095
Paul Menzel6a4e9b52013-10-18 09:42:55 +020096 m->bus_mcp55[0] = (sysconf.pci1234[0] >> 16) & 0xff;
Bingxun Shifb1fddb2007-02-09 00:26:10 +000097
Paul Menzel6a4e9b52013-10-18 09:42:55 +020098 /* MCP55 */
99 dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x06, 0));
100 if (dev) {
101 m->bus_mcp55[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
102 } else {
103 printk(BIOS_DEBUG,
104 "ERROR - could not find PCI 1:%02x.0, using defaults\n",
105 sysconf.sbdn + 0x06);
106 }
Bingxun Shifb1fddb2007-02-09 00:26:10 +0000107
Paul Menzel6a4e9b52013-10-18 09:42:55 +0200108 for (i = 2; i < 8; i++) {
109 dev =
110 dev_find_slot(m->bus_mcp55[0],
111 PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2, 0));
112 if (dev) {
113 m->bus_mcp55[i] =
114 pci_read_config8(dev, PCI_SECONDARY_BUS);
115 } else {
116 printk(BIOS_DEBUG,
117 "ERROR - could not find PCI %02x:%02x.0, using defaults\n",
118 m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2);
119 }
120 }
Bingxun Shifb1fddb2007-02-09 00:26:10 +0000121
Bingxun Shifb1fddb2007-02-09 00:26:10 +0000122/*I/O APICs: APIC ID Version State Address*/
Patrick Georgie1667822012-05-05 15:29:32 +0200123#if CONFIG_LOGICAL_CPUS
Paul Menzel6a4e9b52013-10-18 09:42:55 +0200124 apicid_base = get_apicid_base(1);
Bingxun Shifb1fddb2007-02-09 00:26:10 +0000125#else
Paul Menzel6a4e9b52013-10-18 09:42:55 +0200126 apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
Bingxun Shifb1fddb2007-02-09 00:26:10 +0000127#endif
Paul Menzel6a4e9b52013-10-18 09:42:55 +0200128 m->apicid_mcp55 = apicid_base + 0;
Bingxun Shifb1fddb2007-02-09 00:26:10 +0000129
130}