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Stefan Reinauer9d5e36e2015-04-27 13:40:16 -07001# TODO These two options look too similar
Kyösti Mälkki5c3f3842014-05-08 15:27:15 +03002config PARALLEL_CPU_INIT
Sven Schnellea2701c62012-07-29 17:42:52 +02003 bool
Kyösti Mälkki5c3f3842014-05-08 15:27:15 +03004 default n
Sven Schnellea2701c62012-07-29 17:42:52 +02005
Stefan Reinauer9d5e36e2015-04-27 13:40:16 -07006config PARALLEL_MP
7 def_bool n
8 help
9 This option uses common MP infrastructure for bringing up APs
10 in parallel. It additionally provides a more flexible mechanism
11 for sequencing the steps of bringing up the APs.
12
Aaron Durbinb21e3622016-12-07 00:32:19 -060013config PARALLEL_MP_AP_WORK
14 def_bool n
15 depends on PARALLEL_MP
16 help
17 Allow APs to do other work after initialization instead of going
18 to sleep.
Stefan Reinauer9d5e36e2015-04-27 13:40:16 -070019
Patrick Georgi0e9a9252009-10-06 20:48:07 +000020config UDELAY_IO
21 bool
Aaron Durbinf70c1bf2018-01-24 17:20:11 -070022 default y if !UDELAY_LAPIC && !UDELAY_TSC && !UDELAY_TIMER2 && !GENERIC_UDELAY
Patrick Georgi0e9a9252009-10-06 20:48:07 +000023 default n
24
25config UDELAY_LAPIC
26 bool
27 default n
28
Aaron Durbinfd8291c2013-04-29 17:18:49 -050029config LAPIC_MONOTONIC_TIMER
30 def_bool n
31 depends on UDELAY_LAPIC
32 select HAVE_MONOTONIC_TIMER
33 help
Elyes HAOUASd6e96862016-08-21 10:12:15 +020034 Expose monotonic time using the local APIC.
Aaron Durbinfd8291c2013-04-29 17:18:49 -050035
Patrick Georgie135ac52012-11-20 11:53:47 +010036config UDELAY_LAPIC_FIXED_FSB
37 int
38
Ronald G. Minnich669c4a92009-08-29 03:00:51 +000039config UDELAY_TSC
40 bool
41 default n
42
Aaron Durbin8e73b5d2013-05-01 15:27:09 -050043config TSC_CONSTANT_RATE
44 def_bool n
45 depends on UDELAY_TSC
46 help
47 This option asserts that the TSC ticks at a known constant rate.
48 Therefore, no TSC calibration is required.
49
Aaron Durbine8501642013-04-29 22:22:55 -050050config TSC_MONOTONIC_TIMER
51 def_bool n
52 depends on UDELAY_TSC
53 select HAVE_MONOTONIC_TIMER
54 help
55 Expose monotonic time using the TSC.
56
Stefan Reinauer9d5e36e2015-04-27 13:40:16 -070057# This option is used in code but never selected.
Stefan Reinauer9d5e36e2015-04-27 13:40:16 -070058config UDELAY_TIMER2
Ronald G. Minnich669c4a92009-08-29 03:00:51 +000059 bool
60 default n
61
Stefan Reinauer0db68202012-08-07 14:44:51 -070062config TSC_SYNC_LFENCE
63 bool
64 default n
65 help
66 The CPU driver should select this if the CPU needs
67 to execute an lfence instruction in order to synchronize
68 rdtsc. This is true for all modern AMD CPUs.
69
70config TSC_SYNC_MFENCE
71 bool
72 default n
73 help
74 The CPU driver should select this if the CPU needs
75 to execute an mfence instruction in order to synchronize
76 rdtsc. This is true for all modern Intel CPUs.
77
Aaron Durbinef105292016-05-05 10:34:22 -050078config NO_FIXED_XIP_ROM_SIZE
79 bool
80 default n
81 help
82 The XIP_ROM_SIZE Kconfig variable is used globally on x86
83 with the assumption that all chipsets utilize this value.
84 For the chipsets which do not use the variable it can lead
85 to unnecessary alignment constraints in cbfs for romstage.
86 Therefore, allow those chipsets a path to not be burdened.
87
Uwe Hermannf9d4c2b2009-08-25 12:19:28 +000088config XIP_ROM_SIZE
Patrick Georgi0588d192009-08-12 15:00:51 +000089 hex
Aaron Durbinef105292016-05-05 10:34:22 -050090 depends on !NO_FIXED_XIP_ROM_SIZE
Patrick Georgi1c93d902012-03-16 21:16:55 +010091 default ROM_SIZE if ROMCC
Patrick Georgif1ce6f22010-04-12 09:50:53 +000092 default 0x10000
Stefan Reinauer8aedcbc2010-12-16 23:37:17 +000093
94config CPU_ADDR_BITS
95 int
96 default 36
97
98config LOGICAL_CPUS
99 bool
100 default y
101
Duncan Laurie8bb77232012-01-09 22:11:25 -0800102config SMM_TSEG
103 bool
104 default n
Aaron Durbin50a34642013-01-03 17:38:47 -0600105 select RELOCATABLE_MODULES
Aaron Durbin50a34642013-01-03 17:38:47 -0600106
107config SMM_MODULE_HEAP_SIZE
108 hex
109 default 0x4000
Vladimir Serbinenko44cbe102015-05-28 21:09:31 +0200110 depends on SMM_TSEG
Aaron Durbin50a34642013-01-03 17:38:47 -0600111 help
112 This option determines the size of the heap within the SMM handler
113 modules.
Aaron Durbin57686f82013-03-20 15:50:59 -0500114
Patrick Georgice2564a2015-09-05 20:21:24 +0200115config SMM_LAPIC_REMAP_MITIGATION
116 bool
117 default y if NORTHBRIDGE_INTEL_I945
118 default y if NORTHBRIDGE_INTEL_GM45
119 default y if NORTHBRIDGE_INTEL_NEHALEM
120 default n
121
Damien Zammit149c4c52015-11-28 21:27:05 +1100122config SERIALIZED_SMM_INITIALIZATION
123 bool
124 default n
125 help
126 On some CPUs, there is a race condition in SMM.
127 This can occur when both hyperthreads change SMM state
128 variables in parallel without coordination.
129 Setting this option serializes the SMM initialization
130 to avoid an ugly hang in the boot process at the cost
131 of a slightly longer boot time.
132
Aaron Durbin57686f82013-03-20 15:50:59 -0500133config X86_AMD_FIXED_MTRRS
134 bool
135 default n
136 help
137 This option informs the MTRR code to use the RdMem and WrMem fields
138 in the fixed MTRR MSRs.
Aaron Durbine0785c02013-10-21 12:15:29 -0500139
Marc Jones78687972015-04-22 23:16:31 -0600140config PLATFORM_USES_FSP1_0
Martin Rotha6427162014-04-25 14:12:13 -0600141 bool
142 default n
143 help
144 Selected for Intel processors/platform combinations that use the
Marc Jones78687972015-04-22 23:16:31 -0600145 Intel Firmware Support Package (FSP) 1.0 for initialization.
Martin Rotha6427162014-04-25 14:12:13 -0600146
Aaron Durbinc34713d2014-02-25 20:36:56 -0600147config MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING
148 def_bool n
149 help
150 On certain platforms a boot speed gain can be realized if mirroring
151 the payload data stored in non-volatile storage. On x86 systems the
152 payload would typically live in a memory-mapped SPI part. Copying
Daniele Forsi53847a22014-07-22 18:00:56 +0200153 the SPI contents to RAM before performing the load can speed up
Aaron Durbinc34713d2014-02-25 20:36:56 -0600154 the boot process.
David Hendricksbe6f8cb2014-03-21 17:09:29 -0700155
Lee Leahyae738ac2016-07-24 08:03:37 -0700156config SOC_SETS_MSRS
157 bool
158 default n
159 help
160 The SoC requires different access methods for reading and writing
161 the MSRs. Use SoC specific routines to handle the MSR access.