blob: 4aea1a02c9603c94c38d197c427eca52c682c8dc [file] [log] [blame]
Timothy Pearsonbfa19e12016-01-05 11:00:49 -06001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2016 Raptor Engineering
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <stdint.h>
17#include <cpu/x86/msr.h>
18#include <cpu/x86/tsc.h>
19
20unsigned long tsc_freq_mhz(void)
21{
22 msr_t msr;
23 uint8_t cpufid;
24 uint8_t cpudid;
25
26 /* On Family 10h/15h CPUs the TSC increments
Elyes HAOUAS2765a892016-09-01 19:44:56 +020027 * at the P0 clock rate. Read the P0 clock
28 * frequency from the P0 MSR and convert
29 * to MHz. See also the Family 15h BKDG
30 * Rev. 3.14 page 569.
31 */
Timothy Pearsonbfa19e12016-01-05 11:00:49 -060032 msr = rdmsr(0xc0010064);
33 cpufid = (msr.lo & 0x3f);
34 cpudid = (msr.lo & 0x1c0) >> 6;
35
36 return (100 * (cpufid + 0x10)) / (0x01 << cpudid);
37}