Frank Vibrans | 69da1b6 | 2011-02-14 19:04:45 +0000 | [diff] [blame^] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | */ |
| 19 | |
| 20 | |
| 21 | #include <console/console.h> |
| 22 | #include <arch/smp/mpspec.h> |
| 23 | #include <device/pci.h> |
| 24 | #include <arch/io.h> |
| 25 | #include <string.h> |
| 26 | #include <stdint.h> |
| 27 | #include <arch/cpu.h> |
| 28 | #include <cpu/x86/lapic.h> |
| 29 | |
| 30 | #define IO_APIC_ID CONFIG_MAX_PHYSICAL_CPUS + 1 |
| 31 | extern u8 bus_sb800[2]; |
| 32 | |
| 33 | |
| 34 | extern u32 bus_type[256]; |
| 35 | extern u32 sbdn_sb800; |
| 36 | u32 apicid_sb800; |
| 37 | |
| 38 | u8 picr_data[] = { |
| 39 | 0x0B,0x0A,0x0B,0x05,0x1F,0x1F,0x1F,0x1F,0x50,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F, |
| 40 | 0x1F,0x1F,0x1F,0x0B,0x1F,0x0B,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, |
| 41 | 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, |
| 42 | 0x0B,0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, |
| 43 | 0x0A,0x05,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, |
| 44 | 0x0B,0x0A,0x0B,0x05 |
| 45 | }; |
| 46 | u8 intr_data[] = { |
| 47 | 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, |
| 48 | 0x1F,0x1F,0x1F,0x10,0x1F,0x12,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, |
| 49 | 0x05,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, |
| 50 | 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, |
| 51 | 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, |
| 52 | 0x10,0x11,0x12,0x13 |
| 53 | }; |
| 54 | |
| 55 | static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned length) |
| 56 | { |
| 57 | mc->mpc_length += length; |
| 58 | mc->mpc_entry_count++; |
| 59 | } |
| 60 | static void my_smp_write_bus(struct mp_config_table *mc, |
| 61 | unsigned char id, const char *bustype) |
| 62 | { |
| 63 | struct mpc_config_bus *mpc; |
| 64 | mpc = smp_next_mpc_entry(mc); |
| 65 | memset(mpc, '\0', sizeof(*mpc)); |
| 66 | mpc->mpc_type = MP_BUS; |
| 67 | mpc->mpc_busid = id; |
| 68 | memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype)); |
| 69 | smp_add_mpc_entry(mc, sizeof(*mpc)); |
| 70 | } |
| 71 | static void *smp_write_config_table(void *v) |
| 72 | { |
| 73 | struct mp_config_table *mc; |
| 74 | int bus_isa; |
| 75 | int boot_apic_id; |
| 76 | unsigned apic_version; |
| 77 | unsigned cpu_features; |
| 78 | unsigned cpu_feature_flags; |
| 79 | struct cpuid_result result; |
| 80 | unsigned long cpu_flag; |
| 81 | |
| 82 | mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); |
| 83 | |
| 84 | mptable_init(mc, LAPIC_ADDR); |
| 85 | memcpy(mc->mpc_oem, "AMD ", 8); |
| 86 | |
| 87 | /*Inagua used dure core cpu with one die */ |
| 88 | boot_apic_id = lapicid(); |
| 89 | apic_version = lapic_read(LAPIC_LVR) & 0xff; |
| 90 | result = cpuid(1); |
| 91 | cpu_features = result.eax; |
| 92 | cpu_feature_flags = result.edx; |
| 93 | cpu_flag = MPC_CPU_ENABLED | MPC_CPU_BOOTPROCESSOR; |
| 94 | smp_write_processor(mc, |
| 95 | 0, apic_version, |
| 96 | cpu_flag, cpu_features, cpu_feature_flags |
| 97 | ); |
| 98 | |
| 99 | cpu_flag = MPC_CPU_ENABLED; |
| 100 | smp_write_processor(mc, |
| 101 | 1, apic_version, |
| 102 | cpu_flag, cpu_features, cpu_feature_flags |
| 103 | ); |
| 104 | |
| 105 | get_bus_conf(); |
| 106 | |
| 107 | //mptable_write_buses(mc, NULL, &bus_isa); |
| 108 | my_smp_write_bus(mc, 0, "PCI "); |
| 109 | my_smp_write_bus(mc, 1, "PCI "); |
| 110 | bus_isa = 0x02; |
| 111 | my_smp_write_bus(mc, bus_isa, "ISA "); |
| 112 | |
| 113 | /* I/O APICs: APIC ID Version State Address */ |
| 114 | |
| 115 | device_t dev; |
| 116 | u32 dword; |
| 117 | u8 byte; |
| 118 | |
| 119 | dword = 0; |
| 120 | dword = pm_ioread(0x34) & 0xF0; |
| 121 | dword |= (pm_ioread(0x35) & 0xFF) << 8; |
| 122 | dword |= (pm_ioread(0x36) & 0xFF) << 16; |
| 123 | dword |= (pm_ioread(0x37) & 0xFF) << 24; |
| 124 | /* Set IO APIC ID onto IO_APIC_ID */ |
| 125 | write32 (dword, 0x00); |
| 126 | write32 (dword + 0x10, IO_APIC_ID << 24); |
| 127 | apicid_sb800 = IO_APIC_ID; |
| 128 | smp_write_ioapic(mc, apicid_sb800, 0x21, dword); |
| 129 | |
| 130 | /* PIC IRQ routine */ |
| 131 | for (byte = 0x0; byte < sizeof(picr_data); byte ++) { |
| 132 | outb(byte, 0xC00); |
| 133 | outb(picr_data[byte], 0xC01); |
| 134 | } |
| 135 | |
| 136 | /* APIC IRQ routine */ |
| 137 | for (byte = 0x0; byte < sizeof(intr_data); byte ++) { |
| 138 | outb(byte | 0x80, 0xC00); |
| 139 | outb(intr_data[byte], 0xC01); |
| 140 | } |
| 141 | |
| 142 | /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ |
| 143 | #define IO_LOCAL_INT(type, intr, apicid, pin) \ |
| 144 | smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); |
| 145 | |
| 146 | //mptable_add_isa_interrupts(mc, bus_isa, apicid_sb800, 0); |
| 147 | /*I/O Ints: Type Trigger Polarity Bus ID IRQ APIC ID PIN# */ |
| 148 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_sb800, 0x0); |
| 149 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x1, apicid_sb800, 0x1); |
| 150 | smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x2, apicid_sb800, 0x2); |
| 151 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x3, apicid_sb800, 0x3); |
| 152 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x4, apicid_sb800, 0x4); |
| 153 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, 0x49, apicid_sb800, 0x11); |
| 154 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x6, apicid_sb800, 0x6); |
| 155 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x7, apicid_sb800, 0x7); |
| 156 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x8, apicid_sb800, 0x8); |
| 157 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x9, apicid_sb800, 0x9); |
| 158 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_isa, 0xa, apicid_sb800, 0xa); |
| 159 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_isa, 0x1c, apicid_sb800, 0x13); |
| 160 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xc, apicid_sb800, 0xc); |
| 161 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xd, apicid_sb800, 0xd); |
| 162 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xe, apicid_sb800, 0xe); |
| 163 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xf, apicid_sb800, 0xf); |
| 164 | |
| 165 | /* PCI interrupts are level triggered, and are |
| 166 | * associated with a specific bus/device/function tuple. |
| 167 | */ |
| 168 | #define PCI_INT(bus, dev, int_sign, pin) \ |
| 169 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_sb800, (pin)) |
| 170 | |
| 171 | /* SMBUS */ |
| 172 | PCI_INT(0x0, 0x14, 0x0, 0x10); |
| 173 | |
| 174 | /* HD Audio */ |
| 175 | PCI_INT(0x0, 0x14, 0x0, intr_data[0x13]); |
| 176 | |
| 177 | /* USB */ |
| 178 | PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); |
| 179 | PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]); |
| 180 | PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]); |
| 181 | PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]); |
| 182 | PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]); |
| 183 | PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]); |
| 184 | PCI_INT(0x0, 0x14, 0x2, intr_data[0x36]); |
| 185 | |
| 186 | /* sata */ |
| 187 | PCI_INT(0x0, 0x11, 0x0, intr_data[0x40]); |
| 188 | PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]); |
| 189 | |
| 190 | |
| 191 | /* on board NIC & Slot PCIE. */ |
| 192 | |
| 193 | /* PCI slots */ |
| 194 | /* PCI_SLOT 0. */ |
| 195 | PCI_INT(bus_sb800[1], 0x5, 0x0, 0x14); |
| 196 | PCI_INT(bus_sb800[1], 0x5, 0x1, 0x15); |
| 197 | PCI_INT(bus_sb800[1], 0x5, 0x2, 0x16); |
| 198 | PCI_INT(bus_sb800[1], 0x5, 0x3, 0x17); |
| 199 | |
| 200 | /* PCI_SLOT 1. */ |
| 201 | PCI_INT(bus_sb800[1], 0x6, 0x0, 0x15); |
| 202 | PCI_INT(bus_sb800[1], 0x6, 0x1, 0x16); |
| 203 | PCI_INT(bus_sb800[1], 0x6, 0x2, 0x17); |
| 204 | PCI_INT(bus_sb800[1], 0x6, 0x3, 0x14); |
| 205 | |
| 206 | /* PCI_SLOT 2. */ |
| 207 | PCI_INT(bus_sb800[1], 0x7, 0x0, 0x16); |
| 208 | PCI_INT(bus_sb800[1], 0x7, 0x1, 0x17); |
| 209 | PCI_INT(bus_sb800[1], 0x7, 0x2, 0x14); |
| 210 | PCI_INT(bus_sb800[1], 0x7, 0x3, 0x15); |
| 211 | |
| 212 | PCI_INT(bus_sb800[2], 0x0, 0x0, 0x12); |
| 213 | PCI_INT(bus_sb800[2], 0x0, 0x1, 0x13); |
| 214 | PCI_INT(bus_sb800[2], 0x0, 0x2, 0x14); |
| 215 | |
| 216 | /* PCIe Lan*/ |
| 217 | PCI_INT(0x0, 0x06, 0x0, 0x13); |
| 218 | |
| 219 | /* FCH PCIe PortA */ |
| 220 | PCI_INT(0x0, 0x15, 0x0, 0x10); |
| 221 | /* FCH PCIe PortB */ |
| 222 | PCI_INT(0x0, 0x15, 0x1, 0x11); |
| 223 | /* FCH PCIe PortC */ |
| 224 | PCI_INT(0x0, 0x15, 0x2, 0x12); |
| 225 | /* FCH PCIe PortD */ |
| 226 | PCI_INT(0x0, 0x15, 0x3, 0x13); |
| 227 | |
| 228 | /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ |
| 229 | IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0); |
| 230 | IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1); |
| 231 | /* There is no extension information... */ |
| 232 | |
| 233 | /* Compute the checksums */ |
| 234 | mc->mpe_checksum = |
| 235 | smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); |
| 236 | mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length); |
| 237 | printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n", |
| 238 | mc, smp_next_mpe_entry(mc)); |
| 239 | return smp_next_mpe_entry(mc); |
| 240 | } |
| 241 | |
| 242 | unsigned long write_smp_table(unsigned long addr) |
| 243 | { |
| 244 | void *v; |
| 245 | v = smp_write_floating_table(addr); |
| 246 | return (unsigned long)smp_write_config_table(v); |
| 247 | } |