blob: 8c98316655fdd22f60f71cf6d012c29b41af86ab [file] [log] [blame]
Patrick Georgiac959032020-05-05 22:49:26 +02001/* SPDX-License-Identifier: GPL-2.0-only */
Mukesh Savaliyab02452b2018-05-11 07:41:33 -07002
3#include <spi-generic.h>
4#include <spi_flash.h>
5#include <arch/cache.h>
Kyösti Mälkki13f66502019-03-03 08:01:05 +02006#include <device/mmio.h>
Mukesh Savaliyab02452b2018-05-11 07:41:33 -07007#include <soc/addressmap.h>
8#include <soc/qspi.h>
9#include <soc/gpio.h>
10#include <soc/clock.h>
11#include <symbols.h>
12#include <assert.h>
13#include <gpio.h>
14#include <string.h>
15
16#define CACHE_LINE_SIZE 64
17
18static int curr_desc_idx = -1;
19
20struct cmd_desc {
21 uint32_t data_address;
22 uint32_t next_descriptor;
23 uint32_t direction:1;
24 uint32_t multi_io_mode:3;
25 uint32_t reserved1:4;
26 uint32_t fragment:1;
27 uint32_t reserved2:7;
28 uint32_t length:16;
29 //------------------------//
30 uint32_t bounce_src;
31 uint32_t bounce_dst;
32 uint32_t bounce_length;
33 uint64_t padding[5];
34};
35
36enum qspi_mode {
37 SDR_1BIT = 1,
38 SDR_2BIT = 2,
39 SDR_4BIT = 3,
40 DDR_1BIT = 5,
41 DDR_2BIT = 6,
42 DDR_4BIT = 7,
43};
44
45enum cs_state {
46 CS_DEASSERT,
47 CS_ASSERT
48};
49
50struct xfer_cfg {
51 enum qspi_mode mode;
52};
53
54enum bus_xfer_direction {
55 MASTER_READ = 0,
56 MASTER_WRITE = 1,
57};
58
59struct {
60 struct cmd_desc descriptors[3];
61 uint8_t buffers[3][CACHE_LINE_SIZE];
62} *dma = (void *)_dma_coherent;
63
64static void dma_transfer_chain(struct cmd_desc *chain)
65{
66 uint32_t mstr_int_status;
67
68 write32(&sdm845_qspi->mstr_int_sts, 0xFFFFFFFF);
69 write32(&sdm845_qspi->next_dma_desc_addr, (uint32_t)(uintptr_t) chain);
70
71 while (1) {
72 mstr_int_status = read32(&sdm845_qspi->mstr_int_sts);
73 if (mstr_int_status & DMA_CHAIN_DONE)
74 break;
75 }
76}
77
78static void flush_chain(void)
79{
80 struct cmd_desc *desc = &dma->descriptors[0];
81 uint8_t *src;
82 uint8_t *dst;
83
84 dma_transfer_chain(desc);
85
86 while (desc) {
87 if (desc->direction == MASTER_READ) {
88 if (desc->bounce_length == 0)
89 dcache_invalidate_by_mva(
90 (void *)(uintptr_t) desc->data_address,
91 desc->length);
92 else {
93 src = (void *)(uintptr_t) desc->bounce_src;
94 dst = (void *)(uintptr_t) desc->bounce_dst;
95 memcpy(dst, src, desc->bounce_length);
96 }
97 }
98 desc = (void *)(uintptr_t) desc->next_descriptor;
99 }
100 curr_desc_idx = -1;
101}
102
103static struct cmd_desc *allocate_descriptor(void)
104{
105 struct cmd_desc *current;
106 struct cmd_desc *next;
107 uint8_t index;
108
109 current = (curr_desc_idx == -1) ?
110 NULL : &dma->descriptors[curr_desc_idx];
111
112 index = ++curr_desc_idx;
113 next = &dma->descriptors[index];
114
115 next->data_address = (uint32_t) (uintptr_t) dma->buffers[index];
116
117 next->next_descriptor = 0;
118 next->direction = MASTER_READ;
119 next->multi_io_mode = 0;
120 next->reserved1 = 0;
121 next->fragment = 0;
122 next->reserved2 = 0;
123 next->length = 0;
124 next->bounce_src = 0;
125 next->bounce_dst = 0;
126 next->bounce_length = 0;
127
128 if (current) {
129 current->next_descriptor = (uint32_t)(uintptr_t) next;
130 current->fragment = 1;
131 }
132
133 return next;
134}
135
136static void cs_change(enum cs_state state)
137{
138 gpio_set(GPIO(90), state == CS_DEASSERT);
139}
140
141static void configure_gpios(void)
142{
143 gpio_output(GPIO(90), 1);
144
145 gpio_configure(GPIO(91), GPIO91_FUNC_QSPI_DATA,
146 GPIO_NO_PULL, GPIO_2MA, GPIO_ENABLE);
147
148 gpio_configure(GPIO(92), GPIO92_FUNC_QSPI_DATA,
149 GPIO_NO_PULL, GPIO_2MA, GPIO_ENABLE);
150
151 gpio_configure(GPIO(95), GPIO95_FUNC_QSPI_CLK,
152 GPIO_NO_PULL, GPIO_2MA, GPIO_ENABLE);
153}
154
155static void queue_bounce_data(uint8_t *data, uint32_t data_bytes,
156 enum qspi_mode data_mode, bool write)
157{
158 struct cmd_desc *desc;
159 uint8_t *ptr;
160
161 desc = allocate_descriptor();
162 desc->direction = write;
163 desc->multi_io_mode = data_mode;
164 ptr = (void *)(uintptr_t) desc->data_address;
165
166 if (write) {
167 memcpy(ptr, data, data_bytes);
168 } else {
169 desc->bounce_src = (uint32_t)(uintptr_t) ptr;
170 desc->bounce_dst = (uint32_t)(uintptr_t) data;
171 desc->bounce_length = data_bytes;
172 }
173
174 desc->length = data_bytes;
175}
176
177static void queue_direct_data(uint8_t *data, uint32_t data_bytes,
178 enum qspi_mode data_mode, bool write)
179{
180 struct cmd_desc *desc;
181
182 desc = allocate_descriptor();
183 desc->direction = write;
184 desc->multi_io_mode = data_mode;
185 desc->data_address = (uint32_t)(uintptr_t) data;
186 desc->length = data_bytes;
187
188 if (write)
189 dcache_clean_by_mva(data, data_bytes);
190 else
191 dcache_invalidate_by_mva(data, data_bytes);
192}
193
194static void queue_data(uint8_t *data, uint32_t data_bytes,
195 enum qspi_mode data_mode, bool write)
196{
197 uint8_t *aligned_ptr;
198 uint8_t *epilog_ptr;
199 uint32_t prolog_bytes, aligned_bytes, epilog_bytes;
200
201 if (data_bytes == 0)
202 return;
203
204 aligned_ptr =
205 (uint8_t *)ALIGN_UP((uintptr_t)data, CACHE_LINE_SIZE);
206
207 prolog_bytes = MIN(data_bytes, aligned_ptr - data);
208 aligned_bytes = ALIGN_DOWN(data_bytes - prolog_bytes, CACHE_LINE_SIZE);
209 epilog_bytes = data_bytes - prolog_bytes - aligned_bytes;
210
211 epilog_ptr = data + prolog_bytes + aligned_bytes;
212
213 if (prolog_bytes)
214 queue_bounce_data(data, prolog_bytes, data_mode, write);
215 if (aligned_bytes)
216 queue_direct_data(aligned_ptr, aligned_bytes, data_mode, write);
217 if (epilog_bytes)
218 queue_bounce_data(epilog_ptr, epilog_bytes, data_mode, write);
219}
220
221static void reg_init(void)
222{
223 uint32_t spi_mode;
224 uint32_t tx_data_oe_delay, tx_data_delay;
225 uint32_t mstr_config;
226
227 spi_mode = 0;
228
229 tx_data_oe_delay = 0;
230 tx_data_delay = 0;
231
232 mstr_config = (tx_data_oe_delay << TX_DATA_OE_DELAY_SHIFT) |
233 (tx_data_delay << TX_DATA_DELAY_SHIFT) | (SBL_EN) |
234 (spi_mode << SPI_MODE_SHIFT) |
235 (PIN_HOLDN) |
236 (FB_CLK_EN) |
237 (DMA_ENABLE) |
238 (FULL_CYCLE_MODE);
239
240 write32(&sdm845_qspi->mstr_cfg, mstr_config);
241 write32(&sdm845_qspi->ahb_mstr_cfg, 0xA42);
242 write32(&sdm845_qspi->mstr_int_en, 0x0);
243 write32(&sdm845_qspi->mstr_int_sts, 0xFFFFFFFF);
244 write32(&sdm845_qspi->rd_fifo_cfg, 0x0);
245 write32(&sdm845_qspi->rd_fifo_rst, RESET_FIFO);
246}
247
248void quadspi_init(uint32_t hz)
249{
250 assert(dcache_line_bytes() == CACHE_LINE_SIZE);
251 clock_configure_qspi(hz * 4);
252 configure_gpios();
253 reg_init();
254}
255
256int sdm845_claim_bus(const struct spi_slave *slave)
257{
258 cs_change(CS_ASSERT);
259 return 0;
260}
261
262void sdm845_release_bus(const struct spi_slave *slave)
263{
264 cs_change(CS_DEASSERT);
265}
266
Julius Werner127a55e2019-06-06 17:09:58 -0700267static int xfer(enum qspi_mode mode, const void *dout, size_t out_bytes,
268 void *din, size_t in_bytes)
Mukesh Savaliyab02452b2018-05-11 07:41:33 -0700269{
Mukesh Savaliyab02452b2018-05-11 07:41:33 -0700270 if ((out_bytes && !dout) || (in_bytes && !din) ||
271 (in_bytes && out_bytes)) {
272 return -1;
273 }
274
275 queue_data((uint8_t *) (out_bytes ? dout : din),
276 in_bytes | out_bytes, mode, !!out_bytes);
277
278 flush_chain();
279
280 return 0;
281}
Julius Werner127a55e2019-06-06 17:09:58 -0700282
283int sdm845_xfer(const struct spi_slave *slave, const void *dout,
284 size_t out_bytes, void *din, size_t in_bytes)
285{
286 return xfer(SDR_1BIT, dout, out_bytes, din, in_bytes);
287}
288
289int sdm845_xfer_dual(const struct spi_slave *slave, const void *dout,
290 size_t out_bytes, void *din, size_t in_bytes)
291{
292 return xfer(SDR_2BIT, dout, out_bytes, din, in_bytes);
293}