blob: ff52fbd8c896355b1e7820d0f4a7f23045781c3a [file] [log] [blame]
Angel Ponsae593872020-04-04 18:50:57 +02001/* SPDX-License-Identifier: GPL-2.0-only */
Marc Jones1587dc82017-05-15 18:55:11 -06002
Furquan Shaikh76cedd22020-05-02 10:24:23 -07003#include <acpi/acpi.h>
Elyes HAOUAS20eaef02019-03-29 17:45:28 +01004#include <console/console.h>
Martin Rothbc5c3e72017-12-09 10:40:45 -07005#include <timestamp.h>
Michał Żygowskif65c1e42019-12-01 18:14:39 +01006#include <amdblocks/biosram.h>
Marshall Dawsonc2f6da02017-12-04 15:28:10 -07007#include <amdblocks/s3_resume.h>
Marshall Dawson857a3872017-12-13 20:01:59 -07008#include <amdblocks/agesawrapper.h>
9#include <amdblocks/BiosCallOuts.h>
Martin Roth50f2e4c2018-10-29 11:16:53 -060010#include <soc/pci_devs.h>
Richard Spiegeldd9b1d12018-09-20 14:50:11 -070011#include <soc/northbridge.h>
12#include <soc/cpu.h>
Marc Jones1587dc82017-05-15 18:55:11 -060013
Aaron Durbin64031672018-04-21 14:45:32 -060014void __weak SetMemParams(AMD_POST_PARAMS *PostParams) {}
15void __weak OemPostParams(AMD_POST_PARAMS *PostParams) {}
Marc Jones1587dc82017-05-15 18:55:11 -060016
Marc Jones1587dc82017-05-15 18:55:11 -060017/* ACPI table pointers returned by AmdInitLate */
Aaron Durbin8dd40062017-11-03 11:50:14 -060018static void *DmiTable;
19static void *AcpiPstate;
20static void *AcpiSrat;
21static void *AcpiSlit;
Marc Jones1587dc82017-05-15 18:55:11 -060022
Aaron Durbin8dd40062017-11-03 11:50:14 -060023static void *AcpiWheaMce;
24static void *AcpiWheaCmc;
25static void *AcpiAlib;
26static void *AcpiIvrs;
27static void *AcpiCrat;
Marc Jones1587dc82017-05-15 18:55:11 -060028
Kyösti Mälkki85b2ed52018-06-14 06:57:05 +030029static AGESA_STATUS module_dispatch(AGESA_STRUCT_NAME func,
30 AMD_CONFIG_PARAMS *StdHeader)
31{
32 MODULE_ENTRY dispatcher = agesa_get_dispatcher();
33
34 if (!dispatcher)
35 return AGESA_UNSUPPORTED;
36
37 StdHeader->Func = func;
38 return dispatcher(StdHeader);
39}
40
41static AGESA_STATUS amd_dispatch(void *Params)
42{
43 AMD_CONFIG_PARAMS *StdHeader = Params;
44 return module_dispatch(StdHeader->Func, StdHeader);
45}
46
47AGESA_STATUS amd_late_run_ap_task(AP_EXE_PARAMS *ApExeParams)
48{
49 AMD_CONFIG_PARAMS *StdHeader = (void *)ApExeParams;
50 return module_dispatch(AMD_LATE_RUN_AP_TASK, StdHeader);
51}
52
Kyösti Mälkkifa6233d2018-06-28 16:55:29 +030053static AGESA_STATUS amd_create_struct(AMD_INTERFACE_PARAMS *aip,
Kyösti Mälkki7f8a57e2018-06-28 16:58:52 +030054 AGESA_STRUCT_NAME func, void *buf, size_t len)
Marshall Dawson4c5a3b62018-01-25 11:13:35 -070055{
Kyösti Mälkki7f8a57e2018-06-28 16:58:52 +030056 AGESA_STATUS status;
Kyösti Mälkki85b2ed52018-06-14 06:57:05 +030057
Kyösti Mälkki4cdd2f82018-06-14 06:49:38 +030058 /* Should clone entire StdHeader here. */
Kyösti Mälkki7f8a57e2018-06-28 16:58:52 +030059 memset(aip, 0, sizeof(*aip));
60 aip->StdHeader.CalloutPtr = &GetBiosCallout;
Kyösti Mälkki4cdd2f82018-06-14 06:49:38 +030061
Kyösti Mälkki7f8a57e2018-06-28 16:58:52 +030062 /* If we provide the buffer, API expects it to have
63 StdHeader already filled. */
Kyösti Mälkkifa6233d2018-06-28 16:55:29 +030064 if (buf != NULL && len >= sizeof(aip->StdHeader)) {
65 memcpy(buf, &aip->StdHeader, sizeof(aip->StdHeader));
Kyösti Mälkki7f8a57e2018-06-28 16:58:52 +030066 aip->AllocationMethod = ByHost;
67 aip->NewStructPtr = buf;
68 aip->NewStructSize = len;
69 } else {
70 if (ENV_ROMSTAGE)
71 aip->AllocationMethod = PreMemHeap;
72 if (ENV_RAMSTAGE)
73 aip->AllocationMethod = PostMemDram;
74 }
75
76 aip->AgesaFunctionName = func;
77 status = module_dispatch(AMD_CREATE_STRUCT, &aip->StdHeader);
Marshall Dawson4c5a3b62018-01-25 11:13:35 -070078
Kyösti Mälkki2fc1a372018-06-14 06:57:05 +030079 if (status != AGESA_SUCCESS) {
80 printk(BIOS_ERR, "Error: AmdCreateStruct() for 0x%x returned 0x%x. "
81 "Proper system initialization may not be possible.\n",
Kyösti Mälkki7f8a57e2018-06-28 16:58:52 +030082 aip->AgesaFunctionName, status);
Kyösti Mälkki2fc1a372018-06-14 06:57:05 +030083 }
Marshall Dawson4c5a3b62018-01-25 11:13:35 -070084
Kyösti Mälkki7f8a57e2018-06-28 16:58:52 +030085 if (!aip->NewStructPtr)
Marshall Dawson4c5a3b62018-01-25 11:13:35 -070086 die("No AGESA structure created");
87
Kyösti Mälkkifa6233d2018-06-28 16:55:29 +030088 return status;
Marshall Dawson4c5a3b62018-01-25 11:13:35 -070089}
90
Kyösti Mälkki7f8a57e2018-06-28 16:58:52 +030091static AGESA_STATUS amd_release_struct(AMD_INTERFACE_PARAMS *aip)
92{
93 return module_dispatch(AMD_RELEASE_STRUCT, &aip->StdHeader);
94}
95
Kyösti Mälkkifa6233d2018-06-28 16:55:29 +030096static AGESA_STATUS amd_init_reset(AMD_RESET_PARAMS *ResetParams)
Marc Jones1587dc82017-05-15 18:55:11 -060097{
98 AGESA_STATUS status;
Kyösti Mälkki108fb8a2018-06-14 06:57:05 +030099
Kyösti Mälkki108fb8a2018-06-14 06:57:05 +0300100 SetFchResetParams(&ResetParams->FchInterface);
Marc Jones1587dc82017-05-15 18:55:11 -0600101
Martin Rothbc5c3e72017-12-09 10:40:45 -0700102 timestamp_add_now(TS_AGESA_INIT_RESET_START);
Kyösti Mälkki85b2ed52018-06-14 06:57:05 +0300103 status = amd_dispatch(ResetParams);
Martin Rothbc5c3e72017-12-09 10:40:45 -0700104 timestamp_add_now(TS_AGESA_INIT_RESET_DONE);
105
Marc Jones1587dc82017-05-15 18:55:11 -0600106 return status;
107}
108
Kyösti Mälkkifa6233d2018-06-28 16:55:29 +0300109static AGESA_STATUS amd_init_early(AMD_EARLY_PARAMS *EarlyParams)
Marc Jones1587dc82017-05-15 18:55:11 -0600110{
111 AGESA_STATUS status;
Marc Jones1587dc82017-05-15 18:55:11 -0600112
Richard Spiegeldd9b1d12018-09-20 14:50:11 -0700113 soc_customize_init_early(EarlyParams);
Marshall Dawson857a3872017-12-13 20:01:59 -0700114 OemCustomizeInitEarly(EarlyParams);
Marc Jones1587dc82017-05-15 18:55:11 -0600115
Martin Rothbc5c3e72017-12-09 10:40:45 -0700116 timestamp_add_now(TS_AGESA_INIT_EARLY_START);
Kyösti Mälkki85b2ed52018-06-14 06:57:05 +0300117 status = amd_dispatch(EarlyParams);
Martin Rothbc5c3e72017-12-09 10:40:45 -0700118 timestamp_add_now(TS_AGESA_INIT_EARLY_DONE);
Marc Jones1587dc82017-05-15 18:55:11 -0600119
Marc Jones1587dc82017-05-15 18:55:11 -0600120 return status;
121}
122
Marshall Dawson972f8262017-12-14 09:08:02 -0700123static void print_init_post_settings(AMD_POST_PARAMS *parms)
124{
125 u64 syslimit, bottomio, uma_size, uma_start;
126 const char *mode;
127
128 switch (parms->MemConfig.UmaMode) {
129 case UMA_AUTO:
130 mode = "UMA_AUTO";
131 break;
132 case UMA_SPECIFIED:
133 mode = "UMA_SPECIFIED";
134 break;
135 case UMA_NONE:
136 mode = "UMA_NONE";
137 break;
138 default:
139 mode = "unknown!";
140 break;
141 }
142
Marshall Dawson74258d72018-10-22 15:22:46 -0600143 syslimit = (u64)(parms->MemConfig.SysLimit + 1) * 64 * KiB - 1;
Marshall Dawson972f8262017-12-14 09:08:02 -0700144 bottomio = (u64)parms->MemConfig.BottomIo * 64 * KiB;
145
146 uma_size = (u64)parms->MemConfig.UmaSize * 64 * KiB;
147 uma_start = (u64)parms->MemConfig.UmaBase * 64 * KiB;
148
149 printk(BIOS_SPEW, "AGESA set: umamode %s\n", mode);
150 printk(BIOS_SPEW, " : syslimit 0x%llx, bottomio 0x%08llx\n",
151 syslimit, bottomio);
152 printk(BIOS_SPEW, " : uma size %lluMB, uma start 0x%08llx\n",
153 uma_size / MiB, uma_start);
154}
155
Kyösti Mälkkifa6233d2018-06-28 16:55:29 +0300156static AGESA_STATUS amd_init_post(AMD_POST_PARAMS *PostParams)
Marc Jones1587dc82017-05-15 18:55:11 -0600157{
158 AGESA_STATUS status;
Marc Jones1587dc82017-05-15 18:55:11 -0600159
Julius Werner5d1f9a02019-03-07 17:07:26 -0800160 PostParams->MemConfig.UmaMode = CONFIG(GFXUMA) ? UMA_AUTO : UMA_NONE;
Marc Jones1587dc82017-05-15 18:55:11 -0600161 PostParams->MemConfig.UmaSize = 0;
Richard Spiegel271b8a52018-11-06 16:32:28 -0700162 PostParams->MemConfig.BottomIo = (uint16_t)
Marc Jones1587dc82017-05-15 18:55:11 -0600163 (CONFIG_BOTTOMIO_POSITION >> 24);
164
Richard Spiegel67c2a7b2017-11-09 16:04:35 -0700165 SetMemParams(PostParams);
Marc Jones1587dc82017-05-15 18:55:11 -0600166 OemPostParams(PostParams);
Richard Spiegel67c2a7b2017-11-09 16:04:35 -0700167 printk(BIOS_SPEW, "DRAM clear on reset: %s\n",
168 (PostParams->MemConfig.EnableMemClr == FALSE) ? "Keep" :
169 (PostParams->MemConfig.EnableMemClr == TRUE) ? "Clear" :
170 "unknown"
171 );
Marc Jones1587dc82017-05-15 18:55:11 -0600172
Martin Rothbc5c3e72017-12-09 10:40:45 -0700173 timestamp_add_now(TS_AGESA_INIT_POST_START);
Kyösti Mälkki85b2ed52018-06-14 06:57:05 +0300174 status = amd_dispatch(PostParams);
Martin Rothbc5c3e72017-12-09 10:40:45 -0700175 timestamp_add_now(TS_AGESA_INIT_POST_DONE);
Marc Jones1587dc82017-05-15 18:55:11 -0600176
Marshall Dawson972f8262017-12-14 09:08:02 -0700177 /*
Marc Jones932b5bd2018-02-19 13:34:31 -0700178 * AGESA passes back the base and size of UMA. This is the only
179 * opportunity to get and save these settings to be used in resource
180 * allocation. We also need to allocate the top of low memory.
181 * If UMA is below 4GiB, UMA base is the top of low memory, otherwise
182 * Sub4GCachetop is the top of low memory.
183 * With UMA_NONE we see UmaBase==0.
Marshall Dawson972f8262017-12-14 09:08:02 -0700184 */
185 uintptr_t top;
Marc Jones932b5bd2018-02-19 13:34:31 -0700186 if (PostParams->MemConfig.UmaBase &&
187 (PostParams->MemConfig.UmaBase < ((4ull * GiB) >> 16)))
Marshall Dawson972f8262017-12-14 09:08:02 -0700188 top = PostParams->MemConfig.UmaBase << 16;
Marc Jones1587dc82017-05-15 18:55:11 -0600189 else
Marshall Dawson972f8262017-12-14 09:08:02 -0700190 top = PostParams->MemConfig.Sub4GCacheTop;
191 backup_top_of_low_cacheable(top);
Marc Jones1587dc82017-05-15 18:55:11 -0600192
Marc Jones932b5bd2018-02-19 13:34:31 -0700193 save_uma_size(PostParams->MemConfig.UmaSize * 64 * KiB);
194 save_uma_base((u64)PostParams->MemConfig.UmaBase * 64 * KiB);
195
Marshall Dawson972f8262017-12-14 09:08:02 -0700196 print_init_post_settings(PostParams);
Marc Jones1587dc82017-05-15 18:55:11 -0600197
Marc Jones1587dc82017-05-15 18:55:11 -0600198 return status;
199}
200
Kyösti Mälkkifa6233d2018-06-28 16:55:29 +0300201static AGESA_STATUS amd_init_env(AMD_ENV_PARAMS *EnvParams)
Marc Jones1587dc82017-05-15 18:55:11 -0600202{
203 AGESA_STATUS status;
Marc Jones1587dc82017-05-15 18:55:11 -0600204
Marshall Dawson857a3872017-12-13 20:01:59 -0700205 SetFchEnvParams(&EnvParams->FchInterface);
206 SetNbEnvParams(&EnvParams->GnbEnvConfiguration);
Marc Jones1587dc82017-05-15 18:55:11 -0600207
Martin Rothbc5c3e72017-12-09 10:40:45 -0700208 timestamp_add_now(TS_AGESA_INIT_ENV_START);
Kyösti Mälkki85b2ed52018-06-14 06:57:05 +0300209 status = amd_dispatch(EnvParams);
Martin Rothbc5c3e72017-12-09 10:40:45 -0700210 timestamp_add_now(TS_AGESA_INIT_ENV_DONE);
211
Marc Jones1587dc82017-05-15 18:55:11 -0600212 return status;
213}
214
Richard Spiegel271b8a52018-11-06 16:32:28 -0700215void *agesawrapper_getlateinitptr(int pick)
Marc Jones1587dc82017-05-15 18:55:11 -0600216{
217 switch (pick) {
218 case PICK_DMI:
219 return DmiTable;
220 case PICK_PSTATE:
221 return AcpiPstate;
222 case PICK_SRAT:
223 return AcpiSrat;
224 case PICK_SLIT:
225 return AcpiSlit;
226 case PICK_WHEA_MCE:
227 return AcpiWheaMce;
228 case PICK_WHEA_CMC:
229 return AcpiWheaCmc;
230 case PICK_ALIB:
231 return AcpiAlib;
232 case PICK_IVRS:
233 return AcpiIvrs;
234 case PICK_CRAT:
235 return AcpiCrat;
236 default:
237 return NULL;
238 }
239}
Marc Jones1587dc82017-05-15 18:55:11 -0600240
Kyösti Mälkkifa6233d2018-06-28 16:55:29 +0300241static AGESA_STATUS amd_init_mid(AMD_MID_PARAMS *MidParams)
Marc Jones1587dc82017-05-15 18:55:11 -0600242{
243 AGESA_STATUS status;
Marc Jones1587dc82017-05-15 18:55:11 -0600244
245 /* Enable MMIO on AMD CPU Address Map Controller */
Marshall Dawson857a3872017-12-13 20:01:59 -0700246 amd_initcpuio();
Marc Jones1587dc82017-05-15 18:55:11 -0600247
Marshall Dawson857a3872017-12-13 20:01:59 -0700248 SetFchMidParams(&MidParams->FchInterface);
249 SetNbMidParams(&MidParams->GnbMidConfiguration);
Marc Jones1587dc82017-05-15 18:55:11 -0600250
Martin Rothbc5c3e72017-12-09 10:40:45 -0700251 timestamp_add_now(TS_AGESA_INIT_MID_START);
Kyösti Mälkki85b2ed52018-06-14 06:57:05 +0300252 status = amd_dispatch(MidParams);
Martin Rothbc5c3e72017-12-09 10:40:45 -0700253 timestamp_add_now(TS_AGESA_INIT_MID_DONE);
254
Marc Jones1587dc82017-05-15 18:55:11 -0600255 return status;
256}
257
Kyösti Mälkkifa6233d2018-06-28 16:55:29 +0300258static AGESA_STATUS amd_init_late(AMD_LATE_PARAMS *LateParams)
Marc Jones1587dc82017-05-15 18:55:11 -0600259{
260 AGESA_STATUS Status;
Martin Rothbc5c3e72017-12-09 10:40:45 -0700261
Kyösti Mälkkie7377552018-06-21 16:20:55 +0300262 const struct device *dev = pcidev_path_on_root(IOMMU_DEVFN);
Martin Roth50f2e4c2018-10-29 11:16:53 -0600263 if (dev && dev->enabled) {
Richard Spiegel271b8a52018-11-06 16:32:28 -0700264 LateParams->GnbLateConfiguration.GnbIoapicId = CONFIG_MAX_CPUS
265 + 1;
Martin Roth50f2e4c2018-10-29 11:16:53 -0600266 LateParams->GnbLateConfiguration.FchIoapicId = CONFIG_MAX_CPUS;
267 }
Marc Jonesbc94aea2018-09-26 09:57:08 -0600268
Martin Rothbc5c3e72017-12-09 10:40:45 -0700269 timestamp_add_now(TS_AGESA_INIT_LATE_START);
Kyösti Mälkki85b2ed52018-06-14 06:57:05 +0300270 Status = amd_dispatch(LateParams);
Martin Rothbc5c3e72017-12-09 10:40:45 -0700271 timestamp_add_now(TS_AGESA_INIT_LATE_DONE);
272
Marshall Dawson857a3872017-12-13 20:01:59 -0700273 DmiTable = LateParams->DmiTable;
274 AcpiPstate = LateParams->AcpiPState;
Marc Jones1587dc82017-05-15 18:55:11 -0600275
Marshall Dawson857a3872017-12-13 20:01:59 -0700276 AcpiWheaMce = LateParams->AcpiWheaMce;
277 AcpiWheaCmc = LateParams->AcpiWheaCmc;
278 AcpiAlib = LateParams->AcpiAlib;
279 AcpiIvrs = LateParams->AcpiIvrs;
280 AcpiCrat = LateParams->AcpiCrat;
Marc Jones1587dc82017-05-15 18:55:11 -0600281
Marshall Dawson857a3872017-12-13 20:01:59 -0700282 printk(BIOS_DEBUG, "DmiTable:%p, AcpiPstatein: %p, AcpiSrat:%p,"
283 "AcpiSlit:%p, Mce:%p, Cmc:%p,"
284 "Alib:%p, AcpiIvrs:%p in %s\n",
285 DmiTable, AcpiPstate, AcpiSrat,
286 AcpiSlit, AcpiWheaMce, AcpiWheaCmc,
287 AcpiAlib, AcpiIvrs, __func__);
Marc Jones1587dc82017-05-15 18:55:11 -0600288
Marc Jones1587dc82017-05-15 18:55:11 -0600289 return Status;
290}
Marc Jones1587dc82017-05-15 18:55:11 -0600291
Kyösti Mälkkifa6233d2018-06-28 16:55:29 +0300292static AGESA_STATUS amd_init_rtb(AMD_RTB_PARAMS *RtbParams)
Marshall Dawsonc2f6da02017-12-04 15:28:10 -0700293{
294 AGESA_STATUS Status;
Marshall Dawsonc2f6da02017-12-04 15:28:10 -0700295
296 timestamp_add_now(TS_AGESA_INIT_RTB_START);
Kyösti Mälkki85b2ed52018-06-14 06:57:05 +0300297 Status = amd_dispatch(RtbParams);
Marshall Dawsonc2f6da02017-12-04 15:28:10 -0700298 timestamp_add_now(TS_AGESA_INIT_RTB_DONE);
299
Kyösti Mälkki66cabe72018-07-01 03:48:39 +0300300 if (Status != AGESA_SUCCESS)
301 return Status;
302
303 if (OemS3Save(&RtbParams->S3DataBlock) != AGESA_SUCCESS)
Marshall Dawsonc2f6da02017-12-04 15:28:10 -0700304 printk(BIOS_ERR, "S3 data not saved, resuming impossible\n");
305
Marshall Dawsonc2f6da02017-12-04 15:28:10 -0700306 return Status;
307}
308
Kyösti Mälkkifa6233d2018-06-28 16:55:29 +0300309static AGESA_STATUS amd_init_resume(AMD_RESUME_PARAMS *InitResumeParams)
Marshall Dawsonc2f6da02017-12-04 15:28:10 -0700310{
311 AGESA_STATUS status;
Marshall Dawsonc2f6da02017-12-04 15:28:10 -0700312
Kyösti Mälkki66cabe72018-07-01 03:48:39 +0300313 OemInitResume(&InitResumeParams->S3DataBlock);
Marshall Dawsonc2f6da02017-12-04 15:28:10 -0700314
315 timestamp_add_now(TS_AGESA_INIT_RESUME_START);
Kyösti Mälkki85b2ed52018-06-14 06:57:05 +0300316 status = amd_dispatch(InitResumeParams);
Marshall Dawsonc2f6da02017-12-04 15:28:10 -0700317 timestamp_add_now(TS_AGESA_INIT_RESUME_DONE);
318
Marshall Dawsonc2f6da02017-12-04 15:28:10 -0700319 return status;
320}
321
Kyösti Mälkkifa6233d2018-06-28 16:55:29 +0300322static AGESA_STATUS amd_s3late_restore(AMD_S3LATE_PARAMS *S3LateParams)
Marshall Dawsonc2f6da02017-12-04 15:28:10 -0700323{
324 AGESA_STATUS Status;
Marshall Dawsonc2f6da02017-12-04 15:28:10 -0700325
Marshall Dawsonc2f6da02017-12-04 15:28:10 -0700326 amd_initcpuio();
327
Kyösti Mälkki66cabe72018-07-01 03:48:39 +0300328 OemS3LateRestore(&S3LateParams->S3DataBlock);
Marshall Dawsonc2f6da02017-12-04 15:28:10 -0700329
330 timestamp_add_now(TS_AGESA_S3_LATE_START);
Kyösti Mälkki85b2ed52018-06-14 06:57:05 +0300331 Status = amd_dispatch(S3LateParams);
Marshall Dawsonc2f6da02017-12-04 15:28:10 -0700332 timestamp_add_now(TS_AGESA_S3_LATE_DONE);
333
Marshall Dawsonc2f6da02017-12-04 15:28:10 -0700334 return Status;
335}
336
Kyösti Mälkkifa6233d2018-06-28 16:55:29 +0300337static AGESA_STATUS amd_s3final_restore(AMD_S3FINAL_PARAMS *S3FinalParams)
Marshall Dawsonc2f6da02017-12-04 15:28:10 -0700338{
339 AGESA_STATUS Status;
Marshall Dawsonc2f6da02017-12-04 15:28:10 -0700340
Kyösti Mälkki66cabe72018-07-01 03:48:39 +0300341 OemS3LateRestore(&S3FinalParams->S3DataBlock);
Marshall Dawsonc2f6da02017-12-04 15:28:10 -0700342
343 timestamp_add_now(TS_AGESA_S3_FINAL_START);
Kyösti Mälkki85b2ed52018-06-14 06:57:05 +0300344 Status = amd_dispatch(S3FinalParams);
Marshall Dawsonc2f6da02017-12-04 15:28:10 -0700345 timestamp_add_now(TS_AGESA_S3_FINAL_DONE);
346
Marshall Dawsonc2f6da02017-12-04 15:28:10 -0700347 return Status;
348}
Kyösti Mälkki6e512c42018-06-14 06:57:05 +0300349
350static AGESA_STATUS romstage_dispatch(AMD_CONFIG_PARAMS *StdHeader)
351{
Kyösti Mälkkifa6233d2018-06-28 16:55:29 +0300352 void *Params = StdHeader;
353
Kyösti Mälkki6e512c42018-06-14 06:57:05 +0300354 switch (StdHeader->Func) {
355 case AMD_INIT_RESET:
Kyösti Mälkkifa6233d2018-06-28 16:55:29 +0300356 return amd_init_reset(Params);
Kyösti Mälkki6e512c42018-06-14 06:57:05 +0300357 case AMD_INIT_EARLY:
Kyösti Mälkkifa6233d2018-06-28 16:55:29 +0300358 return amd_init_early(Params);
Kyösti Mälkki6e512c42018-06-14 06:57:05 +0300359 case AMD_INIT_POST:
Kyösti Mälkkifa6233d2018-06-28 16:55:29 +0300360 return amd_init_post(Params);
Kyösti Mälkki6e512c42018-06-14 06:57:05 +0300361 case AMD_INIT_RESUME:
Kyösti Mälkkifa6233d2018-06-28 16:55:29 +0300362 return amd_init_resume(Params);
Kyösti Mälkki6e512c42018-06-14 06:57:05 +0300363 default:
364 return AGESA_UNSUPPORTED;
365 }
366}
367
368static AGESA_STATUS ramstage_dispatch(AMD_CONFIG_PARAMS *StdHeader)
369{
Kyösti Mälkkifa6233d2018-06-28 16:55:29 +0300370 void *Params = StdHeader;
371
Kyösti Mälkki6e512c42018-06-14 06:57:05 +0300372 switch (StdHeader->Func) {
373 case AMD_INIT_ENV:
Kyösti Mälkkifa6233d2018-06-28 16:55:29 +0300374 return amd_init_env(Params);
Kyösti Mälkki6e512c42018-06-14 06:57:05 +0300375 case AMD_INIT_MID:
Kyösti Mälkkifa6233d2018-06-28 16:55:29 +0300376 return amd_init_mid(Params);
Kyösti Mälkki6e512c42018-06-14 06:57:05 +0300377 case AMD_INIT_LATE:
Kyösti Mälkkifa6233d2018-06-28 16:55:29 +0300378 return amd_init_late(Params);
Kyösti Mälkki6e512c42018-06-14 06:57:05 +0300379 case AMD_INIT_RTB:
Kyösti Mälkkifa6233d2018-06-28 16:55:29 +0300380 return amd_init_rtb(Params);
Kyösti Mälkki6e512c42018-06-14 06:57:05 +0300381 case AMD_S3LATE_RESTORE:
Kyösti Mälkkifa6233d2018-06-28 16:55:29 +0300382 return amd_s3late_restore(Params);
Kyösti Mälkki6e512c42018-06-14 06:57:05 +0300383 case AMD_S3FINAL_RESTORE:
Kyösti Mälkkifa6233d2018-06-28 16:55:29 +0300384 return amd_s3final_restore(Params);
Kyösti Mälkki6e512c42018-06-14 06:57:05 +0300385 default:
386 return AGESA_UNSUPPORTED;
387 }
Kyösti Mälkkifa6233d2018-06-28 16:55:29 +0300388
Kyösti Mälkki6e512c42018-06-14 06:57:05 +0300389}
390
391AGESA_STATUS agesa_execute_state(AGESA_STRUCT_NAME func)
392{
393 AGESA_STATUS status = AGESA_UNSUPPORTED;
394 AMD_CONFIG_PARAMS template = {};
395 AMD_CONFIG_PARAMS *StdHeader = &template;
Kyösti Mälkkifa6233d2018-06-28 16:55:29 +0300396 AMD_INTERFACE_PARAMS AmdParamStruct;
397 AMD_INTERFACE_PARAMS *aip = &AmdParamStruct;
398 union {
399 AMD_RESET_PARAMS ResetParams;
400 AMD_S3LATE_PARAMS S3LateParams;
401 AMD_S3FINAL_PARAMS S3FinalParams;
402 } sp;
Kyösti Mälkki6e512c42018-06-14 06:57:05 +0300403
Kyösti Mälkkifa6233d2018-06-28 16:55:29 +0300404 if ((func == AMD_INIT_RESET) || (func == AMD_S3LATE_RESTORE) ||
405 (func == AMD_S3FINAL_RESTORE)) {
406 memset(&sp, 0, sizeof(sp));
407 amd_create_struct(aip, func, &sp, sizeof(sp));
408 } else {
409 amd_create_struct(aip, func, NULL, 0);
410 }
411
412 StdHeader = aip->NewStructPtr;
Kyösti Mälkki6e512c42018-06-14 06:57:05 +0300413 StdHeader->Func = func;
414
415 if (ENV_ROMSTAGE)
416 status = romstage_dispatch(StdHeader);
417 if (ENV_RAMSTAGE)
418 status = ramstage_dispatch(StdHeader);
419
Kyösti Mälkkifa6233d2018-06-28 16:55:29 +0300420 amd_release_struct(aip);
Kyösti Mälkki6e512c42018-06-14 06:57:05 +0300421 return status;
422}