blob: 74b9de342806d7c9cd8a27a5979a088bec073961 [file] [log] [blame]
Patrick Georgiac959032020-05-05 22:49:26 +02001/* SPDX-License-Identifier: GPL-2.0-or-later */
Lee Leahy48dbc662017-05-08 16:56:03 -07002#ifndef __COMMONLIB_STORAGE_SDHCI_H__
3#define __COMMONLIB_STORAGE_SDHCI_H__
Lee Leahyeef40eb2017-03-23 10:54:57 -07004
Kyösti Mälkki13f66502019-03-03 08:01:05 +02005#include <device/mmio.h>
Lee Leahy48dbc662017-05-08 16:56:03 -07006#include <commonlib/sd_mmc_ctrlr.h>
Lee Leahyeef40eb2017-03-23 10:54:57 -07007
8/*
9 * Controller registers
10 */
11
12#define SDHCI_DMA_ADDRESS 0x00
13
14#define SDHCI_BLOCK_SIZE 0x04
15#define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF))
16
17#define SDHCI_BLOCK_COUNT 0x06
18
19#define SDHCI_ARGUMENT 0x08
20
21#define SDHCI_TRANSFER_MODE 0x0C
22#define SDHCI_TRNS_DMA 0x01
23#define SDHCI_TRNS_BLK_CNT_EN 0x02
24#define SDHCI_TRNS_ACMD12 0x04
25#define SDHCI_TRNS_READ 0x10
26#define SDHCI_TRNS_MULTI 0x20
27
28#define SDHCI_COMMAND 0x0E
29#define SDHCI_CMD_RESP_MASK 0x03
30#define SDHCI_CMD_CRC 0x08
31#define SDHCI_CMD_INDEX 0x10
32#define SDHCI_CMD_DATA 0x20
33#define SDHCI_CMD_ABORTCMD 0xC0
34
35#define SDHCI_CMD_RESP_NONE 0x00
36#define SDHCI_CMD_RESP_LONG 0x01
37#define SDHCI_CMD_RESP_SHORT 0x02
38#define SDHCI_CMD_RESP_SHORT_BUSY 0x03
39
40#define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff))
41#define SDHCI_GET_CMD(c) ((c>>8) & 0x3f)
42
43#define SDHCI_RESPONSE 0x10
44
45#define SDHCI_BUFFER 0x20
46
47#define SDHCI_PRESENT_STATE 0x24
48#define SDHCI_CMD_INHIBIT 0x00000001
49#define SDHCI_DATA_INHIBIT 0x00000002
50#define SDHCI_DOING_WRITE 0x00000100
51#define SDHCI_DOING_READ 0x00000200
52#define SDHCI_SPACE_AVAILABLE 0x00000400
53#define SDHCI_DATA_AVAILABLE 0x00000800
54#define SDHCI_CARD_PRESENT 0x00010000
55#define SDHCI_CARD_STATE_STABLE 0x00020000
56#define SDHCI_CARD_DETECT_PIN_LEVEL 0x00040000
57#define SDHCI_WRITE_PROTECT 0x00080000
58
59#define SDHCI_HOST_CONTROL 0x28
60#define SDHCI_CTRL_LED 0x01
61#define SDHCI_CTRL_4BITBUS 0x02
62#define SDHCI_CTRL_HISPD 0x04
63#define SDHCI_CTRL_DMA_MASK 0x18
64#define SDHCI_CTRL_SDMA 0x00
65#define SDHCI_CTRL_ADMA1 0x08
66#define SDHCI_CTRL_ADMA32 0x10
67#define SDHCI_CTRL_ADMA64 0x18
68#define SDHCI_CTRL_8BITBUS 0x20
69#define SDHCI_CTRL_CD_TEST_INS 0x40
70#define SDHCI_CTRL_CD_TEST 0x80
71
72#define SDHCI_POWER_CONTROL 0x29
73#define SDHCI_POWER_ON 0x01
74#define SDHCI_POWER_180 0x0A
75#define SDHCI_POWER_300 0x0C
76#define SDHCI_POWER_330 0x0E
77
78#define SDHCI_BLOCK_GAP_CONTROL 0x2A
79
80#define SDHCI_WAKE_UP_CONTROL 0x2B
81#define SDHCI_WAKE_ON_INT 0x01
82#define SDHCI_WAKE_ON_INSERT 0x02
83#define SDHCI_WAKE_ON_REMOVE 0x04
84
85#define SDHCI_CLOCK_CONTROL 0x2C
86#define SDHCI_DIVIDER_SHIFT 8
87#define SDHCI_DIVIDER_HI_SHIFT 6
88#define SDHCI_DIV_MASK 0xFF
89#define SDHCI_DIV_MASK_LEN 8
90#define SDHCI_DIV_HI_MASK 0x300
91#define SDHCI_CLOCK_CARD_EN 0x0004
92#define SDHCI_CLOCK_INT_STABLE 0x0002
93#define SDHCI_CLOCK_INT_EN 0x0001
94
95#define SDHCI_TIMEOUT_CONTROL 0x2E
96
97#define SDHCI_SOFTWARE_RESET 0x2F
98#define SDHCI_RESET_ALL 0x01
99#define SDHCI_RESET_CMD 0x02
100#define SDHCI_RESET_DATA 0x04
101
102#define SDHCI_INT_STATUS 0x30
103#define SDHCI_INT_ENABLE 0x34
104#define SDHCI_SIGNAL_ENABLE 0x38
105#define SDHCI_INT_RESPONSE 0x00000001
106#define SDHCI_INT_DATA_END 0x00000002
107#define SDHCI_INT_DMA_END 0x00000008
108#define SDHCI_INT_SPACE_AVAIL 0x00000010
109#define SDHCI_INT_DATA_AVAIL 0x00000020
110#define SDHCI_INT_CARD_INSERT 0x00000040
111#define SDHCI_INT_CARD_REMOVE 0x00000080
112#define SDHCI_INT_CARD_INT 0x00000100
113#define SDHCI_INT_ERROR 0x00008000
114#define SDHCI_INT_TIMEOUT 0x00010000
115#define SDHCI_INT_CRC 0x00020000
116#define SDHCI_INT_END_BIT 0x00040000
117#define SDHCI_INT_INDEX 0x00080000
118#define SDHCI_INT_DATA_TIMEOUT 0x00100000
119#define SDHCI_INT_DATA_CRC 0x00200000
120#define SDHCI_INT_DATA_END_BIT 0x00400000
121#define SDHCI_INT_BUS_POWER 0x00800000
122#define SDHCI_INT_ACMD12ERR 0x01000000
123#define SDHCI_INT_ADMA_ERROR 0x02000000
124
125#define SDHCI_INT_NORMAL_MASK 0x00007FFF
126#define SDHCI_INT_ERROR_MASK 0xFFFF8000
127
128#define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT \
129 | SDHCI_INT_CRC | SDHCI_INT_END_BIT \
130 | SDHCI_INT_INDEX)
131#define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END \
132 | SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL \
133 | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC \
134 | SDHCI_INT_DATA_END_BIT | SDHCI_INT_ADMA_ERROR)
135#define SDHCI_INT_ALL_MASK ((unsigned int)-1)
136
137#define SDHCI_ACMD12_ERR 0x3C
138
139#define SDHCI_HOST_CONTROL2 0x3E
140#define SDHCI_CTRL_UHS_MASK 0x0007
141#define SDHCI_CTRL_UHS_SDR12 0x0000
142#define SDHCI_CTRL_UHS_SDR25 0x0001
143#define SDHCI_CTRL_UHS_SDR50 0x0002
144#define SDHCI_CTRL_UHS_SDR104 0x0003
145#define SDHCI_CTRL_UHS_DDR50 0x0004
146#define SDHCI_CTRL_HS400 0x0005 /* reserved value in SDIO spec */
147#define SDHCI_CTRL_VDD_180 0x0008
148#define SDHCI_CTRL_DRV_TYPE_MASK 0x0030
149#define SDHCI_CTRL_DRV_TYPE_B 0x0000
150#define SDHCI_CTRL_DRV_TYPE_A 0x0010
151#define SDHCI_CTRL_DRV_TYPE_C 0x0020
152#define SDHCI_CTRL_DRV_TYPE_D 0x0030
153#define SDHCI_CTRL_EXEC_TUNING 0x0040
154#define SDHCI_CTRL_TUNED_CLK 0x0080
155#define SDHCI_CTRL_PRESET_VAL_ENABLE 0x8000
156
157#define SDHCI_CAPABILITIES 0x40
158#define SDHCI_TIMEOUT_CLK_MASK 0x0000003F
159#define SDHCI_TIMEOUT_CLK_SHIFT 0
160#define SDHCI_TIMEOUT_CLK_UNIT 0x00000080
161#define SDHCI_CLOCK_BASE_MASK 0x00003F00
162#define SDHCI_CLOCK_V3_BASE_MASK 0x0000FF00
163#define SDHCI_CLOCK_BASE_SHIFT 8
164#define SDHCI_MAX_BLOCK_MASK 0x00030000
165#define SDHCI_MAX_BLOCK_SHIFT 16
166#define SDHCI_CAN_DO_8BIT 0x00040000
167#define SDHCI_CAN_DO_ADMA2 0x00080000
168#define SDHCI_CAN_DO_ADMA1 0x00100000
169#define SDHCI_CAN_DO_HISPD 0x00200000
170#define SDHCI_CAN_DO_SDMA 0x00400000
171#define SDHCI_CAN_VDD_330 0x01000000
172#define SDHCI_CAN_VDD_300 0x02000000
173#define SDHCI_CAN_VDD_180 0x04000000
174#define SDHCI_CAN_64BIT 0x10000000
175
176#define SDHCI_CAPABILITIES_1 0x44
177#define SDHCI_SUPPORT_HS400 0x80000000
178
179#define SDHCI_MAX_CURRENT 0x48
180
181/* 4C-4F reserved for more max current */
182
183#define SDHCI_SET_ACMD12_ERROR 0x50
184#define SDHCI_SET_INT_ERROR 0x52
185
186#define SDHCI_ADMA_ERROR 0x54
187
188/* 55-57 reserved */
189
190#define SDHCI_ADMA_ADDRESS 0x58
191
192/* 60-FB reserved */
193
194#define SDHCI_SLOT_INT_STATUS 0xFC
195
196#define SDHCI_HOST_VERSION 0xFE
197#define SDHCI_VENDOR_VER_MASK 0xFF00
198#define SDHCI_VENDOR_VER_SHIFT 8
199#define SDHCI_SPEC_VER_MASK 0x00FF
200#define SDHCI_SPEC_VER_SHIFT 0
201#define SDHCI_SPEC_100 0
202#define SDHCI_SPEC_200 1
203#define SDHCI_SPEC_300 2
204
205/*
206 * End of controller registers.
207 */
208
209#define SDHCI_MAX_DIV_SPEC_200 256
210#define SDHCI_MAX_DIV_SPEC_300 2046
211
212/*
213 * Controller SDMA buffer boundary. Valid values from 4K to 512K in powers of 2.
214 */
215#define SDHCI_DEFAULT_BOUNDARY_SIZE (512 * 1024)
216#define SDHCI_DEFAULT_BOUNDARY_ARG (7)
217
218#define SDHCI_MAX_PER_DESCRIPTOR 0x10000
219
220/* ADMA descriptor attributes */
221#define SDHCI_ADMA_VALID (1 << 0)
222#define SDHCI_ADMA_END (1 << 1)
223#define SDHCI_ADMA_INT (1 << 2)
224#define SDHCI_ACT_NOP (0 << 4)
225#define SDHCI_ACT_TRAN (2 << 4)
226#define SDHCI_ACT_LINK (3 << 4)
227
228static inline void sdhci_writel(struct sdhci_ctrlr *sdhci_ctrlr, u32 val,
229 int reg)
230{
231 write32(sdhci_ctrlr->ioaddr + reg, val);
232}
233
234static inline void sdhci_writew(struct sdhci_ctrlr *sdhci_ctrlr, u16 val,
235 int reg)
236{
237 write16(sdhci_ctrlr->ioaddr + reg, val);
238}
239
240static inline void sdhci_writeb(struct sdhci_ctrlr *sdhci_ctrlr, u8 val,
241 int reg)
242{
243 write8(sdhci_ctrlr->ioaddr + reg, val);
244}
245static inline u32 sdhci_readl(struct sdhci_ctrlr *sdhci_ctrlr, int reg)
246{
247 return read32(sdhci_ctrlr->ioaddr + reg);
248}
249
250static inline u16 sdhci_readw(struct sdhci_ctrlr *sdhci_ctrlr, int reg)
251{
252 return read16(sdhci_ctrlr->ioaddr + reg);
253}
254
255static inline u8 sdhci_readb(struct sdhci_ctrlr *sdhci_ctrlr, int reg)
256{
257 return read8(sdhci_ctrlr->ioaddr + reg);
258}
259
260void sdhci_reset(struct sdhci_ctrlr *sdhci_ctrlr, u8 mask);
261void sdhci_cmd_done(struct sdhci_ctrlr *sdhci_ctrlr, struct mmc_command *cmd);
262int sdhci_setup_adma(struct sdhci_ctrlr *sdhci_ctrlr, struct mmc_data *data);
263int sdhci_complete_adma(struct sdhci_ctrlr *sdhci_ctrlr,
264 struct mmc_command *cmd);
265
Lee Leahy48dbc662017-05-08 16:56:03 -0700266#endif /* __COMMONLIB_STORAGE_SDHCI_H__ */