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Lee Leahy77ff0b12015-05-05 15:07:29 -07001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2013 Google Inc.
Lee Leahy32471722015-04-20 15:20:28 -07005 * Copyright (C) 2015 Intel Corp.
Frans Hendriksed7780d2018-12-14 07:49:18 +01006 * Copyright (C) 2018 Eltan B.V.
Lee Leahy77ff0b12015-05-05 15:07:29 -07007 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
Lee Leahy77ff0b12015-05-05 15:07:29 -070016 */
17
Lee Leahy32471722015-04-20 15:20:28 -070018#include <arch/acpi.h>
19#include <cbmem.h>
Lee Leahy77ff0b12015-05-05 15:07:29 -070020#include <cpu/x86/smm.h>
21#include <device/device.h>
22#include <device/pci.h>
23#include <device/pci_ids.h>
Frans Hendriksd97eb642018-11-26 11:01:56 +010024#include <cpu/x86/lapic.h>
Kyösti Mälkkib2a5f0b2019-08-04 19:54:32 +030025#include <cpu/x86/smm.h>
Aaron Durbin789f2b62015-09-09 17:05:06 -050026#include <fsp/util.h>
Lee Leahy77ff0b12015-05-05 15:07:29 -070027#include <soc/iomap.h>
28#include <soc/iosf.h>
29#include <soc/pci_devs.h>
30#include <soc/ramstage.h>
Lee Leahy32471722015-04-20 15:20:28 -070031#include <vendorcode/google/chromeos/chromeos.h>
Harry Pan43dcbfd2016-08-11 14:35:04 +080032#include <stddef.h>
Lee Leahy77ff0b12015-05-05 15:07:29 -070033
Lee Leahy32471722015-04-20 15:20:28 -070034/*
35 * Host Memory Map:
Lee Leahy77ff0b12015-05-05 15:07:29 -070036 *
37 * +--------------------------+ BMBOUND_HI
38 * | Usable DRAM |
39 * +--------------------------+ 4GiB
40 * | PCI Address Space |
41 * +--------------------------+ BMBOUND
42 * | TPM |
43 * +--------------------------+ IMR2
44 * | TXE |
45 * +--------------------------+ IMR1
46 * | iGD |
47 * +--------------------------+
48 * | GTT |
49 * +--------------------------+ SMMRRH, IRM0
50 * | TSEG |
51 * +--------------------------+ SMMRRL
52 * | Usable DRAM |
53 * +--------------------------+ 0
54 *
55 * Note that there are really only a few regions that need to enumerated w.r.t.
Frans Hendriksb81dcc62018-12-10 10:30:37 +010056 * coreboot's resource model:
Lee Leahy77ff0b12015-05-05 15:07:29 -070057 *
58 * +--------------------------+ BMBOUND_HI
59 * | Cacheable/Usable |
60 * +--------------------------+ 4GiB
61 *
62 * +--------------------------+ BMBOUND
63 * | Uncacheable/Reserved |
64 * +--------------------------+ SMMRRH
65 * | Cacheable/Reserved |
66 * +--------------------------+ SMMRRL
67 * | Cacheable/Usable |
68 * +--------------------------+ 0
69 */
Lee Leahy32471722015-04-20 15:20:28 -070070#define RES_IN_KIB(r) ((r) >> 10)
Lee Leahy77ff0b12015-05-05 15:07:29 -070071
72uint32_t nc_read_top_of_low_memory(void)
73{
Kyösti Mälkki117cf2b2019-08-20 06:01:57 +030074 MAYBE_STATIC_BSS uint32_t tolm = 0;
Harry Pan43dcbfd2016-08-11 14:35:04 +080075
76 if (tolm)
77 return tolm;
78
79 tolm = iosf_bunit_read(BUNIT_BMBOUND) & ~((1 << 27) - 1);
80
81 return tolm;
Lee Leahy77ff0b12015-05-05 15:07:29 -070082}
83
Elyes HAOUASb13fac32018-05-24 22:29:44 +020084static void nc_read_resources(struct device *dev)
Lee Leahy77ff0b12015-05-05 15:07:29 -070085{
86 unsigned long mmconf;
Lee Leahy32471722015-04-20 15:20:28 -070087 unsigned long bmbound_k;
Lee Leahy77ff0b12015-05-05 15:07:29 -070088 unsigned long bmbound_hi;
Kyösti Mälkki14222d82019-08-05 15:10:18 +030089 uintptr_t smm_base;
Lee Leahy32471722015-04-20 15:20:28 -070090 size_t smm_size;
91 unsigned long tseg_base_k;
92 unsigned long tseg_top_k;
93 unsigned long fsp_res_base_k;
Lee Leahy77ff0b12015-05-05 15:07:29 -070094 unsigned long base_k, size_k;
95 const unsigned long four_gig_kib = (4 << (30 - 10));
Frans Hendriksc6d672f2018-10-30 15:07:39 +010096 void *fsp_reserved_memory_area;
Lee Leahy77ff0b12015-05-05 15:07:29 -070097 int index = 0;
98
99 /* Read standard PCI resources. */
100 pci_dev_read_resources(dev);
101
Lee Leahy32471722015-04-20 15:20:28 -0700102 /* Determine TSEG data */
103 smm_region(&smm_base, &smm_size);
Kyösti Mälkki14222d82019-08-05 15:10:18 +0300104 tseg_base_k = RES_IN_KIB(smm_base);
Lee Leahy32471722015-04-20 15:20:28 -0700105 tseg_top_k = tseg_base_k + RES_IN_KIB(smm_size);
106
107 /* Determine the base of the FSP reserved memory */
Frans Hendriksc6d672f2018-10-30 15:07:39 +0100108 fsp_reserved_memory_area = cbmem_find(CBMEM_ID_FSP_RESERVED_MEMORY);
109 if (fsp_reserved_memory_area) {
110 fsp_res_base_k =
111 RES_IN_KIB((unsigned int)fsp_reserved_memory_area);
112 } else {
113 /* If no FSP reserverd area */
114 fsp_res_base_k = tseg_base_k;
115 }
Lee Leahy32471722015-04-20 15:20:28 -0700116
Lee Leahy77ff0b12015-05-05 15:07:29 -0700117 /* PCIe memory-mapped config space access - 256 MiB. */
118 mmconf = iosf_bunit_read(BUNIT_MMCONF_REG) & ~((1 << 28) - 1);
Lee Leahy32471722015-04-20 15:20:28 -0700119 mmio_resource(dev, BUNIT_MMCONF_REG, RES_IN_KIB(mmconf), 256 * 1024);
Lee Leahy77ff0b12015-05-05 15:07:29 -0700120
121 /* 0 -> 0xa0000 */
Lee Leahy32471722015-04-20 15:20:28 -0700122 base_k = RES_IN_KIB(0);
123 size_k = RES_IN_KIB(0xa0000) - base_k;
Lee Leahy77ff0b12015-05-05 15:07:29 -0700124 ram_resource(dev, index++, base_k, size_k);
125
Frans Hendriksc6d672f2018-10-30 15:07:39 +0100126 /* High memory -> fsp_res_base - cacheable and usable */
127 base_k = RES_IN_KIB(0x100000);
Lee Leahy32471722015-04-20 15:20:28 -0700128 size_k = fsp_res_base_k - base_k;
Lee Leahy77ff0b12015-05-05 15:07:29 -0700129 ram_resource(dev, index++, base_k, size_k);
130
Lee Leahy32471722015-04-20 15:20:28 -0700131 /* fsp_res_base -> tseg_top - Reserved */
132 base_k = fsp_res_base_k;
133 size_k = tseg_top_k - base_k;
134 reserved_ram_resource(dev, index++, base_k, size_k);
Lee Leahy77ff0b12015-05-05 15:07:29 -0700135
Lee Leahy32471722015-04-20 15:20:28 -0700136 /* TSEG TOP -> bmbound is memory backed mmio. */
137 bmbound_k = RES_IN_KIB(nc_read_top_of_low_memory());
138 mmio_resource(dev, index++, tseg_top_k, bmbound_k - tseg_top_k);
Lee Leahy77ff0b12015-05-05 15:07:29 -0700139
Lee Leahy32471722015-04-20 15:20:28 -0700140 /*
141 * The BMBOUND_HI register matches register bits of 31:24 with address
142 * bits of 35:28. Therefore, shift register to align properly.
143 */
Lee Leahy77ff0b12015-05-05 15:07:29 -0700144 bmbound_hi = iosf_bunit_read(BUNIT_BMBOUND_HI) & ~((1 << 24) - 1);
Lee Leahy32471722015-04-20 15:20:28 -0700145 bmbound_hi = RES_IN_KIB(bmbound_hi) << 4;
Lee Leahy77ff0b12015-05-05 15:07:29 -0700146 if (bmbound_hi > four_gig_kib)
147 ram_resource(dev, index++, four_gig_kib,
Lee Leahy32471722015-04-20 15:20:28 -0700148 bmbound_hi - four_gig_kib);
Lee Leahy77ff0b12015-05-05 15:07:29 -0700149
Lee Leahy32471722015-04-20 15:20:28 -0700150 /*
151 * Reserve everything between A segment and 1MB:
Lee Leahy77ff0b12015-05-05 15:07:29 -0700152 *
153 * 0xa0000 - 0xbffff: legacy VGA
154 * 0xc0000 - 0xfffff: RAM
155 */
156 mmio_resource(dev, index++, (0xa0000 >> 10), (0xc0000 - 0xa0000) >> 10);
157 reserved_ram_resource(dev, index++, (0xc0000 >> 10),
Lee Leahy32471722015-04-20 15:20:28 -0700158 (0x100000 - 0xc0000) >> 10);
Lee Leahy77ff0b12015-05-05 15:07:29 -0700159
Frans Hendriksd97eb642018-11-26 11:01:56 +0100160 /*
161 * Reserve local APIC
162 */
163 base_k = RES_IN_KIB(LAPIC_DEFAULT_BASE);
164 size_k = RES_IN_KIB(0x00100000);
165 mmio_resource(dev, index++, base_k, size_k);
166
Julius Wernercd49cce2019-03-05 16:53:33 -0800167 if (CONFIG(CHROMEOS))
Frans Hendriksed7780d2018-12-14 07:49:18 +0100168 chromeos_reserve_ram_oops(dev, index++);
Lee Leahy77ff0b12015-05-05 15:07:29 -0700169}
170
171static struct device_operations nc_ops = {
Lee Leahy32471722015-04-20 15:20:28 -0700172 .acpi_fill_ssdt_generator = generate_cpu_entries,
173 .read_resources = nc_read_resources,
174 .ops_pci = &soc_pci_ops,
Lee Leahy77ff0b12015-05-05 15:07:29 -0700175};
176
177static const struct pci_driver nc_driver __pci_driver = {
178 .ops = &nc_ops,
179 .vendor = PCI_VENDOR_ID_INTEL,
180 .device = SOC_DEVID,
181};