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Lee Leahy77ff0b12015-05-05 15:07:29 -07001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2013 Google Inc.
Lee Leahy32471722015-04-20 15:20:28 -07005 * Copyright (C) 2015 Intel Corp.
Lee Leahy77ff0b12015-05-05 15:07:29 -07006 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
Lee Leahy77ff0b12015-05-05 15:07:29 -070015 */
16
Lee Leahy32471722015-04-20 15:20:28 -070017#ifndef _SOC_RAMSTAGE_H_
18#define _SOC_RAMSTAGE_H_
Lee Leahy77ff0b12015-05-05 15:07:29 -070019
20#include <device/device.h>
Lee Leahy94b856e2015-10-15 12:07:03 -070021#include <fsp/ramstage.h>
Lee Leahy77ff0b12015-05-05 15:07:29 -070022
Elyes HAOUASc3385072019-03-21 15:38:06 +010023#include "../../chip.h"
24
Matt DeVillier143a8362017-08-26 04:47:15 -050025#define V_PCH_LPC_RID_A0 0x00 // A0 Stepping
26#define V_PCH_LPC_RID_A1 0x04 // A1 Stepping
27#define V_PCH_LPC_RID_A2 0x08 // A2 Stepping
28#define V_PCH_LPC_RID_A3 0x0C // A3 Stepping
29#define V_PCH_LPC_RID_A4 0x80 // A4 Stepping
30#define V_PCH_LPC_RID_A5 0x84 // A5 Stepping
31#define V_PCH_LPC_RID_A6 0x88 // A6 Stepping
32#define V_PCH_LPC_RID_A7 0x8C // A7 Stepping
33#define V_PCH_LPC_RID_B0 0x10 // B0 Stepping
34#define V_PCH_LPC_RID_B1 0x14 // B1 Stepping
35#define V_PCH_LPC_RID_B2 0x18 // B2 Stepping
36#define V_PCH_LPC_RID_B3 0x1C // B3 Stepping
37#define V_PCH_LPC_RID_B4 0x90 // B4 Stepping
38#define V_PCH_LPC_RID_B5 0x94 // B5 Stepping
39#define V_PCH_LPC_RID_B6 0x98 // B6 Stepping
40#define V_PCH_LPC_RID_B7 0x9C // B7 Stepping
41#define V_PCH_LPC_RID_C0 0x20 // C0 Stepping
42#define V_PCH_LPC_RID_C1 0x24 // C1 Stepping
43#define V_PCH_LPC_RID_C2 0x28 // C2 Stepping
44#define V_PCH_LPC_RID_C3 0x2C // C3 Stepping
45#define V_PCH_LPC_RID_C4 0xA0 // C4 Stepping
46#define V_PCH_LPC_RID_C5 0xA4 // C5 Stepping
47#define V_PCH_LPC_RID_C6 0xA8 // C6 Stepping
48#define V_PCH_LPC_RID_C7 0xAC // C7 Stepping
49#define V_PCH_LPC_RID_D0 0x30 // D0 Stepping
50#define V_PCH_LPC_RID_D1 0x34 // D1 Stepping
51#define V_PCH_LPC_RID_D2 0x38 // D2 Stepping
52#define V_PCH_LPC_RID_D3 0x3C // D3 Stepping
53#define V_PCH_LPC_RID_D4 0xB0 // D4 Stepping
54#define V_PCH_LPC_RID_D5 0xB4 // D5 Stepping
55#define V_PCH_LPC_RID_D6 0xB8 // D6 Stepping
56#define V_PCH_LPC_RID_D7 0xBC // D7 Stepping
57#define B_PCH_LPC_RID_STEPPING_MASK 0xFC // SoC Stepping Mask (Ignoring Package Type)
58
59enum {
60 SocA0 = 0,
61 SocA1 = 1,
62 SocA2 = 2,
63 SocA3 = 3,
64 SocA4 = 4,
65 SocA5 = 5,
66 SocA6 = 6,
67 SocA7 = 7,
68 SocB0 = 8,
69 SocB1 = 9,
70 SocB2 = 10,
71 SocB3 = 11,
72 SocB4 = 12,
73 SocB5 = 13,
74 SocB6 = 14,
75 SocB7 = 15,
76 SocC0 = 16,
77 SocC1 = 17,
78 SocC2 = 18,
79 SocC3 = 19,
80 SocC4 = 20,
81 SocC5 = 21,
82 SocC6 = 22,
83 SocC7 = 23,
84 SocD0 = 24,
85 SocD1 = 25,
86 SocD2 = 26,
87 SocD3 = 27,
88 SocD4 = 28,
89 SocD5 = 29,
90 SocD6 = 30,
91 SocD7 = 31,
92 SocSteppingMax
93};
94
Lee Leahy32471722015-04-20 15:20:28 -070095/*
96 * The soc_init_pre_device() function is called prior to device
97 * initialization, but it's after console and cbmem has been reinitialized.
98 */
99void soc_init_pre_device(struct soc_intel_braswell_config *config);
Elyes HAOUASb13fac32018-05-24 22:29:44 +0200100void soc_init_cpus(struct device *dev);
Elyes HAOUASb13fac32018-05-24 22:29:44 +0200101void southcluster_enable_dev(struct device *dev);
102void scc_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index);
Matt DeVillier143a8362017-08-26 04:47:15 -0500103int SocStepping(void);
Matt DeVillier2c8ac222017-08-26 04:53:35 -0500104void board_silicon_USB2_override(SILICON_INIT_UPD *params);
Lee Leahy77ff0b12015-05-05 15:07:29 -0700105
106extern struct pci_operations soc_pci_ops;
107
Lee Leahy32471722015-04-20 15:20:28 -0700108#endif /* _SOC_RAMSTAGE_H_ */