blob: 854b858e7fdae3a3bdedefb5ba94866f8d6c443d [file] [log] [blame]
Lee Leahy77ff0b12015-05-05 15:07:29 -07001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2013 Google Inc.
Lee Leahy32471722015-04-20 15:20:28 -07005 * Copyright (C) 2015 Intel Corp.
Frans Hendriks339738632019-03-04 15:35:36 +01006 * Copyright (C) 2019 Eltan B.V.
Lee Leahy77ff0b12015-05-05 15:07:29 -07007 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
Lee Leahy77ff0b12015-05-05 15:07:29 -070016 */
17
Lee Leahy32471722015-04-20 15:20:28 -070018#ifndef _SOC_PCI_DEVS_H_
19#define _SOC_PCI_DEVS_H_
Lee Leahy77ff0b12015-05-05 15:07:29 -070020
21/* All these devices live on bus 0 with the associated device and function */
22
23/* SoC transaction router */
24#define SOC_DEV 0x0
25#define SOC_FUNC 0
Lee Leahy77ff0b12015-05-05 15:07:29 -070026
27/* Graphics and Display */
28#define GFX_DEV 0x2
29#define GFX_FUNC 0
Lee Leahy32471722015-04-20 15:20:28 -070030
Frans Hendriks339738632019-03-04 15:35:36 +010031/* P-Unit DPTF */
32#define PUNIT_DEV 0xB
33#define PUNIT_FUNC 0
Frans Hendriks339738632019-03-04 15:35:36 +010034
Lee Leahy32471722015-04-20 15:20:28 -070035/* MMC Port */
36#define MMC_DEV 0x10
37#define MMC_FUNC 0
Lee Leahy77ff0b12015-05-05 15:07:29 -070038
39/* SDIO Port */
40#define SDIO_DEV 0x11
41#define SDIO_FUNC 0
Lee Leahy77ff0b12015-05-05 15:07:29 -070042
43/* SD Port */
44#define SD_DEV 0x12
45#define SD_FUNC 0
Lee Leahy77ff0b12015-05-05 15:07:29 -070046
47/* SATA */
48#define SATA_DEV 0x13
49#define SATA_FUNC 0
Lee Leahy77ff0b12015-05-05 15:07:29 -070050
51/* xHCI */
52#define XHCI_DEV 0x14
53#define XHCI_FUNC 0
Lee Leahy77ff0b12015-05-05 15:07:29 -070054
55/* LPE Audio */
56#define LPE_DEV 0x15
57#define LPE_FUNC 0
Lee Leahy77ff0b12015-05-05 15:07:29 -070058
59/* Serial IO 1 */
60#define SIO1_DEV 0x18
61# define SIO_DMA1_DEV SIO1_DEV
62# define SIO_DMA1_FUNC 0
Lee Leahy77ff0b12015-05-05 15:07:29 -070063# define I2C1_DEV SIO1_DEV
64# define I2C1_FUNC 1
Lee Leahy77ff0b12015-05-05 15:07:29 -070065# define I2C2_DEV SIO1_DEV
66# define I2C2_FUNC 2
Lee Leahy77ff0b12015-05-05 15:07:29 -070067# define I2C3_DEV SIO1_DEV
68# define I2C3_FUNC 3
Lee Leahy77ff0b12015-05-05 15:07:29 -070069# define I2C4_DEV SIO1_DEV
70# define I2C4_FUNC 4
Lee Leahy77ff0b12015-05-05 15:07:29 -070071# define I2C5_DEV SIO1_DEV
72# define I2C5_FUNC 5
Lee Leahy77ff0b12015-05-05 15:07:29 -070073# define I2C6_DEV SIO1_DEV
74# define I2C6_FUNC 6
Lee Leahy77ff0b12015-05-05 15:07:29 -070075# define I2C7_DEV SIO1_DEV
76# define I2C7_FUNC 7
Lee Leahy77ff0b12015-05-05 15:07:29 -070077
78/* Trusted Execution Engine */
79#define TXE_DEV 0x1a
80#define TXE_FUNC 0
Lee Leahy77ff0b12015-05-05 15:07:29 -070081
82/* HD Audio */
83#define HDA_DEV 0x1b
84#define HDA_FUNC 0
Lee Leahy77ff0b12015-05-05 15:07:29 -070085
86/* PCIe Ports */
87#define PCIE_DEV 0x1c
88# define PCIE_PORT1_DEV PCIE_DEV
89# define PCIE_PORT1_FUNC 0
Lee Leahy77ff0b12015-05-05 15:07:29 -070090# define PCIE_PORT2_DEV PCIE_DEV
91# define PCIE_PORT2_FUNC 1
Lee Leahy77ff0b12015-05-05 15:07:29 -070092# define PCIE_PORT3_DEV PCIE_DEV
93# define PCIE_PORT3_FUNC 2
Lee Leahy77ff0b12015-05-05 15:07:29 -070094# define PCIE_PORT4_DEV PCIE_DEV
95# define PCIE_PORT4_FUNC 3
Lee Leahy32471722015-04-20 15:20:28 -070096/* Total number of ROOT PORTS */
97#define MAX_ROOT_PORTS_BSW 4
Lee Leahy77ff0b12015-05-05 15:07:29 -070098
99/* Serial IO 2 */
100#define SIO2_DEV 0x1e
101# define SIO_DMA2_DEV SIO2_DEV
102# define SIO_DMA2_FUNC 0
Lee Leahy77ff0b12015-05-05 15:07:29 -0700103# define PWM1_DEV SIO2_DEV
104# define PWM1_FUNC 1
Lee Leahy77ff0b12015-05-05 15:07:29 -0700105# define PWM2_DEV SIO2_DEV
106# define PWM2_FUNC 2
Lee Leahy77ff0b12015-05-05 15:07:29 -0700107# define HSUART1_DEV SIO2_DEV
108# define HSUART1_FUNC 3
Lee Leahy77ff0b12015-05-05 15:07:29 -0700109# define HSUART2_DEV SIO2_DEV
110# define HSUART2_FUNC 4
Lee Leahy77ff0b12015-05-05 15:07:29 -0700111# define SPI_DEV SIO2_DEV
112# define SPI_FUNC 5
Lee Leahy77ff0b12015-05-05 15:07:29 -0700113
114/* Platform Controller Unit */
115#define PCU_DEV 0x1f
116# define LPC_DEV PCU_DEV
117# define LPC_FUNC 0
Lee Leahy77ff0b12015-05-05 15:07:29 -0700118# define SMBUS_DEV PCU_DEV
119# define SMBUS_FUNC 3
Lee Leahy77ff0b12015-05-05 15:07:29 -0700120
Lee Leahy32471722015-04-20 15:20:28 -0700121/* PCH SCC Device Modes */
122#define PCH_DISABLED 0
123#define PCH_PCI_MODE 1
124#define PCH_ACPI_MODE 2
Kyösti Mälkki0b4298c2019-09-29 21:17:46 +0300125
126#define SOC_DEVID 0x2280
127#define GFX_DEVID 0x22b1
128#define PUNIT_DEVID 0x22DC
129#define MMC_DEVID 0x2294
130#define SDIO_DEVID 0x2295
131#define SD_DEVID 0x2296
132#define AHCI1_DEVID 0x22a3
133#define XHCI_DEVID 0x22b5
134#define LPE_DEVID 0x22a8
135#define SIO_DMA1_DEVID 0x22c0
136#define I2C1_DEVID 0x22c1
137#define I2C2_DEVID 0x22c2
138#define I2C3_DEVID 0x22c3
139#define I2C4_DEVID 0x22c4
140#define I2C5_DEVID 0x22c5
141#define I2C6_DEVID 0x22c6
142#define I2C7_DEVID 0x22c7
143#define TXE_DEVID 0x2298
144#define HDA_DEVID 0x2284
145#define PCIE_PORT1_DEVID 0x22c8
146#define PCIE_PORT2_DEVID 0x22ca
147#define PCIE_PORT3_DEVID 0x22cc
148#define PCIE_PORT4_DEVID 0x22ce
149#define SIO_DMA2_DEVID 0x2286
150#define PWM1_DEVID 0x2288
151#define PWM2_DEVID 0x2289
152#define HSUART1_DEVID 0x228a
153#define HSUART2_DEVID 0x228c
154#define SPI_DEVID 0x228e
155#define LPC_DEVID 0x229c
156#define SMBUS_DEVID 0x0f12
157
Lee Leahy32471722015-04-20 15:20:28 -0700158#endif /* _SOC_PCI_DEVS_H_ */