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Lee Leahy77ff0b12015-05-05 15:07:29 -07001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2008-2009 coresystems GmbH
5 * Copyright (C) 2011 Google Inc
Lee Leahy32471722015-04-20 15:20:28 -07006 * Copyright (C) 2015 Intel Corp.
Lee Leahy77ff0b12015-05-05 15:07:29 -07007 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
Lee Leahy77ff0b12015-05-05 15:07:29 -070016 */
17
Lee Leahy32471722015-04-20 15:20:28 -070018#ifndef _SOC_NVS_H_
19#define _SOC_NVS_H_
Lee Leahy77ff0b12015-05-05 15:07:29 -070020
Jonathan Neuschäfer0781cbe2017-10-30 17:20:18 +010021#include <commonlib/helpers.h>
Lee Leahy77ff0b12015-05-05 15:07:29 -070022#include <soc/device_nvs.h>
Jonathan Neuschäfer0781cbe2017-10-30 17:20:18 +010023#include <vendorcode/google/chromeos/gnvs.h>
Lee Leahy77ff0b12015-05-05 15:07:29 -070024
Jonathan Neuschäfer0781cbe2017-10-30 17:20:18 +010025typedef struct global_nvs_t {
Lee Leahy77ff0b12015-05-05 15:07:29 -070026 /* Miscellaneous */
27 u16 osys; /* 0x00 - Operating System */
28 u8 smif; /* 0x02 - SMI function call ("TRAP") */
29 u8 prm0; /* 0x03 - SMI function call parameter */
30 u8 prm1; /* 0x04 - SMI function call parameter */
31 u8 scif; /* 0x05 - SCI function call (via _L00) */
32 u8 prm2; /* 0x06 - SCI function call parameter */
33 u8 prm3; /* 0x07 - SCI function call parameter */
34 u8 lckf; /* 0x08 - Global Lock function for EC */
35 u8 prm4; /* 0x09 - Lock function parameter */
36 u8 prm5; /* 0x0a - Lock function parameter */
37 u32 p80d; /* 0x0b - Debug port (IO 0x80) value */
38 u8 lids; /* 0x0f - LID state (open = 1) */
39 u8 pwrs; /* 0x10 - Power state (AC = 1) */
Lee Leahy32471722015-04-20 15:20:28 -070040 u8 pcnt; /* 0x11 - Processor Count */
Lee Leahy77ff0b12015-05-05 15:07:29 -070041 u8 tpmp; /* 0x12 - TPM Present and Enabled */
42 u8 tlvl; /* 0x13 - Throttle Level */
43 u8 ppcm; /* 0x14 - Maximum P-state usable by OS */
44 u32 pm1i; /* 0x15 - System Wake Source - PM1 Index */
Duncan Lauriee73da802015-09-08 16:16:34 -070045 u32 gpei; /* 0x19 - GPE Wake Source */
46 u8 bdid; /* 0x1d - Board ID */
Felix Durairaj15184e02015-11-23 14:07:40 -080047 u16 cid1; /* 0x1a - Wifi Country Identifier */
Lee Leahy77ff0b12015-05-05 15:07:29 -070048
49 /* Device Config */
50 u8 s5u0; /* 0x20 - Enable USB0 in S5 */
51 u8 s5u1; /* 0x21 - Enable USB1 in S5 */
52 u8 s3u0; /* 0x22 - Enable USB0 in S3 */
53 u8 s3u1; /* 0x23 - Enable USB1 in S3 */
54 u8 tact; /* 0x24 - Thermal Active trip point */
55 u8 tpsv; /* 0x25 - Thermal Passive trip point */
56 u8 tcrt; /* 0x26 - Thermal Critical trip point */
57 u8 dpte; /* 0x27 - Enable DPTF */
58 u8 rsvd2[8];
59
60 /* Base Addresses */
Lee Leahy32471722015-04-20 15:20:28 -070061 u32 cmem; /* 0x30 - CBMEM TOC */
Lee Leahy77ff0b12015-05-05 15:07:29 -070062 u32 tolm; /* 0x34 - Top of Low Memory */
63 u32 cbmc; /* 0x38 - coreboot memconsole */
Matt DeVillier132bbe62017-07-01 13:02:47 -050064 u8 rsvd3[120]; /* 0x3c - 0xb3 - unused */
65
66 /* IGD OpRegion */
67 u32 aslb; /* 0xb4 - IGD OpRegion Base Address */
68 u8 ibtt; /* 0xb8 - IGD boot type */
69 u8 ipat; /* 0xb9 - IGD panel type */
70 u8 itvf; /* 0xba - IGD TV format */
71 u8 itvm; /* 0xbb - IGD TV minor format */
72 u8 ipsc; /* 0xbc - IGD Panel Scaling */
73 u8 iblc; /* 0xbd - IGD BLC configuration */
74 u8 ibia; /* 0xbe - IGD BIA configuration */
75 u8 issc; /* 0xbf - IGD SSC configuration */
76 u8 i409; /* 0xc0 - IGD 0409 modified settings */
77 u8 i509; /* 0xc1 - IGD 0509 modified settings */
78 u8 i609; /* 0xc2 - IGD 0609 modified settings */
79 u8 i709; /* 0xc3 - IGD 0709 modified settings */
80 u8 idmm; /* 0xc4 - IGD Power Conservation */
81 u8 idms; /* 0xc5 - IGD DVMT memory size */
82 u8 if1e; /* 0xc6 - IGD Function 1 Enable */
83 u8 hvco; /* 0xc7 - IGD HPLL VCO */
84 u32 nxd[8]; /* 0xc8 - IGD next state DIDx for _DGS */
85 u8 isci; /* 0xe8 - IGD SMI/SCI mode (0: SCI) */
86 u8 pavp; /* 0xe9 - IGD PAVP data */
87 u8 rsvd12; /* 0xea - rsvd */
88 u8 oscc; /* 0xeb - PCIe OSC control */
89 u8 npce; /* 0xec - native pcie support */
90 u8 plfl; /* 0xed - platform flavor */
91 u8 brev; /* 0xee - board revision */
92 u8 dpbm; /* 0xef - digital port b mode */
93 u8 dpcm; /* 0xf0 - digital port c mode */
94 u8 dpdm; /* 0xf1 - digital port c mode */
95 u8 alfp; /* 0xf2 - active lfp */
96 u8 imon; /* 0xf3 - current graphics turbo imon value */
97 u8 mmio; /* 0xf4 - 64bit mmio support */
98
99 u8 unused[11];
Lee Leahy77ff0b12015-05-05 15:07:29 -0700100
Lee Leahy32471722015-04-20 15:20:28 -0700101 /* ChromeOS specific (0x100-0xfff) */
Lee Leahy77ff0b12015-05-05 15:07:29 -0700102 chromeos_acpi_t chromeos;
103
Lee Leahy32471722015-04-20 15:20:28 -0700104 /* LPSS (0x1000) */
Lee Leahy77ff0b12015-05-05 15:07:29 -0700105 device_nvs_t dev;
Stefan Reinauer6a001132017-07-13 02:20:27 +0200106} __packed global_nvs_t;
Joel Kitching44cff7a2018-08-17 15:38:59 +0800107check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
Lee Leahy77ff0b12015-05-05 15:07:29 -0700108
Lee Leahy32471722015-04-20 15:20:28 -0700109void acpi_create_gnvs(global_nvs_t *gnvs);
Lee Leahy77ff0b12015-05-05 15:07:29 -0700110/* Used in SMM to find the ACPI GNVS address */
111global_nvs_t *smm_get_gnvs(void);
Lee Leahy77ff0b12015-05-05 15:07:29 -0700112
Lee Leahy32471722015-04-20 15:20:28 -0700113#endif /* _SOC_NVS_H_ */