blob: 1a56f9e8c18fb140d9c4617e60c9c7d14c4759ed [file] [log] [blame]
Lee Leahy77ff0b12015-05-05 15:07:29 -07001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2013 Google Inc.
Lee Leahy32471722015-04-20 15:20:28 -07005 * Copyright (C) 2015 Intel Corp.
Frans Hendriks83e73242018-07-13 09:52:04 +02006 * Copyright (C) 2018 Eltan B.V.
Lee Leahy77ff0b12015-05-05 15:07:29 -07007 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
Lee Leahy77ff0b12015-05-05 15:07:29 -070016 */
17
Lee Leahy32471722015-04-20 15:20:28 -070018#ifndef _SOC_LPC_H_
19#define _SOC_LPC_H_
Lee Leahy77ff0b12015-05-05 15:07:29 -070020
21/* PCI config registers in LPC bridge. */
22#define REVID 0x08
23#define ABASE 0x40
24#define PBASE 0x44
25#define GBASE 0x48
26#define IOBASE 0x4c
27#define IBASE 0x50
28#define SBASE 0x54
29#define MPBASE 0x58
30#define PUBASE 0x5c
31#define UART_CONT 0x80
32#define RCBA 0xf0
33
Frans Hendriks2c630172019-04-02 15:06:29 +020034/* iLB Memory Mapped IO */
35#define ILB_OIC 0x60
36#define SIRQEN (1 << 12)
37
Hannah Williams3fa80a92017-03-22 16:33:36 -070038/* Memory Mapped IO in LPC bridge */
39#define SCNT 0x10
40#define SCNT_MODE (1 << 7) /* When cleared, SERIRQ is in quiet mode */
Lee Leahy77ff0b12015-05-05 15:07:29 -070041
42#define RID_A_STEPPING_START 1
43#define RID_B_STEPPING_START 5
Frans Hendriks83e73242018-07-13 09:52:04 +020044#define RID_C_STEPPING_START 0x21
45#define RID_D_STEPPING_START 0x35
Lee Leahy32471722015-04-20 15:20:28 -070046enum soc_stepping {
Lee Leahy77ff0b12015-05-05 15:07:29 -070047 STEP_A0,
48 STEP_A1,
49 STEP_B0,
50 STEP_B1,
51 STEP_B2,
52 STEP_B3,
53 STEP_C0,
Frans Hendriks83e73242018-07-13 09:52:04 +020054 STEP_D1,
Lee Leahy77ff0b12015-05-05 15:07:29 -070055};
56
57/* Registers behind the RCBA_BASE_ADDRESS bar. */
58#define GCS 0x00
59# define BILD (1 << 0)
60
Lee Leahy32471722015-04-20 15:20:28 -070061#endif /* _SOC_LPC_H_ */