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Lee Leahy77ff0b12015-05-05 15:07:29 -07001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2013 Google Inc.
Lee Leahy32471722015-04-20 15:20:28 -07005 * Copyright (C) 2015 Intel Corp.
Frans Hendriks190e5be2018-10-31 13:58:26 +01006 * Copyright (C) 2018 Eltan B.V.
Lee Leahy77ff0b12015-05-05 15:07:29 -07007 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
Lee Leahy77ff0b12015-05-05 15:07:29 -070016 */
17
Lee Leahy32471722015-04-20 15:20:28 -070018#ifndef _SOC_IRQ_H_
19#define _SOC_IRQ_H_
Lee Leahy77ff0b12015-05-05 15:07:29 -070020
21#define PIRQA_APIC_IRQ 16
22#define PIRQB_APIC_IRQ 17
23#define PIRQC_APIC_IRQ 18
24#define PIRQD_APIC_IRQ 19
25#define PIRQE_APIC_IRQ 20
26#define PIRQF_APIC_IRQ 21
27#define PIRQG_APIC_IRQ 22
28#define PIRQH_APIC_IRQ 23
Lee Leahy32471722015-04-20 15:20:28 -070029
Lee Leahy77ff0b12015-05-05 15:07:29 -070030/* The below IRQs are for when devices are in ACPI mode. Active low. */
31#define LPE_DMA0_IRQ 24
32#define LPE_DMA1_IRQ 25
33#define LPE_SSP0_IRQ 26
34#define LPE_SSP1_IRQ 27
35#define LPE_SSP2_IRQ 28
36#define LPE_IPC2HOST_IRQ 29
37#define LPSS_I2C1_IRQ 32
38#define LPSS_I2C2_IRQ 33
39#define LPSS_I2C3_IRQ 34
40#define LPSS_I2C4_IRQ 35
41#define LPSS_I2C5_IRQ 36
42#define LPSS_I2C6_IRQ 37
43#define LPSS_I2C7_IRQ 38
44#define LPSS_HSUART1_IRQ 39
45#define LPSS_HSUART2_IRQ 40
46#define LPSS_SPI_IRQ 41
47#define LPSS_DMA1_IRQ 42
48#define LPSS_DMA2_IRQ 43
Lee Leahy32471722015-04-20 15:20:28 -070049#define SCC_EMMC_IRQ 45
Lee Leahy77ff0b12015-05-05 15:07:29 -070050#define SCC_SDIO_IRQ 46
Lee Leahy32471722015-04-20 15:20:28 -070051#define SCC_SD_IRQ 47
52
53#define GPIO_N_IRQ 48
54#define GPIO_SW_IRQ 49
55#define GPIO_E_IRQ 50
56
Lee Leahy77ff0b12015-05-05 15:07:29 -070057/* GPIO direct / dedicated IRQs. */
Lee Leahy32471722015-04-20 15:20:28 -070058
59/* NORTH COMMUNITY */
60#define GPIO_N_DED_IRQ_0 51
61#define GPIO_N_DED_IRQ_1 52
62#define GPIO_N_DED_IRQ_2 53
63#define GPIO_N_DED_IRQ_3 54
64#define GPIO_N_DED_IRQ_4 55
65#define GPIO_N_DED_IRQ_5 56
66#define GPIO_N_DED_IRQ_6 57
67#define GPIO_N_DED_IRQ_7 58
68
69/* SOUTH WEST COMMUNITY */
70#define GPIO_SW_DED_IRQ_0 59
71#define GPIO_SW_DED_IRQ_1 60
72#define GPIO_SW_DED_IRQ_2 61
73#define GPIO_SW_DED_IRQ_3 62
74#define GPIO_SW_DED_IRQ_4 63
75#define GPIO_SW_DED_IRQ_5 64
76#define GPIO_SW_DED_IRQ_6 65
77#define GPIO_SW_DED_IRQ_7 66
78
79/* EAST COMMUNITY */
80#define GPIO_E_DED_IRQ_0 67
81#define GPIO_E_DED_IRQ_1 68
82#define GPIO_E_DED_IRQ_2 69
83#define GPIO_E_DED_IRQ_3 70
84#define GPIO_E_DED_IRQ_4 71
85#define GPIO_E_DED_IRQ_5 72
86#define GPIO_E_DED_IRQ_6 73
87#define GPIO_E_DED_IRQ_7 74
88#define GPIO_E_DED_IRQ_8 75
89#define GPIO_E_DED_IRQ_9 76
90#define GPIO_E_DED_IRQ_10 77
91#define GPIO_E_DED_IRQ_11 78
92#define GPIO_E_DED_IRQ_12 79
93#define GPIO_E_DED_IRQ_13 80
94#define GPIO_E_DED_IRQ_14 81
95#define GPIO_E_DED_IRQ_15 82
96
97/* More IRQ */
98#define LPSS_SPI2_IRQ 89
99#define LPSS_SPI3_IRQ 90
100#define GPIO_SE_IRQ 91
101
102/* GPIO direct / dedicated IRQs. */
103/* SOUTH EAST COMMUNITY */
104#define GPIO_SE_DED_IRQ_0 92
105#define GPIO_SE_DED_IRQ_1 93
106#define GPIO_SE_DED_IRQ_2 94
107#define GPIO_SE_DED_IRQ_3 95
108#define GPIO_SE_DED_IRQ_4 96
109#define GPIO_SE_DED_IRQ_5 97
110#define GPIO_SE_DED_IRQ_6 98
111#define GPIO_SE_DED_IRQ_7 99
112#define GPIO_SE_DED_IRQ_8 100
113#define GPIO_SE_DED_IRQ_9 101
114#define GPIO_SE_DED_IRQ_10 102
115#define GPIO_SE_DED_IRQ_11 103
116#define GPIO_SE_DED_IRQ_12 104
117#define GPIO_SE_DED_IRQ_13 105
118#define GPIO_SE_DED_IRQ_14 106
119#define GPIO_SE_DED_IRQ_15 107
120
121/* OTHER IRQs */
122#define GPIO_VIRTUAL 108
123#define LPE_DMA2 109
124#define LPE_SSP3 110
125#define LPE_SSP4 111
126#define LPE_SSP5 112
127
Lee Leahy77ff0b12015-05-05 15:07:29 -0700128/* DIRQs - Two levels of expansion to evaluate to numeric constants for ASL. */
Lee Leahy32471722015-04-20 15:20:28 -0700129#define _GPIO_N_DED_IRQ(slot) GPIO_N_DED_IRQ_##slot
130#define _GPIO_SW_DED_IRQ(slot) GPIO_SW_DED_IRQ_##slot
131#define _GPIO_E_DED_IRQ(slot) GPIO_E_DED_IRQ_##slot
132#define _GPIO_SE_DED_IRQ(slot) GPIO_SE_DED_IRQ_##slot
133#define GPIO_N_DED_IRQ(slot) _GPIO_N_DED_IRQ(slot)
134#define GPIO_SW_DED_IRQ(slot) _GPIO_SW_DED_IRQ(slot)
135#define GPIO_E_DED_IRQ(slot) _GPIO_E_DED_IRQ(slot)
136#define GPIO_SE_DED_IRQ(slot) _GPIO_SE_DED_IRQ(slot)
137
138/* TODO NEED TO UPDATE THESE IN onboard.h */
139#define _GPIO_S0_DED_IRQ(slot) GPIO_N_DED_IRQ_##slot
140#define _GPIO_S5_DED_IRQ(slot) GPIO_SE_DED_IRQ_##slot
141#define GPIO_S0_DED_IRQ(slot) _GPIO_N_DED_IRQ(slot)
142#define GPIO_S5_DED_IRQ(slot) _GPIO_E_DED_IRQ(slot)
143
Lee Leahy77ff0b12015-05-05 15:07:29 -0700144
145/* PIC IRQ settings. */
Frans Hendriks190e5be2018-10-31 13:58:26 +0100146#define PIRQ_PIC_IRQDISABLE 0x80
Lee Leahy77ff0b12015-05-05 15:07:29 -0700147#define PIRQ_PIC_IRQ3 0x3
148#define PIRQ_PIC_IRQ4 0x4
149#define PIRQ_PIC_IRQ5 0x5
150#define PIRQ_PIC_IRQ6 0x6
151#define PIRQ_PIC_IRQ7 0x7
152#define PIRQ_PIC_IRQ9 0x9
153#define PIRQ_PIC_IRQ10 0xa
154#define PIRQ_PIC_IRQ11 0xb
155#define PIRQ_PIC_IRQ12 0xc
156#define PIRQ_PIC_IRQ14 0xe
157#define PIRQ_PIC_IRQ15 0xf
Frans Hendriks93484132018-12-10 12:38:16 +0100158#define PIRQ_PIC_UNKNOWN_UNUSED 0xff
Lee Leahy77ff0b12015-05-05 15:07:29 -0700159
160/* Overloaded term, but these values determine the per device route. */
161#define PIRQA 0
162#define PIRQB 1
163#define PIRQC 2
164#define PIRQD 3
165#define PIRQE 4
166#define PIRQF 5
167#define PIRQG 6
168#define PIRQH 7
169
170/* These registers live behind the ILB_BASE_ADDRESS */
171#define ACTL 0x00
172# define SCIS_MASK 0x07
173# define SCIS_IRQ9 0x00
174# define SCIS_IRQ10 0x01
175# define SCIS_IRQ11 0x02
176# define SCIS_IRQ20 0x04
177# define SCIS_IRQ21 0x05
178# define SCIS_IRQ22 0x06
179# define SCIS_IRQ23 0x07
180
Lee Leahy32471722015-04-20 15:20:28 -0700181/*
Frans Hendriks8bd5c992018-10-29 10:47:52 +0100182 * In each mainboard directory there should exist a header file irqroute.h that
Lee Leahy77ff0b12015-05-05 15:07:29 -0700183 * defines the PCI_DEV_PIRQ_ROUTES and PIRQ_PIC_ROUTES macros which
Lee Leahy32471722015-04-20 15:20:28 -0700184 * consist of PCI_DEV_PIRQ_ROUTE and PIRQ_PIC entries.
185 */
Lee Leahy77ff0b12015-05-05 15:07:29 -0700186
187#if !defined(__ASSEMBLER__) && !defined(__ACPI__)
188#include <stdint.h>
189
190#define NUM_IR_DEVS 32
191#define NUM_PIRQS 8
192
Lee Leahy32471722015-04-20 15:20:28 -0700193struct soc_irq_route {
Lee Leahy77ff0b12015-05-05 15:07:29 -0700194 /* Per device configuration. */
195 uint16_t pcidev[NUM_IR_DEVS];
196 /* Route path for each internal PIRQx in PIC mode. */
197 uint8_t pic[NUM_PIRQS];
198};
199
Lee Leahy32471722015-04-20 15:20:28 -0700200extern const struct soc_irq_route global_soc_irq_route;
Lee Leahy77ff0b12015-05-05 15:07:29 -0700201
202#define DEFINE_IRQ_ROUTES \
Lee Leahy32471722015-04-20 15:20:28 -0700203 const struct soc_irq_route global_soc_irq_route = { \
Lee Leahy77ff0b12015-05-05 15:07:29 -0700204 .pcidev = { PCI_DEV_PIRQ_ROUTES, }, \
205 .pic = { PIRQ_PIC_ROUTES, }, \
206 }
207
Lee Leahy32471722015-04-20 15:20:28 -0700208/* The following macros are used for ACPI by the ASL compiler */
Lee Leahy77ff0b12015-05-05 15:07:29 -0700209#define PCI_DEV_PIRQ_ROUTE(dev_, a_, b_, c_, d_) \
Lee Leahy32471722015-04-20 15:20:28 -0700210 [dev_] = (((PIRQ ## d_) << 12) | ((PIRQ ## c_) << 8) | \
211 ((PIRQ ## b_) << 4) | ((PIRQ ## a_) << 0))
Lee Leahy77ff0b12015-05-05 15:07:29 -0700212
213#define PIRQ_PIC(pirq_, pic_irq_) \
214 [PIRQ ## pirq_] = PIRQ_PIC_IRQ ## pic_irq_
215
216#endif /* !defined(__ASSEMBLER__) && !defined(__ACPI__) */
217
Lee Leahy32471722015-04-20 15:20:28 -0700218#endif /* _SOC_IRQ_H_ */