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Lee Leahy77ff0b12015-05-05 15:07:29 -07001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2013 Google Inc.
Lee Leahy32471722015-04-20 15:20:28 -07005 * Copyright (C) 2015 Intel Corp.
Frans Hendriks624195e2018-10-31 13:50:10 +01006 * Copyright (C) 2018 Eltan B.V.
Lee Leahy77ff0b12015-05-05 15:07:29 -07007 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
Lee Leahy77ff0b12015-05-05 15:07:29 -070016 */
17
Lee Leahy32471722015-04-20 15:20:28 -070018#ifndef _SOC_IOMAP_H_
19#define _SOC_IOMAP_H_
Lee Leahy77ff0b12015-05-05 15:07:29 -070020
Lee Leahy77ff0b12015-05-05 15:07:29 -070021/*
22 * Memory Mapped IO bases.
23 */
24
25/* PCI Configuration Space */
26#define MCFG_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS
27#define MCFG_BASE_SIZE 0x10000000
28
29/* Transactions in this range will abort */
30#define ABORT_BASE_ADDRESS 0xfeb00000
31#define ABORT_BASE_SIZE 0x00100000
32
33/* Power Management Controller */
34#define PMC_BASE_ADDRESS 0xfed03000
35#define PMC_BASE_SIZE 0x400
36
37/* IO Memory */
Lee Leahy32471722015-04-20 15:20:28 -070038#define IO_BASE_ADDRESS 0xfed80000
Frans Hendriks624195e2018-10-31 13:50:10 +010039#define IO_BASE_SIZE 0x40000
Lee Leahy32471722015-04-20 15:20:28 -070040#define COMMUNITY_OFFSET_GPSOUTHWEST 0x00000
41#define COMMUNITY_OFFSET_GPNORTH 0x08000
42#define COMMUNITY_OFFSET_GPEAST 0x10000
43#define COMMUNITY_OFFSET_GPSOUTHEAST 0x18000
Lee Leahy77ff0b12015-05-05 15:07:29 -070044
45/* Intel Legacy Block */
46#define ILB_BASE_ADDRESS 0xfed08000
Frans Hendriks624195e2018-10-31 13:50:10 +010047#define ILB_BASE_SIZE 0x2000
Lee Leahy77ff0b12015-05-05 15:07:29 -070048
49/* SPI Bus */
50#define SPI_BASE_ADDRESS 0xfed01000
51#define SPI_BASE_SIZE 0x400
52
53/* MODPHY */
Lee Leahy32471722015-04-20 15:20:28 -070054#define MPHY_BASE_ADDRESS 0xfea00000
Lee Leahy77ff0b12015-05-05 15:07:29 -070055#define MPHY_BASE_SIZE 0x100000
56
57/* Power Management Unit */
Lee Leahy32471722015-04-20 15:20:28 -070058#define PUNIT_BASE_ADDRESS 0xfed06000
Lee Leahy77ff0b12015-05-05 15:07:29 -070059#define PUNIT_BASE_SIZE 0x800
60
61/* Root Complex Base Address */
62#define RCBA_BASE_ADDRESS 0xfed1c000
63#define RCBA_BASE_SIZE 0x400
64
65/* High Performance Event Timer */
66#define HPET_BASE_ADDRESS 0xfed00000
67#define HPET_BASE_SIZE 0x400
68
69/* Temporary Base Address */
70#define TEMP_BASE_ADDRESS 0xfd000000
71
72/*
73 * IO Port bases.
74 */
75#define ACPI_BASE_ADDRESS 0x0400
76#define ACPI_BASE_SIZE 0x80
77
78#define GPIO_BASE_ADDRESS 0x0500
79#define GPIO_BASE_SIZE 0x100
80
81#define SMBUS_BASE_ADDRESS 0xefa0
82
83#ifndef __ACPI__
Elyes HAOUASdfbe6bd2018-10-29 06:56:52 +010084#include <stdint.h>
85
Lee Leahy77ff0b12015-05-05 15:07:29 -070086/* Read Top of Low Memory (BMBOUND) */
87uint32_t nc_read_top_of_low_memory(void);
88#endif
89
Lee Leahy32471722015-04-20 15:20:28 -070090#endif /* _SOC_IOMAP_H_ */