blob: 2240ae1e4b024a5c148e751f77ee9fbbcb1e2ddb [file] [log] [blame]
Lee Leahy77ff0b12015-05-05 15:07:29 -07001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2013 Google Inc.
Lee Leahy32471722015-04-20 15:20:28 -07005 * Copyright (C) 2015 Intel Corp.
Lee Leahy77ff0b12015-05-05 15:07:29 -07006 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
Lee Leahy77ff0b12015-05-05 15:07:29 -070015 */
16
Lee Leahy32471722015-04-20 15:20:28 -070017#ifndef _SOC_GPIO_H_
18#define _SOC_GPIO_H_
Lee Leahy77ff0b12015-05-05 15:07:29 -070019
20#include <stdint.h>
Subrata Baniked7275f2015-08-22 10:36:41 +053021#include <soc/gpio_defs.h>
Lee Leahy77ff0b12015-05-05 15:07:29 -070022#include <soc/iomap.h>
23
Aaron Durbinb0f81512016-07-25 21:31:41 -050024#define CROS_GPIO_DEVICE_NAME "Braswell"
25
Lee Leahy32471722015-04-20 15:20:28 -070026#define COMMUNITY_SIZE 0x20000
Lee Leahy77ff0b12015-05-05 15:07:29 -070027
Lee Leahy32471722015-04-20 15:20:28 -070028#define COMMUNITY_GPSOUTHWEST_BASE \
29(IO_BASE_ADDRESS + COMMUNITY_OFFSET_GPSOUTHWEST)
Lee Leahy77ff0b12015-05-05 15:07:29 -070030
Lee Leahy32471722015-04-20 15:20:28 -070031#define COMMUNITY_GPNORTH_BASE \
32(IO_BASE_ADDRESS + COMMUNITY_OFFSET_GPNORTH)
33
34#define COMMUNITY_GPEAST_BASE \
35(IO_BASE_ADDRESS + COMMUNITY_OFFSET_GPEAST)
36
37#define COMMUNITY_GPSOUTHEAST_BASE \
38(IO_BASE_ADDRESS + COMMUNITY_OFFSET_GPSOUTHEAST)
39
40#define GPIO_COMMUNITY_COUNT 4
41#define GPIO_FAMILIES_MAX_PER_COMM 7
42#define GP_SOUTHWEST 0
43#define GP_NORTH 1
44#define GP_EAST 2
45#define GP_SOUTHEAST 3
46
47#define COMMUNITY_BASE(community) \
48(IO_BASE_ADDRESS + community * 0x8000)
49
50#define GP_READ_ACCESS_POLICY_BASE(community) \
51(COMMUNITY_BASE(community) + 0x000)
52
53#define GP_WRITE_ACCESS_POLICY_BASE(community) \
54(COMMUNITY_BASE(community) + 0x100)
55
56#define GP_WAKE_STATUS_REG_BASE(community) \
57(COMMUNITY_BASE(community) + 0x200)
58
59#define GP_WAKE_MASK_REG_BASE(community) \
60(COMMUNITY_BASE(community) + 0x280)
61
62#define GP_INT_STATUS_REG_BASE(community) \
63(COMMUNITY_BASE(community) + 0x300)
64
65#define GP_INT_MASK_REG_BASE(community) \
66(COMMUNITY_BASE(community) + 0x380)
67
68#define GP_FAMILY_RCOMP_CTRL(community, family) \
69(COMMUNITY_BASE(community) + 0x1080 + 0x80 * family)
70
71#define GP_FAMILY_RCOMP_OFFSET(community, family) \
72(COMMUNITY_BASE(community) + 0x1084 + 0x80 * family)
73
74#define GP_FAMILY_RCOMP_OVERRIDE(community, family) \
75(COMMUNITY_BASE(community) + 0x1088 + 0x80 * family)
76
77#define GP_FAMILY_RCOMP_VALUE(community, family) \
78(COMMUNITY_BASE(community) + 0x108C + 0x80 * family)
79
80#define GP_FAMILY_CONF_COMP(community, family) \
81(COMMUNITY_BASE(community) + 0x1090 + 0x80 * family)
82
83#define GP_FAMILY_CONF_REG(community, family) \
84(COMMUNITY_BASE(community) + 0x1094 + 0x80 * family)
85
86
87/* Value written into pad control reg 0 */
88#define PAD_CONTROL_REG0_TRISTATE (PAD_CONFIG0_DEFAULT|PAD_GPIOFG_HI_Z)
89
90/* Calculate the MMIO Address for specific GPIO pin
91 * control register pointed by index.
92 */
93#define FAMILY_NUMBER(gpio_pad) (gpio_pad / MAX_FAMILY_PAD_GPIO_NO)
94#define INTERNAL_PAD_NUM(gpio_pad) (gpio_pad % MAX_FAMILY_PAD_GPIO_NO)
95#define GPIO_OFFSET(gpio_pad) (FAMILY_PAD_REGS_OFF \
96 + (FAMILY_PAD_REGS_SIZE * FAMILY_NUMBER(gpio_pad) \
97 + (GPIO_REGS_SIZE * INTERNAL_PAD_NUM(gpio_pad))))
98
99/* Gpio to Pad mapping */
100#define SDMMC1_CMD_MMIO_OFFSET GPIO_OFFSET(23)
101#define SDMMC1_D0_MMIO_OFFSET GPIO_OFFSET(17)
102#define SDMMC1_D1_MMIO_OFFSET GPIO_OFFSET(24)
103#define SDMMC1_D2_MMIO_OFFSET GPIO_OFFSET(20)
104#define SDMMC1_D3_MMIO_OFFSET GPIO_OFFSET(26)
105#define MMC1_D4_SD_WE_MMIO_OFFSET GPIO_OFFSET(67)
106#define MMC1_D5_MMIO_OFFSET GPIO_OFFSET(65)
107#define MMC1_D6_MMIO_OFFSET GPIO_OFFSET(63)
108#define MMC1_D7_MMIO_OFFSET GPIO_OFFSET(68)
Shobhit Srivastava97f09c32015-08-10 11:48:23 +0530109#define MMC1_RCLK_OFFSET GPIO_OFFSET(69)
Lee Leahy32471722015-04-20 15:20:28 -0700110#define HV_DDI2_DDC_SDA_MMIO_OFFSET GPIO_OFFSET(62)
111#define HV_DDI2_DDC_SCL_MMIO_OFFSET GPIO_OFFSET(67)
Ravi Sarawadia5d98882015-08-11 14:06:15 -0700112#define CFIO_139_MMIO_OFFSET GPIO_OFFSET(64)
113#define CFIO_140_MMIO_OFFSET GPIO_OFFSET(67)
Lee Leahy32471722015-04-20 15:20:28 -0700114
115/* GPIO Security registers offset */
116#define GPIO_READ_ACCESS_POLICY_REG 0x0000
117#define GPIO_WRITE_ACCESS_POLICY_REG 0x0100
118#define GPIO_WAKE_STATUS_REG 0x0200
119#define GPIO_WAKE_MASK_REG0 0x0280
120#define GPIO_WAKE_MASK_REG1 0x0284
121#define GPIO_INTERRUPT_STATUS 0x0300
122#define GPIO_INTERRUPT_MASK 0x0380
123#define GPE0A_STS_REG 0x20
124#define GPE0A_EN_REG 0x28
125#define ALT_GPIO_SMI_REG 0x38
126#define GPIO_ROUT_REG 0x58
Lee Leahy77ff0b12015-05-05 15:07:29 -0700127
128/* Pad register offset */
129#define PAD_CONF0_REG 0x0
130#define PAD_CONF1_REG 0x4
131#define PAD_VAL_REG 0x8
132
Lee Leahy77ff0b12015-05-05 15:07:29 -0700133/* Some banks have no legacy GPIO interface */
134#define GP_LEGACY_BASE_NONE 0xFFFF
135
Lee Leahy77ff0b12015-05-05 15:07:29 -0700136/* Number of GPIOs in each bank */
Lee Leahy32471722015-04-20 15:20:28 -0700137#define GPNCORE_COUNT 27
138#define GPSCORE_COUNT 102
139#define GPSSUS_COUNT 44
Lee Leahy77ff0b12015-05-05 15:07:29 -0700140
Lee Leahy32471722015-04-20 15:20:28 -0700141#define GP_SOUTHWEST_COUNT 56
142#define GP_NORTH_COUNT 59
143#define GP_EAST_COUNT 24
144#define GP_SOUTHEAST_COUNT 55
Lee Leahy77ff0b12015-05-05 15:07:29 -0700145
Lee Leahy32471722015-04-20 15:20:28 -0700146/* General */
147#define GPIO_REGS_SIZE 8
148#define NA 0
149#define LOW 0
150#define HIGH 1
151#define MASK_WAKE 0
152#define UNMASK_WAKE 1
153#define GPE_CAPABLE 1
154#define GPE_CAPABLE_NONE 0
Lee Leahy77ff0b12015-05-05 15:07:29 -0700155
Lee Leahy32471722015-04-20 15:20:28 -0700156#define MAX_FAMILY_PAD_GPIO_NO 15
157#define FAMILY_PAD_REGS_OFF 0x4400
158#define FAMILY_PAD_REGS_SIZE 0x400
Lee Leahy77ff0b12015-05-05 15:07:29 -0700159
Lee Leahy32471722015-04-20 15:20:28 -0700160/* config0[31:28] - Interrupt Selection Interrupt Select */
161#define PAD_INT_SEL(int_s) (int_s << 28)
Lee Leahy77ff0b12015-05-05 15:07:29 -0700162
Lee Leahy32471722015-04-20 15:20:28 -0700163/* config0[27:26] - Glitch Filter Config */
164#define PAD_GFCFG(glitch_cfg) (glitch_cfg << 26)
165#define PAD_GFCFG_DISABLE (0 << 26)
166#define PAD_ENABLE_EDGE_DETECTION (1 << 26) /* EDGE DETECTION ONLY */
167#define PAD_ENABLE_RX_DETECTION (2 << 26) /* RX DETECTION ONLY */
168#define PAD_ENABLE_EDGE_RX_DETECTION (3 << 26) /* RX & EDGE DETECTION */
Lee Leahy77ff0b12015-05-05 15:07:29 -0700169
Lee Leahy32471722015-04-20 15:20:28 -0700170/* config0[25:24] - RX/TX Enable Config */
171#define PAD_FUNC_CTRL(tx_rx_enable) (tx_rx_enable << 24)
172#define PAD_FUNC_CTRL_RX_TX_ENABLE (0 << 24)
173#define PAD_FUNC_CTRL_TX_ENABLE_RX_DISABLE (1 << 24)
174#define PAD_FUNC_CTRL_TX_ENABLE_RX_ENABLE (2 << 24)
175#define PAD_TX_RX_ENABLE (3 << 24)
Lee Leahy77ff0b12015-05-05 15:07:29 -0700176
Lee Leahy32471722015-04-20 15:20:28 -0700177/* config0[23:20] - Termination */
178#define PAD_PULL(TERM) (TERM << 20)
179#define PAD_PULL_DISABLE (0 << 20)
180#define PAD_PULL_DOWN_20K (1 << 20)
181#define PAD_PULL_DOWN_5K (2 << 20)
182#define PAD_PULL_DOWN_1K (4 << 20)
183#define PAD_PULL_UP_20K (9 << 20)
184#define PAD_PULL_UP_5K (10 << 20)
185#define PAD_PULL_UP_1K (12 << 20)
Lee Leahy77ff0b12015-05-05 15:07:29 -0700186
Lee Leahy32471722015-04-20 15:20:28 -0700187/* config0[19:16] - PAD Mode */
188#define PAD_MODE_SELECTION(MODE_SEL) (MODE_SEL<<16)
Lee Leahy77ff0b12015-05-05 15:07:29 -0700189
Lee Leahy32471722015-04-20 15:20:28 -0700190#define SET_PAD_MODE_SELECTION(pad_config, mode) \
191 ((pad_config & 0xfff0ffff) | PAD_MODE_SELECTION(mode))
Lee Leahy77ff0b12015-05-05 15:07:29 -0700192
Lee Leahy32471722015-04-20 15:20:28 -0700193/* config0[15] - GPIO Enable */
194#define PAD_GPIO_DISABLE (0 << 15)
195#define PAD_GPIO_ENABLE (1 << 15)
Lee Leahy77ff0b12015-05-05 15:07:29 -0700196
Lee Leahy32471722015-04-20 15:20:28 -0700197/* config0[14:11] - Reserver2 */
Lee Leahy77ff0b12015-05-05 15:07:29 -0700198
Lee Leahy32471722015-04-20 15:20:28 -0700199/* config0[10:8] - GPIO Config */
200#define PAD_GPIO_CFG(gpio_cfg) (gpio_cfg << 8)
201#define PAD_GPIOFG_GPIO (0 << 8)
202#define PAD_GPIOFG_GPO (1 << 8)
203#define PAD_GPIOFG_GPI (2 << 8)
204#define PAD_GPIOFG_HI_Z (3 << 8)
Lee Leahy77ff0b12015-05-05 15:07:29 -0700205
Lee Leahy32471722015-04-20 15:20:28 -0700206/* config0[7] - Gpio Light Mode Bar */
207/* config0[6:2] - Reserved1 */
208/* config0[1] - GPIO TX State */
209#define PAD_DEFAULT_TX(STATE) (STATE<<1)
210/* config0[0] - GPIO RX State */
211#define PAD_RX_BIT 1
Lee Leahy77ff0b12015-05-05 15:07:29 -0700212
Lee Leahy32471722015-04-20 15:20:28 -0700213/* Pad Control Register 1 configuration */
214#define PAD_DISABLE_INT (0 << 0)
215#define PAD_TRIG_EDGE_LOW (1 << 0)
216#define PAD_TRIG_EDGE_HIGH (2 << 0)
217#define PAD_TRIG_EDGE_BOTH (3 << 0)
218#define PAD_TRIG_EDGE_LEVEL (4 << 0)
Lee Leahy77ff0b12015-05-05 15:07:29 -0700219
Lee Leahy32471722015-04-20 15:20:28 -0700220/* Pad config0 power-on values */
221#define PAD_CONFIG0_DEFAULT 0x00010300
222#define PAD_CONFIG0_DEFAULT0 0x00910300
223#define PAD_CONFIG0_DEFAULT1 0x00110300
224#define PAD_CONFIG0_GPI_DEFAULT 0x00010200
Lee Leahy77ff0b12015-05-05 15:07:29 -0700225
Lee Leahy32471722015-04-20 15:20:28 -0700226/* Pad config1 reg power-on values */
227#define PAD_CONFIG1_DEFAULT0 0x05C00000
228#define PAD_CONFIG1_CSEN 0x0DC00000
229#define PAD_CONFIG1_DEFAULT1 0x05C00020
Lee Leahy77ff0b12015-05-05 15:07:29 -0700230
Lee Leahy32471722015-04-20 15:20:28 -0700231#define GPIO_INPUT_NO_PULL \
232 { .pad_conf0 = PAD_PULL_DISABLE | PAD_GPIO_ENABLE \
233 | PAD_CONFIG0_GPI_DEFAULT, \
234 .pad_conf1 = PAD_CONFIG1_DEFAULT0 }
Lee Leahy77ff0b12015-05-05 15:07:29 -0700235
236#define GPIO_INPUT_PU_20K \
Lee Leahy32471722015-04-20 15:20:28 -0700237 { .pad_conf0 = PAD_PULL_UP_20K | PAD_GPIO_ENABLE \
238 | PAD_CONFIG0_GPI_DEFAULT, \
239 .pad_conf1 = PAD_CONFIG1_DEFAULT0 }
Lee Leahy77ff0b12015-05-05 15:07:29 -0700240
Subrata Baniked7275f2015-08-22 10:36:41 +0530241#define GPIO_INPUT_PD_5K \
242 { .pad_conf0 = PAD_PULL_DOWN_5K | PAD_GPIO_ENABLE \
243 | PAD_CONFIG0_GPI_DEFAULT, \
244 .pad_conf1 = PAD_CONFIG1_DEFAULT0 }
245
246#define GPIO_INPUT_PD_20K \
247 { .pad_conf0 = PAD_PULL_DOWN_20K | PAD_GPIO_ENABLE \
248 | PAD_CONFIG0_GPI_DEFAULT, \
249 .pad_conf1 = PAD_CONFIG1_DEFAULT0 }
250
Lee Leahy32471722015-04-20 15:20:28 -0700251#define GPIO_INPUT_PU_5K \
252 { .pad_conf0 = PAD_PULL_UP_5K | PAD_GPIO_ENABLE \
253 | PAD_CONFIG0_GPI_DEFAULT, \
254 .pad_conf1 = PAD_CONFIG1_DEFAULT0 }
Lee Leahy77ff0b12015-05-05 15:07:29 -0700255
Lee Leahy32471722015-04-20 15:20:28 -0700256#define GPI(int_type, int_sel, term, int_msk, glitch_cfg, wake_msk, gpe_val) { \
257 .pad_conf0 = PAD_INT_SEL(int_sel) | PAD_GFCFG(glitch_cfg) \
258 | PAD_PULL(term) | PAD_GPIO_ENABLE | PAD_GPIOFG_GPI, \
259 .pad_conf1 = int_type << 0 | PAD_CONFIG1_DEFAULT0, \
260 .wake_mask = wake_msk, \
261 .int_mask = int_msk, \
262 .gpe = gpe_val }
Lee Leahy77ff0b12015-05-05 15:07:29 -0700263
Lee Leahy32471722015-04-20 15:20:28 -0700264#define GPO_FUNC(term, tx_state) {\
265 .pad_conf0 = PAD_GPIO_ENABLE | PAD_GPIOFG_GPO | PAD_PULL(term) \
266 | tx_state << 1, \
267 .pad_conf1 = PAD_CONFIG1_DEFAULT0 }
Lee Leahy77ff0b12015-05-05 15:07:29 -0700268
Lee Leahy32471722015-04-20 15:20:28 -0700269#define NATIVE_FUNC(mode, term, inv_rx_tx) {\
270 .pad_conf0 = PAD_GPIO_DISABLE | PAD_GPIOFG_HI_Z \
271 | PAD_MODE_SELECTION(mode) | PAD_PULL(term),\
272 .pad_conf1 = PAD_CONFIG1_DEFAULT0 | inv_rx_tx << 4 }
Lee Leahy77ff0b12015-05-05 15:07:29 -0700273
Lee Leahy32471722015-04-20 15:20:28 -0700274#define NATIVE_FUNC_TX_RX(tx_rx_enable, mode, term, inv_rx_tx) {\
275 .pad_conf0 = PAD_FUNC_CTRL(tx_rx_enable) | PAD_GPIO_DISABLE \
276 | PAD_GPIOFG_GPIO | PAD_MODE_SELECTION(mode) \
277 | PAD_PULL(term),\
278 .pad_conf1 = PAD_CONFIG1_DEFAULT0 | inv_rx_tx << 4 }
Lee Leahy77ff0b12015-05-05 15:07:29 -0700279
Lee Leahy32471722015-04-20 15:20:28 -0700280#define NATIVE_FUNC_CSEN(mode, term, inv_rx_tx) {\
281 .pad_conf0 = PAD_GPIO_DISABLE | PAD_GPIOFG_HI_Z \
282 | PAD_MODE_SELECTION(mode) | PAD_PULL(term),\
283 .pad_conf1 = PAD_CONFIG1_CSEN | inv_rx_tx << 4 }
Lee Leahy77ff0b12015-05-05 15:07:29 -0700284
Lee Leahy32471722015-04-20 15:20:28 -0700285#define NATIVE_INT(mode, int_sel) {\
286 .pad_conf0 = PAD_INT_SEL(int_sel) | PAD_GPIO_DISABLE \
287 | PAD_GPIOFG_HI_Z | PAD_MODE_SELECTION(mode),\
288 .pad_conf1 = PAD_CONFIG1_DEFAULT0 }
Lee Leahy77ff0b12015-05-05 15:07:29 -0700289
Hannah Williamsfc5489f2016-01-19 11:58:58 -0800290#define NATIVE_INT_PU20K(mode, int_sel) {\
291 .pad_conf0 = PAD_PULL_UP_20K | PAD_INT_SEL(int_sel) | PAD_GPIO_DISABLE \
292 | PAD_GPIOFG_HI_Z | PAD_MODE_SELECTION(mode),\
293 .pad_conf1 = PAD_CONFIG1_DEFAULT0 }
294
Lee Leahy32471722015-04-20 15:20:28 -0700295#define SPEAKER \
296{ .pad_conf0 = PAD_CONFIG0_DEFAULT0, \
297 .pad_conf1 = PAD_CONFIG1_DEFAULT0 }
Lee Leahy77ff0b12015-05-05 15:07:29 -0700298
Lee Leahy32471722015-04-20 15:20:28 -0700299#define SPARE_PIN\
300 { .pad_conf0 = 0x00110300,\
301 .pad_conf1 = PAD_CONFIG1_DEFAULT0 }
Lee Leahy77ff0b12015-05-05 15:07:29 -0700302
Lee Leahy32471722015-04-20 15:20:28 -0700303/* SCI , SMI, Wake */
304#define GPIO_SCI(int_sel) \
305 { .pad_conf0 = PAD_PULL_DISABLE | PAD_ENABLE_EDGE_RX_DETECTION\
306 | PAD_GPIO_ENABLE | PAD_GPIOFG_GPI \
307 | PAD_INT_SEL(int_sel), \
308 .pad_conf1 = PAD_TRIG_EDGE_LOW | PAD_CONFIG1_DEFAULT0, \
309 .gpe = SCI, \
310 .int_mask = 1 }
Lee Leahy77ff0b12015-05-05 15:07:29 -0700311
Lee Leahy32471722015-04-20 15:20:28 -0700312#define GPIO_WAKE(int_sel) \
313 { .pad_conf0 = PAD_PULL_DISABLE | PAD_ENABLE_EDGE_RX_DETECTION\
314 | PAD_GPIO_ENABLE | PAD_GPIOFG_GPI \
315 | PAD_INT_SEL(int_sel), \
316 .pad_conf1 = PAD_TRIG_EDGE_LOW | PAD_CONFIG1_DEFAULT0, \
Lee Leahy6598b912017-03-16 17:30:09 -0700317 .int_mask = 1,\
Lee Leahy32471722015-04-20 15:20:28 -0700318 .wake_mask = 1 }
Lee Leahy77ff0b12015-05-05 15:07:29 -0700319
Lee Leahy32471722015-04-20 15:20:28 -0700320#define GPIO_SMI(int_sel) \
321 { .pad_conf0 = PAD_PULL_DISABLE | PAD_ENABLE_EDGE_RX_DETECTION\
322 | PAD_GPIO_ENABLE | PAD_GPIOFG_GPI \
323 | PAD_INT_SEL(int_sel), \
324 .pad_conf1 = PAD_TRIG_EDGE_LOW | PAD_CONFIG1_DEFAULT0, \
325 .int_mask = 1,\
326 .gpe = SMI }
Lee Leahy77ff0b12015-05-05 15:07:29 -0700327
Lee Leahy32471722015-04-20 15:20:28 -0700328#define GPIO_SKIP { .skip_config = 1 }
Lee Leahy77ff0b12015-05-05 15:07:29 -0700329
Lee Leahy32471722015-04-20 15:20:28 -0700330/* Common GPIO settings */
331#define NATIVE_DEFAULT(mode) NATIVE_FUNC(mode, 0, 0) /* no pull */
332#define NATIVE_PU20K(mode) NATIVE_FUNC(mode, 9, 0) /* PH 20k */
333#define NATIVE_PU5K(mode) NATIVE_FUNC(mode, 10, 0) /* PH 5k */
334#define NATIVE_PU5K_INVTX(mode) NATIVE_FUNC(mode, 10, inv_tx_enable) /* PH 5k */
335#define NATIVE_PU1K(mode) NATIVE_FUNC(mode, 12, 0) /* PH 1k */
336#define NATIVE_PU1K_CSEN_INVTX(mode) \
337 NATIVE_FUNC_CSEN(mode, 12, inv_tx_enable) /* PH 1k */
338#define NATIVE_PU1K_INVTX(mode) NATIVE_FUNC(mode, 12, inv_tx_enable) /* PH 1k */
339#define NATIVE_PD20K(mode) NATIVE_FUNC(mode, 1, 0) /* PD 20k */
340#define NATIVE_PD5K(mode) NATIVE_FUNC(mode, 2, 0) /* PD 5k */
341#define NATIVE_PD1K(mode) NATIVE_FUNC(mode, 4, 0) /* PD 1k */
342#define NATIVE_PD1K_CSEN_INVTX(mode) NATIVE_FUNC_CSEN(mode, 4, inv_tx_enable)
343 /* no pull */
344#define NATIVE_TX_RX_EN NATIVE_FUNC_TX_RX(3, 1, 0, inv_tx_enable)
345#define NATIVE_TX_RX_M1 NATIVE_FUNC_TX_RX(0, 1, 0, 0) /* no pull */
346#define NATIVE_TX_RX_M3 NATIVE_FUNC_TX_RX(0, 3, 0, 0) /* no pull */
347#define NATIVE_PU1K_M1 NATIVE_PU1K(1) /* PU1k M1 */
Lee Leahy77ff0b12015-05-05 15:07:29 -0700348
Lee Leahy32471722015-04-20 15:20:28 -0700349/* Default native functions */
350#define Native_M0 NATIVE_DEFAULT(0)
351#define Native_M1 NATIVE_DEFAULT(1)
352#define Native_M2 NATIVE_DEFAULT(2)
353#define Native_M3 NATIVE_DEFAULT(3)
354#define Native_M4 NATIVE_DEFAULT(4)
355#define Native_M5 NATIVE_DEFAULT(5)
356#define Native_M6 NATIVE_DEFAULT(6)
357#define Native_M7 NATIVE_DEFAULT(7)
358#define Native_M8 NATIVE_DEFAULT(8)
Lee Leahy77ff0b12015-05-05 15:07:29 -0700359
Lee Leahy32471722015-04-20 15:20:28 -0700360#define GPIO_OUT_LOW GPO_FUNC(0, 0) /* gpo low */
361#define GPIO_OUT_HIGH GPO_FUNC(0, 1) /* gpo high */
362#define GPIO_NC GPIO_INPUT_PU_20K /* not connect */
Lee Leahy77ff0b12015-05-05 15:07:29 -0700363
364/* End marker */
365#define GPIO_LIST_END 0xffffffff
366
367#define GPIO_END \
368 { .pad_conf0 = GPIO_LIST_END }
369
Lee Leahy77ff0b12015-05-05 15:07:29 -0700370/* 16 DirectIRQs per supported bank */
Lee Leahy32471722015-04-20 15:20:28 -0700371#define GPIO_MAX_DIRQS 16
Lee Leahy77ff0b12015-05-05 15:07:29 -0700372
Lee Leahy32471722015-04-20 15:20:28 -0700373#define GPIO_NONE 255
374
375/* Functions / defines for changing GPIOs in romstage */
376/* SCORE Pad definitions. */
377#define UART_RXD_PAD 82
378#define UART_TXD_PAD 83
379#define PCU_SMB_CLK_PAD 88
380#define PCU_SMB_DATA_PAD 90
381#define SOC_DDI1_VDDEN_PAD 16
382#define UART1_RXD_PAD 9
383#define UART1_TXD_PAD 13
384#define DDI2_DDC_SCL 48
385#define DDI2_DDC_SDA 53
Lee Leahy77ff0b12015-05-05 15:07:29 -0700386
387struct soc_gpio_map {
388 u32 pad_conf0;
389 u32 pad_conf1;
390 u32 pad_val;
Lee Leahy32471722015-04-20 15:20:28 -0700391 u32 gpe;
392 u32 int_mask:1;
393 u32 wake_mask:1;
394 u32 is_gpio:1;
395 u32 skip_config:1;
Stefan Reinauer6a001132017-07-13 02:20:27 +0200396} __packed;
Lee Leahy77ff0b12015-05-05 15:07:29 -0700397
398struct soc_gpio_config {
Lee Leahy32471722015-04-20 15:20:28 -0700399 const struct soc_gpio_map *north;
400 const struct soc_gpio_map *southeast;
401 const struct soc_gpio_map *southwest;
402 const struct soc_gpio_map *east;
Lee Leahy77ff0b12015-05-05 15:07:29 -0700403};
404
Lee Leahy32471722015-04-20 15:20:28 -0700405/* Description of a GPIO 'community' */
Lee Leahy77ff0b12015-05-05 15:07:29 -0700406struct gpio_bank {
407 const int gpio_count;
Lee Leahy32471722015-04-20 15:20:28 -0700408 const u8 *gpio_to_pad;
Lee Leahy77ff0b12015-05-05 15:07:29 -0700409 const int legacy_base;
410 const unsigned long pad_base;
Lee Leahy32471722015-04-20 15:20:28 -0700411 const u8 has_gpe_en:1;
412 const u8 has_wake_en:1;
Lee Leahy77ff0b12015-05-05 15:07:29 -0700413};
414
Lee Leahy32471722015-04-20 15:20:28 -0700415typedef enum {
416 NATIVE = 0xff,
417 GPIO = 0, /* Native, no need to set PAD_VALUE */
418 GPO = 1, /* GPI, input only in PAD_VALUE */
419 GPI = 2, /* GPO, output only in PAD_VALUE */
420 HI_Z = 3,
421 NA_GPO = 0,
422} gpio_en_t;
423
424typedef enum {
425 LO = 0,
426 HI = 1,
427} gpo_d4_t;
428
429typedef enum {
430 F0 = 0,
431 F1 = 1,
432 F2 = 2,
433 F3 = 3
434} gpio_func_num_t;
435
436typedef enum {
437 _CAP = 1,
438 _NOT_CAP = 0
439} int_capable_t;
440
441typedef enum {
442 P_NONE = 0, /* Pull None */
443 P_20K_L = 1, /* Pull Down 20K */
444 P_5K_L = 2, /* Pull Down 5K */
445 P_1K_L = 4, /* Pull Down 1K */
446 P_20K_H = 9, /* Pull Up 20K */
447 P_5K_H = 10, /* Pull Up 5K */
448 P_1K_H = 12 /* Pull Up 1K */
449} pull_type_t;
450
451typedef enum {
452 DISABLE = 0, /* Disable */
453 ENABLE = 1, /* Enable */
454} park_mode_enb_t;
455
456typedef enum {
457 VOLT_3_3 = 0, /* Working on 3.3 Volts */
458 VOLT_1_8 = 1, /* Working on 1.8 Volts */
459} voltage_t;
460
461typedef enum {
462 DISABLE_HS = 0, /* Disable high speed mode */
463 ENABLE_HS = 1, /* Enable high speed mode */
464} hs_mode_t;
465
466typedef enum {
467 PULL_UP = 0, /* On Die Termination Up */
468 PULL_DOWN = 1, /* On Die Termination Down */
469} odt_up_dn_t;
470
471typedef enum {
472 DISABLE_OD = 0, /* On Die Termination Disable */
473 ENABLE_OD = 1, /* On Die Termination Enable */
474} odt_en_t;
475
476typedef enum {
477 ONE_BIT = 1,
478 TWO_BIT = 3,
479 THREE_BIT = 7,
480 FOUR_BIT = 15,
481 FIVE_BIT = 31,
482 SIX_BIT = 63,
483 SEVEN_BIT = 127,
484 EIGHT_BIT = 255
485} bit_t;
486
487typedef enum {
488 M0 = 0,
489 M1,
490 M2,
491 M3,
492 M4,
493 M5,
494 M6,
495 M7,
496 M8,
497 M9,
498 M10,
499 M11,
500 M12,
501 M13,
502} mode_list_t;
503
504typedef enum {
505 L0 = 0,
506 L1 = 1,
507 L2 = 2,
508 L3 = 3,
509 L4 = 4,
510 L5 = 5,
511 L6 = 6,
512 L7 = 7,
513 L8 = 8,
514 L9 = 9,
515 L10 = 10,
516 L11 = 11,
517 L12 = 12,
518 L13 = 13,
519 L14 = 14,
520 L15 = 15,
521} int_select_t;
522
523typedef enum {
524 INT_DIS = 0,
Matt DeVillier73b723d2018-07-31 16:41:06 -0500525 trig_edge_low = PAD_TRIG_EDGE_LOW,
526 trig_edge_high = PAD_TRIG_EDGE_HIGH,
527 trig_edge_both = PAD_TRIG_EDGE_BOTH,
528 trig_level_high = PAD_TRIG_EDGE_LEVEL | (0 << 4),
529 trig_level_low = PAD_TRIG_EDGE_LEVEL | (4 << 4),
Lee Leahy32471722015-04-20 15:20:28 -0700530} int_type_t;
531
532typedef enum {
533 glitch_disable = 0,
534 en_edge_detect,
535 en_rx_data,
536 en_edge_rx_data,
537} glitch_cfg;
538
539typedef enum {
540 maskable = 0,
541 non_maskable,
542} mask_t;
543
544typedef enum {
545 GPE = 0,
546 SMI,
547 SCI,
548} gpe_config_t;
549
550/*
551 * InvertRxTx 7:4
552 * 0 - No Inversion
553 * 1 - Inversion
554 * [0] RX Enable
555 * [1] TX Enable
556 * [2] RX Data
557 * [3] TX Data
558 */
559typedef enum {
560 no_inversion = 0,
561 inv_rx_enable = 0x1,
562 inv_tx_enable = 0x2,
563 inv_rx_tx_enable = 0x3,
564 inv_rx_data = 0x4,
565 inv_tx_data = 0x8,
566} invert_rx_tx_t;
567
568#define PAD_VAL_HIGH (1 << 0)
569
Lee Leahy77ff0b12015-05-05 15:07:29 -0700570void setup_soc_gpios(struct soc_gpio_config *config, u8 enable_xdp_tap);
Lee Leahy32471722015-04-20 15:20:28 -0700571struct soc_gpio_config *mainboard_get_gpios(void);
Lee Leahy77ff0b12015-05-05 15:07:29 -0700572
573static inline void ncore_select_func(int pad, int func)
574{
Lee Leahy77ff0b12015-05-05 15:07:29 -0700575
Lee Leahy77ff0b12015-05-05 15:07:29 -0700576}
577
578/* These functions require that the input pad be configured as an input GPIO */
Lee Leahy77ff0b12015-05-05 15:07:29 -0700579
580static inline int ssus_get_gpio(int pad)
581{
Lee Leahy32471722015-04-20 15:20:28 -0700582 return 0;
Lee Leahy77ff0b12015-05-05 15:07:29 -0700583}
584
585static inline void ssus_disable_internal_pull(int pad)
586{
Lee Leahy77ff0b12015-05-05 15:07:29 -0700587}
588
Subrata Baniked7275f2015-08-22 10:36:41 +0530589typedef int gpio_t;
590
Lee Leahy32471722015-04-20 15:20:28 -0700591int get_gpio(int community_base, int pad0_offset);
592uint16_t gpio_family_number(uint8_t community, uint8_t pad);
593uint32_t *gpio_pad_config_reg(uint8_t community, uint8_t pad);
594
Lee Leahyacb9c0b2015-07-02 11:55:18 -0700595void lpc_init(void);
596void lpc_set_low_power(void);
597
Lee Leahy32471722015-04-20 15:20:28 -0700598#endif /* _SOC_GPIO_H_ */