| Joseph Lo | c4301f7 | 2015-04-14 16:03:58 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. |
| 3 | * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved |
| 4 | * |
| 5 | * Redistribution and use in source and binary forms, with or without |
| 6 | * modification, are permitted provided that the following conditions are met: |
| 7 | * |
| 8 | * Redistributions of source code must retain the above copyright notice, this |
| 9 | * list of conditions and the following disclaimer. |
| 10 | * |
| 11 | * Redistributions in binary form must reproduce the above copyright notice, |
| 12 | * this list of conditions and the following disclaimer in the documentation |
| 13 | * and/or other materials provided with the distribution. |
| 14 | * |
| 15 | * Neither the name of ARM nor the names of its contributors may be used |
| 16 | * to endorse or promote products derived from this software without specific |
| 17 | * prior written permission. |
| 18 | * |
| 19 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 20 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 21 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 22 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 23 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 24 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 25 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 26 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 27 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 28 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 29 | * POSSIBILITY OF SUCH DAMAGE. |
| 30 | */ |
| 31 | |
| 32 | #include <arch/asm.h> |
| 33 | #include <arch/cache_helpers.h> |
| 34 | |
| 35 | /* --------------------------------------------------------------- |
| 36 | * Data cache operations by set/way to the level specified |
| 37 | * |
| 38 | * The main function, do_dcsw_op requires: |
| 39 | * x0: The operation type (0-2), as defined in cache_helpers.h |
| 40 | * x3: The last cache level to operate on |
| 41 | * x9: clidr_el1 |
| 42 | * and will carry out the operation on each data cache from level 0 |
| 43 | * to the level in x3 in sequence |
| 44 | * |
| 45 | * The dcsw_op macro sets up the x3 and x9 parameters based on |
| 46 | * clidr_el1 cache information before invoking the main function |
| 47 | * --------------------------------------------------------------- |
| 48 | */ |
| 49 | |
| 50 | .macro dcsw_op shift, fw, ls |
| 51 | mrs x9, clidr_el1 |
| 52 | ubfx x3, x9, \shift, \fw |
| 53 | lsl x3, x3, \ls |
| 54 | b do_dcsw_op |
| 55 | .endm |
| 56 | |
| 57 | do_dcsw_op: |
| 58 | cbz x3, exit |
| 59 | mov x10, xzr |
| 60 | adr x14, dcsw_loop_table // compute inner loop address |
| 61 | add x14, x14, x0, lsl #5 // inner loop is 8x32-bit instructions |
| 62 | mov x0, x9 |
| 63 | mov w8, #1 |
| 64 | loop1: |
| 65 | add x2, x10, x10, lsr #1 // work out 3x current cache level |
| 66 | lsr x1, x0, x2 // extract cache type bits from clidr |
| 67 | and x1, x1, #7 // mask the bits for current cache only |
| 68 | cmp x1, #2 // see what cache we have at this level |
| 69 | b.lt level_done // nothing to do if no cache or icache |
| 70 | |
| 71 | msr csselr_el1, x10 // select current cache level in csselr |
| 72 | isb // isb to sych the new cssr&csidr |
| 73 | mrs x1, ccsidr_el1 // read the new ccsidr |
| 74 | and x2, x1, #7 // extract the length of the cache lines |
| 75 | add x2, x2, #4 // add 4 (line length offset) |
| 76 | ubfx x4, x1, #3, #10 // maximum way number |
| 77 | clz w5, w4 // bit position of way size increment |
| 78 | lsl w9, w4, w5 // w9 = aligned max way number |
| 79 | lsl w16, w8, w5 // w16 = way number loop decrement |
| 80 | orr w9, w10, w9 // w9 = combine way and cache number |
| 81 | ubfx w6, w1, #13, #15 // w6 = max set number |
| 82 | lsl w17, w8, w2 // w17 = set number loop decrement |
| 83 | dsb sy // barrier before we start this level |
| 84 | br x14 // jump to DC operation specific loop |
| 85 | |
| 86 | level_done: |
| 87 | add x10, x10, #2 // increment cache number |
| 88 | cmp x3, x10 |
| 89 | b.gt loop1 |
| 90 | msr csselr_el1, xzr // select cache level 0 in csselr |
| 91 | dsb sy // barrier to complete final cache operation |
| 92 | isb |
| 93 | exit: |
| 94 | ret |
| 95 | |
| 96 | .macro dcsw_loop _op |
| 97 | loop2_\_op: |
| 98 | lsl w7, w6, w2 // w7 = aligned max set number |
| 99 | |
| 100 | loop3_\_op: |
| 101 | orr w11, w9, w7 // combine cache, way and set number |
| 102 | dc \_op, x11 |
| 103 | subs w7, w7, w17 // decrement set number |
| 104 | b.ge loop3_\_op |
| 105 | |
| 106 | subs x9, x9, x16 // decrement way number |
| 107 | b.ge loop2_\_op |
| 108 | |
| 109 | b level_done |
| 110 | .endm |
| 111 | |
| 112 | dcsw_loop_table: |
| 113 | dcsw_loop isw |
| 114 | dcsw_loop cisw |
| 115 | dcsw_loop csw |
| 116 | |
| 117 | ENTRY(flush_dcache_louis) |
| 118 | dcsw_op #LOUIS_SHIFT, #CLIDR_FIELD_WIDTH, #LEVEL_SHIFT |
| 119 | ENDPROC(flush_dcache_louis) |
| 120 | |
| 121 | ENTRY(flush_dcache_all) |
| 122 | dcsw_op #LOC_SHIFT, #CLIDR_FIELD_WIDTH, #LEVEL_SHIFT |
| 123 | ENDPROC(flush_dcache_all) |