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Lijian Zhaoe391cbf2018-07-24 17:46:20 -07001chip soc/intel/cannonlake
2
3 device cpu_cluster 0 on
4 device lapic 0 on end
5 end
6
7 # FSP configuration
Ronak Kanabarab92f262019-01-28 13:32:31 +05308 register "SaGv" = "SaGv_Enabled"
Lijian Zhaoe391cbf2018-07-24 17:46:20 -07009 register "ScsEmmcHs400Enabled" = "1"
Lijian Zhaoe391cbf2018-07-24 17:46:20 -070010 register "HeciEnabled" = "1"
11
sridhar685b3772019-06-13 14:26:00 +053012 # Enable eDP device
13 register "DdiPortEdp" = "1"
14 # Enable HPD for DDI ports B/C/D/F
15 register "DdiPortBHpd" = "1"
16 register "DdiPortCHpd" = "1"
17 register "DdiPortDHpd" = "1"
18 register "DdiPortFHpd" = "1"
19 # Enable DDC for DDI ports B/C/D/F
20 register "DdiPortBDdc" = "1"
21 register "DdiPortCDdc" = "1"
22 register "DdiPortDDdc" = "1"
23 register "DdiPortFDdc" = "1"
24
Lijian Zhaoe391cbf2018-07-24 17:46:20 -070025 register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)"
26 register "usb2_ports[1]" = "USB2_PORT_MID(OC0)"
27 register "usb2_ports[2]" = "USB2_PORT_MID(OC0)"
28 register "usb2_ports[3]" = "USB2_PORT_MID(OC0)"
29 register "usb2_ports[4]" = "USB2_PORT_MID(OC0)"
30 register "usb2_ports[5]" = "USB2_PORT_MID(OC0)"
31 register "usb2_ports[6]" = "USB2_PORT_MID(OC0)"
32 register "usb2_ports[7]" = "USB2_PORT_MID(OC0)"
33 register "usb2_ports[8]" = "USB2_PORT_MID(OC0)"
34 register "usb2_ports[9]" = "USB2_PORT_MID(OC0)"
35
36 register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)"
37 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)"
38 register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)"
39 register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC0)"
40 register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)"
41 register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)"
42
Lijian Zhaoe391cbf2018-07-24 17:46:20 -070043 register "SataSalpSupport" = "1"
44 register "SataPortsEnable[0]" = "1"
45 register "SataPortsEnable[1]" = "1"
46 register "SataPortsEnable[2]" = "1"
47 register "SataPortsEnable[3]" = "1"
48 register "SataPortsEnable[4]" = "1"
49 register "SataPortsEnable[5]" = "1"
50 register "SataPortsEnable[6]" = "1"
51 register "SataPortsEnable[7]" = "1"
52
53 register "PchHdaDspEnable" = "1"
54 register "PchHdaAudioLinkHda" = "1"
55
56 register "PcieRpEnable[0]" = "1"
57 register "PcieRpEnable[1]" = "1"
58 register "PcieRpEnable[2]" = "1"
59 register "PcieRpEnable[3]" = "1"
60 register "PcieRpEnable[4]" = "1"
61 register "PcieRpEnable[5]" = "1"
62 register "PcieRpEnable[6]" = "1"
63 register "PcieRpEnable[7]" = "1"
64 register "PcieRpEnable[8]" = "1"
65 register "PcieRpEnable[9]" = "1"
66 register "PcieRpEnable[10]" = "1"
67 register "PcieRpEnable[11]" = "1"
68 register "PcieRpEnable[12]" = "1"
69 register "PcieRpEnable[13]" = "1"
70 register "PcieRpEnable[14]" = "1"
71 register "PcieRpEnable[15]" = "1"
72
73 register "PcieClkSrcUsage[0]" = "1"
74 register "PcieClkSrcUsage[1]" = "8"
75 register "PcieClkSrcUsage[2]" = "PCIE_CLK_LAN"
76 register "PcieClkSrcUsage[3]" = "13"
77 register "PcieClkSrcUsage[4]" = "4"
78 register "PcieClkSrcUsage[5]" = "14"
79
80 register "PcieClkSrcClkReq[0]" = "0"
81 register "PcieClkSrcClkReq[1]" = "1"
82 register "PcieClkSrcClkReq[2]" = "2"
83 register "PcieClkSrcClkReq[3]" = "3"
84 register "PcieClkSrcClkReq[4]" = "4"
85 register "PcieClkSrcClkReq[5]" = "5"
86
87 # Enable "Intel Speed Shift Technology"
88 register "speed_shift_enable" = "1"
89
90 # GPIO for SD card detect
91 register "sdcard_cd_gpio" = "GPP_G5"
92
93 device domain 0 on
94 device pci 00.0 on end # Host Bridge
95 device pci 02.0 on end # Integrated Graphics Device
96 device pci 04.0 on end # SA Thermal device
97 device pci 12.0 on end # Thermal Subsystem
98 device pci 12.5 off end # UFS SCS
99 device pci 12.6 off end # GSPI #2
100 device pci 14.0 on end # USB xHCI
101 device pci 14.1 off end # USB xDCI (OTG)
Subrata Banik69b18f02018-11-06 16:59:56 +0530102 chip drivers/intel/wifi
103 register "wake" = "PME_B0_EN_BIT"
104 device pci 14.3 on end # CNVi wifi
105 end
Lijian Zhaoe391cbf2018-07-24 17:46:20 -0700106 device pci 14.5 on end # SDCard
107 device pci 15.0 on end # I2C #0
108 device pci 15.1 on end # I2C #1
109 device pci 15.2 off end # I2C #2
110 device pci 15.3 off end # I2C #3
111 device pci 16.0 on end # Management Engine Interface 1
112 device pci 16.1 off end # Management Engine Interface 2
113 device pci 16.2 off end # Management Engine IDE-R
114 device pci 16.3 off end # Management Engine KT Redirection
115 device pci 16.4 off end # Management Engine Interface 3
116 device pci 16.5 off end # Management Engine Interface 4
117 device pci 17.0 on end # SATA
118 device pci 19.0 on end # I2C #4
119 device pci 19.1 off end # I2C #5
120 device pci 19.2 on end # UART #2
121 device pci 1a.0 on end # eMMC
122 device pci 1c.0 on end # PCI Express Port 1 x4 SLOT1
123 device pci 1c.4 on end # PCI Express Port 5 x1 SLOT2/LAN
124 device pci 1c.5 off end # PCI Express Port 6
125 device pci 1c.6 off end # PCI Express Port 7
126 device pci 1c.7 off end # PCI Express Port 8
127 device pci 1d.0 on end # PCI Express Port 9
128 device pci 1d.1 off end # PCI Express Port 10
129 device pci 1d.2 off end # PCI Express Port 11
130 device pci 1d.3 off end # PCI Express Port 12
131 device pci 1d.4 off end # PCI Express Port 13
132 device pci 1d.5 off end # PCI Express Port 14
133 device pci 1d.6 off end # PCI Express Port 15
134 device pci 1d.7 off end # PCI Express Port 16
135 device pci 1e.0 on end # UART #0
136 device pci 1e.1 off end # UART #1
137 device pci 1e.2 off end # GSPI #0
138 device pci 1e.3 off end # GSPI #1
139 device pci 1f.0 on
140 chip drivers/pc80/tpm
141 device pnp 0c31.0 on end
142 end
143 end # LPC Interface
144 device pci 1f.1 on end # P2SB
145 device pci 1f.2 on end # Power Management Controller
146 device pci 1f.3 on end # Intel HDA
147 device pci 1f.4 on end # SMBus
148 device pci 1f.5 on end # PCH SPI
Lijian Zhao0c392b32018-08-03 13:27:09 -0700149 device pci 1f.6 on end # GbE
Lijian Zhaoe391cbf2018-07-24 17:46:20 -0700150 end
151end