Blame - src/soc/intel/xeon_sp/spr/Kconfig - coreboot

blob: 0c60f8c2f7328c5e8dfe503b73f81ebe06834258 [file] [log] [blame]

Jonathan Zhang	9722f5f	2023-01-25 09:04:59 -0800	[diff] [blame]	1	## SPDX-License-Identifier: GPL-2.0-only
				2
				3	if SOC_INTEL_SAPPHIRERAPIDS_SP
				4
				5	config SOC_SPECIFIC_OPTIONS
				6	def_bool y
				7	select MICROCODE_BLOB_NOT_HOOKED_UP
				8	select SAVE_MRC_AFTER_FSPS
				9	select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION
				10
				11	config FSP_HEADER_PATH
				12	string "Location of FSP headers"
				13	depends on MAINBOARD_USES_FSP2_0
				14	default "src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp"
				15
				16	config MAX_CPUS
				17	int
				18	default 255
				19
				20	config MAX_SOCKET_UPD
				21	int
				22	default 2
				23	help
				24	This is used for configuring common SPR UPD tables which their sizes
				25	depend on the socket number. Since it's the maximal socket number for
				26	the common UPD tables, mainboard should not overwrite it.
				27
				28	config SIPI_FINAL_TIMEOUT
				29	int
				30	default 400000
				31
				32	config PCR_BASE_ADDRESS
				33	hex
				34	default 0xfd000000
				35	help
				36	This option allows you to select MMIO Base Address of sideband bus.
				37
				38	config DCACHE_RAM_BASE
				39	hex
				40	default 0xfe800000
				41
				42	config DCACHE_RAM_SIZE
				43	hex
				44	default 0x1fff00
				45	help
				46	The size of the cache-as-ram region required during bootblock
				47	and/or romstage. FSP-T reserves the upper 0x100 for
				48	FspReservedBuffer.
				49
				50	config DCACHE_BSP_STACK_SIZE
				51	hex
				52	default 0x40000
				53	help
				54	The amount of anticipated stack usage in CAR by bootblock and
				55	other stages. It needs to include FSP-M stack requirement and
				56	CB romstage stack requirement. The integration documentation
				57	says this needs to be 256KiB.
				58
				59	config FSP_M_RC_HEAP_SIZE
				60	hex
				61	default 0x150000
				62	help
				63	On xeon_sp/spr FSP-M has two separate heap managers, one regular
				64	whose size and base are controllable via the StackBase and
				65	StackSize UPDs and a 'rc' heap manager that is statically
				66	allocated at 0xfe800000 (the CAR base) and consumes about 0x150000
				67	bytes of memory.
				68
				69	config CPU_MICROCODE_CBFS_LOC
				70	hex
				71	default 0xffe0fdc0
				72
				73	config CPU_MICROCODE_CBFS_LEN
				74	hex
				75	default 0x8c00
				76
				77	config HEAP_SIZE
				78	hex
				79	default 0x80000
				80
				81	config STACK_SIZE
				82	hex
				83	default 0x4000
				84
				85	config FSP_TEMP_RAM_SIZE
				86	hex
				87	depends on FSP_USES_CB_STACK
				88	default 0x60000
				89	help
				90	The amount of anticipated heap usage in CAR by FSP.
				91	Refer to Platform FSP integration guide document to know
				92	the exact FSP requirement for Heap setup. The FSP integration
				93	documentation says this needs to be at least 128KiB, but practice
				94	show this needs to be 256KiB or more.
				95
				96	config IED_REGION_SIZE
				97	hex
				98	default 0x400000
				99
				100	config IFD_CHIPSET
				101	string
				102	default "lbg"
				103
				104	config SOC_INTEL_COMMON_BLOCK_P2SB
				105	def_bool y
				106
				107	config SOC_INTEL_HAS_BIOS_DONE_MSR
				108	def_bool y
				109
				110	config SOC_INTEL_HAS_NCMEM
				111	def_bool y
				112
				113	config SOC_INTEL_HAS_CXL
				114	def_bool y
				115
				116	config SOC_INTEL_PCIE_64BIT_ALLOC
				117	def_bool y
				118
				119	config SOC_INTEL_MMAPVTD_ONLY_FOR_DPR
				120	def_bool y
				121
				122	config CPU_BCLK_MHZ
				123	int
				124	default 100
				125
				126	# SPR-SP has 4 IMCs, 2 channels per IMC, 2 DIMMs per channel
				127	# Default value is set to two sockets, full config.
				128	config MAX_IMC
				129	int
				130	default 4
				131
				132	config MAX_MC_CHN
				133	int
				134	default 2
				135
				136	config DIMM_MAX
				137	int
				138	default 32
				139
				140	# DDR4
				141	config DIMM_SPD_SIZE
				142	int
				143	default 1024
				144
				145	config MAX_ACPI_TABLE_SIZE_KB
				146	int
				147	default 224
				148
				149	config FIXED_SMBUS_IO_BASE
				150	default 0x780
				151
				152	config DISPLAY_UPD_IIO_DATA
				153	def_bool n
				154	depends on DISPLAY_UPD_DATA
				155
				156	if INTEL_TXT
				157
				158	config INTEL_TXT_SINIT_SIZE
				159	hex
				160	default 0x50000
				161	help
				162	According to document number 572782 this needs to be 256KiB
				163	for the SINIT module and 64KiB for SINIT data.
				164
				165	config INTEL_TXT_HEAP_SIZE
				166	hex
				167	default 0xf0000
				168	help
				169	This must be 960KiB according to 572782.
				170
				171	endif # INTEL_TXT
				172
				173	endif