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Lee Leahyb0005132015-05-12 18:19:47 -07001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2009 coresystems GmbH
5 * Copyright (C) 2014 Google Inc.
Lee Leahy1d14b3e2015-05-12 18:23:27 -07006 * Copyright (C) 2015 Intel Corporation.
Lee Leahyb0005132015-05-12 18:19:47 -07007 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
Lee Leahyb0005132015-05-12 18:19:47 -070016 */
17
18#include <arch/acpi.h>
19#include <arch/acpigen.h>
robbie zhangb45dde02015-10-01 17:21:33 -070020#include <arch/cpu.h>
Lee Leahyb0005132015-05-12 18:19:47 -070021#include <arch/io.h>
Duncan Lauriedb54a672015-09-04 14:19:35 -070022#include <arch/ioapic.h>
Lee Leahyb0005132015-05-12 18:19:47 -070023#include <arch/smp/mpspec.h>
24#include <cbmem.h>
Lee Leahy1d14b3e2015-05-12 18:23:27 -070025#include <chip.h>
Lee Leahyb0005132015-05-12 18:19:47 -070026#include <console/console.h>
Lee Leahy1d14b3e2015-05-12 18:23:27 -070027#include <cpu/cpu.h>
Lee Leahyb0005132015-05-12 18:19:47 -070028#include <cpu/x86/smm.h>
Lee Leahyb0005132015-05-12 18:19:47 -070029#include <cpu/x86/msr.h>
30#include <cpu/x86/tsc.h>
31#include <cpu/intel/turbo.h>
32#include <ec/google/chromeec/ec.h>
Barnali Sarkar0a203d12017-05-04 18:02:17 +053033#include <intelblocks/cpulib.h>
Ravi Sarawadi1483d1f2017-09-28 17:06:01 -070034#include <intelblocks/lpc_lib.h>
Pratik Prajapati418535e2017-10-11 16:12:21 -070035#include <intelblocks/sgx.h>
Duncan Laurie93bbd412017-11-11 20:03:29 -080036#include <intelblocks/uart.h>
Duncan Lauriea1c8b342015-09-08 16:12:44 -070037#include <soc/intel/common/acpi.h>
Lee Leahyb0005132015-05-12 18:19:47 -070038#include <soc/acpi.h>
39#include <soc/cpu.h>
40#include <soc/iomap.h>
Lee Leahyb0005132015-05-12 18:19:47 -070041#include <soc/msr.h>
42#include <soc/pci_devs.h>
43#include <soc/pm.h>
Naresh G Solankia2d40622016-08-30 20:47:13 +053044#include <soc/ramstage.h>
robbie zhangb45dde02015-10-01 17:21:33 -070045#include <string.h>
46#include <types.h>
47#include <vendorcode/google/chromeos/gnvs.h>
Duncan Laurie3d3b76b2016-02-25 08:45:43 -080048#include <wrdd.h>
Lee Leahyb0005132015-05-12 18:19:47 -070049
50/*
Lee Leahy1d14b3e2015-05-12 18:23:27 -070051 * List of suported C-states in this processor.
Lee Leahyb0005132015-05-12 18:19:47 -070052 */
53enum {
Lee Leahy1d14b3e2015-05-12 18:23:27 -070054 C_STATE_C0, /* 0 */
55 C_STATE_C1, /* 1 */
56 C_STATE_C1E, /* 2 */
57 C_STATE_C3, /* 3 */
58 C_STATE_C6_SHORT_LAT, /* 4 */
59 C_STATE_C6_LONG_LAT, /* 5 */
60 C_STATE_C7_SHORT_LAT, /* 6 */
61 C_STATE_C7_LONG_LAT, /* 7 */
62 C_STATE_C7S_SHORT_LAT, /* 8 */
63 C_STATE_C7S_LONG_LAT, /* 9 */
64 C_STATE_C8, /* 10 */
65 C_STATE_C9, /* 11 */
66 C_STATE_C10, /* 12 */
Lee Leahyb0005132015-05-12 18:19:47 -070067 NUM_C_STATES
68};
Lee Leahy1d14b3e2015-05-12 18:23:27 -070069#define MWAIT_RES(state, sub_state) \
70 { \
71 .addrl = (((state) << 4) | (sub_state)), \
72 .space_id = ACPI_ADDRESS_SPACE_FIXED, \
73 .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, \
74 .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, \
75 .access_size = ACPI_FFIXEDHW_FLAG_HW_COORD, \
Lee Leahyb0005132015-05-12 18:19:47 -070076 }
77
78static acpi_cstate_t cstate_map[NUM_C_STATES] = {
79 [C_STATE_C0] = { },
80 [C_STATE_C1] = {
81 .latency = 0,
robbie zhangc16b1fd2015-09-11 14:25:15 -070082 .power = C1_POWER,
Lee Leahy1d14b3e2015-05-12 18:23:27 -070083 .resource = MWAIT_RES(0, 0),
Lee Leahyb0005132015-05-12 18:19:47 -070084 },
85 [C_STATE_C1E] = {
86 .latency = 0,
robbie zhangc16b1fd2015-09-11 14:25:15 -070087 .power = C1_POWER,
Lee Leahy1d14b3e2015-05-12 18:23:27 -070088 .resource = MWAIT_RES(0, 1),
Lee Leahyb0005132015-05-12 18:19:47 -070089 },
90 [C_STATE_C3] = {
91 .latency = C_STATE_LATENCY_FROM_LAT_REG(0),
robbie zhangc16b1fd2015-09-11 14:25:15 -070092 .power = C3_POWER,
Lee Leahyb0005132015-05-12 18:19:47 -070093 .resource = MWAIT_RES(1, 0),
94 },
95 [C_STATE_C6_SHORT_LAT] = {
96 .latency = C_STATE_LATENCY_FROM_LAT_REG(1),
robbie zhangc16b1fd2015-09-11 14:25:15 -070097 .power = C6_POWER,
Lee Leahyb0005132015-05-12 18:19:47 -070098 .resource = MWAIT_RES(2, 0),
99 },
100 [C_STATE_C6_LONG_LAT] = {
101 .latency = C_STATE_LATENCY_FROM_LAT_REG(2),
robbie zhangc16b1fd2015-09-11 14:25:15 -0700102 .power = C6_POWER,
Lee Leahyb0005132015-05-12 18:19:47 -0700103 .resource = MWAIT_RES(2, 1),
104 },
105 [C_STATE_C7_SHORT_LAT] = {
106 .latency = C_STATE_LATENCY_FROM_LAT_REG(1),
robbie zhangc16b1fd2015-09-11 14:25:15 -0700107 .power = C7_POWER,
Lee Leahyb0005132015-05-12 18:19:47 -0700108 .resource = MWAIT_RES(3, 0),
109 },
110 [C_STATE_C7_LONG_LAT] = {
111 .latency = C_STATE_LATENCY_FROM_LAT_REG(2),
robbie zhangc16b1fd2015-09-11 14:25:15 -0700112 .power = C7_POWER,
Lee Leahyb0005132015-05-12 18:19:47 -0700113 .resource = MWAIT_RES(3, 1),
114 },
115 [C_STATE_C7S_SHORT_LAT] = {
116 .latency = C_STATE_LATENCY_FROM_LAT_REG(1),
robbie zhangc16b1fd2015-09-11 14:25:15 -0700117 .power = C7_POWER,
Lee Leahyb0005132015-05-12 18:19:47 -0700118 .resource = MWAIT_RES(3, 2),
119 },
120 [C_STATE_C7S_LONG_LAT] = {
121 .latency = C_STATE_LATENCY_FROM_LAT_REG(2),
robbie zhangc16b1fd2015-09-11 14:25:15 -0700122 .power = C7_POWER,
Lee Leahyb0005132015-05-12 18:19:47 -0700123 .resource = MWAIT_RES(3, 3),
124 },
125 [C_STATE_C8] = {
126 .latency = C_STATE_LATENCY_FROM_LAT_REG(3),
robbie zhangc16b1fd2015-09-11 14:25:15 -0700127 .power = C8_POWER,
Lee Leahyb0005132015-05-12 18:19:47 -0700128 .resource = MWAIT_RES(4, 0),
129 },
130 [C_STATE_C9] = {
131 .latency = C_STATE_LATENCY_FROM_LAT_REG(4),
robbie zhangc16b1fd2015-09-11 14:25:15 -0700132 .power = C9_POWER,
Lee Leahyb0005132015-05-12 18:19:47 -0700133 .resource = MWAIT_RES(5, 0),
134 },
135 [C_STATE_C10] = {
136 .latency = C_STATE_LATENCY_FROM_LAT_REG(5),
robbie zhangc16b1fd2015-09-11 14:25:15 -0700137 .power = C10_POWER,
Lee Leahyb0005132015-05-12 18:19:47 -0700138 .resource = MWAIT_RES(6, 0),
139 },
140};
141
Lee Leahy1d14b3e2015-05-12 18:23:27 -0700142static int cstate_set_s0ix[] = {
Lee Leahyb0005132015-05-12 18:19:47 -0700143 C_STATE_C1E,
144 C_STATE_C7S_LONG_LAT,
145 C_STATE_C10
146};
147
Lee Leahy1d14b3e2015-05-12 18:23:27 -0700148static int cstate_set_non_s0ix[] = {
Lee Leahyb0005132015-05-12 18:19:47 -0700149 C_STATE_C1E,
150 C_STATE_C3,
Lee Leahy1d14b3e2015-05-12 18:23:27 -0700151 C_STATE_C7S_LONG_LAT,
Lee Leahyb0005132015-05-12 18:19:47 -0700152};
153
154static int get_cores_per_package(void)
155{
156 struct cpuinfo_x86 c;
157 struct cpuid_result result;
158 int cores = 1;
159
160 get_fms(&c, cpuid_eax(1));
161 if (c.x86 != 6)
162 return 1;
163
164 result = cpuid_ext(0xb, 1);
165 cores = result.ebx & 0xff;
166
167 return cores;
168}
169
Duncan Lauriedb54a672015-09-04 14:19:35 -0700170static void acpi_create_gnvs(global_nvs_t *gnvs)
Lee Leahyb0005132015-05-12 18:19:47 -0700171{
Duncan Laurie7fce30c2015-09-04 13:53:14 -0700172 const struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC);
173 const struct soc_intel_skylake_config *config = dev->chip_info;
174
Lee Leahyb0005132015-05-12 18:19:47 -0700175 /* Set unknown wake source */
176 gnvs->pm1i = -1;
177
178 /* CPU core count */
179 gnvs->pcnt = dev_count_cpu();
180
Lee Leahy1d14b3e2015-05-12 18:23:27 -0700181#if IS_ENABLED(CONFIG_CONSOLE_CBMEM)
Lee Leahyb0005132015-05-12 18:19:47 -0700182 /* Update the mem console pointer. */
183 gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE);
184#endif
185
Lee Leahy1d14b3e2015-05-12 18:23:27 -0700186#if IS_ENABLED(CONFIG_CHROMEOS)
Lee Leahyb0005132015-05-12 18:19:47 -0700187 /* Initialize Verified Boot data */
188 chromeos_init_vboot(&(gnvs->chromeos));
Lee Leahy1d14b3e2015-05-12 18:23:27 -0700189#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
Lee Leahyb0005132015-05-12 18:19:47 -0700190 gnvs->chromeos.vbt2 = google_ec_running_ro() ?
191 ACTIVE_ECFW_RO : ACTIVE_ECFW_RW;
192#endif
193 gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO;
194#endif
Duncan Laurie7fce30c2015-09-04 13:53:14 -0700195
196 /* Enable DPTF based on mainboard configuration */
197 gnvs->dpte = config->dptf_enable;
Duncan Laurie3d3b76b2016-02-25 08:45:43 -0800198
199 /* Fill in the Wifi Region id */
200 gnvs->cid1 = wifi_regulatory_domain();
Furquan Shaikh3bfe3402016-10-18 14:25:25 -0700201
202 /* Set USB2/USB3 wake enable bitmaps. */
203 gnvs->u2we = config->usb2_wake_enable_bitmap;
204 gnvs->u3we = config->usb3_wake_enable_bitmap;
Pratik Prajapati418535e2017-10-11 16:12:21 -0700205
206 if (IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_SGX))
207 sgx_fill_gnvs(gnvs);
Lee Leahyb0005132015-05-12 18:19:47 -0700208}
209
Lee Leahyb0005132015-05-12 18:19:47 -0700210unsigned long acpi_fill_mcfg(unsigned long current)
211{
212 current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current,
213 MCFG_BASE_ADDRESS, 0, 0, 255);
214 return current;
215}
216
Duncan Lauriedb54a672015-09-04 14:19:35 -0700217unsigned long acpi_fill_madt(unsigned long current)
218{
219 /* Local APICs */
220 current = acpi_create_madt_lapics(current);
221
222 /* IOAPIC */
223 current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
224 2, IO_APIC_ADDR, 0);
225
226 return acpi_madt_irq_overrides(current);
227}
228
Duncan Laurie135c2c42016-10-17 19:47:51 -0700229void acpi_fill_fadt(acpi_fadt_t *fadt)
Lee Leahyb0005132015-05-12 18:19:47 -0700230{
231 const uint16_t pmbase = ACPI_BASE_ADDRESS;
232
Werner Zeh00d250e2017-04-26 07:03:10 +0200233 /* Use ACPI 3.0 revision */
234 fadt->header.revision = ACPI_FADT_REV_ACPI_3_0;
Duncan Laurie135c2c42016-10-17 19:47:51 -0700235
Lee Leahyb0005132015-05-12 18:19:47 -0700236 fadt->sci_int = acpi_sci_irq();
237 fadt->smi_cmd = APM_CNT;
238 fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
239 fadt->acpi_disable = APM_CNT_ACPI_DISABLE;
240 fadt->s4bios_req = 0x0;
241 fadt->pstate_cnt = 0;
242
243 fadt->pm1a_evt_blk = pmbase + PM1_STS;
244 fadt->pm1b_evt_blk = 0x0;
245 fadt->pm1a_cnt_blk = pmbase + PM1_CNT;
246 fadt->pm1b_cnt_blk = 0x0;
247 fadt->pm2_cnt_blk = pmbase + PM2_CNT;
Duncan Laurie662b6cb2018-01-30 09:58:07 -0800248 fadt->pm_tmr_blk = pmbase + PM1_TMR;
Lee Leahyb0005132015-05-12 18:19:47 -0700249 fadt->gpe0_blk = pmbase + GPE0_STS(0);
250 fadt->gpe1_blk = 0;
251
252 fadt->pm1_evt_len = 4;
253 fadt->pm1_cnt_len = 2;
254 fadt->pm2_cnt_len = 1;
Duncan Laurie662b6cb2018-01-30 09:58:07 -0800255 fadt->pm_tmr_len = 4;
Aaron Durbin71e0ac82015-08-07 23:00:22 -0500256 /* There are 4 GPE0 STS/EN pairs each 32 bits wide. */
257 fadt->gpe0_blk_len = 2 * GPE0_REG_MAX * sizeof(uint32_t);
Lee Leahyb0005132015-05-12 18:19:47 -0700258 fadt->gpe1_blk_len = 0;
259 fadt->gpe1_base = 0;
260 fadt->cst_cnt = 0;
261 fadt->p_lvl2_lat = 1;
262 fadt->p_lvl3_lat = 87;
263 fadt->flush_size = 1024;
264 fadt->flush_stride = 16;
265 fadt->duty_offset = 1;
266 fadt->duty_width = 0;
267 fadt->day_alrm = 0xd;
268 fadt->mon_alrm = 0x00;
269 fadt->century = 0x00;
Jenny TC2864f852017-02-09 16:01:59 +0530270 fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES;
271 if (!IS_ENABLED(CONFIG_NO_FADT_8042))
272 fadt->iapc_boot_arch |= ACPI_FADT_8042;
Lee Leahyb0005132015-05-12 18:19:47 -0700273
274 fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
275 ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON |
276 ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE |
277 ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK;
278
279 fadt->reset_reg.space_id = 1;
280 fadt->reset_reg.bit_width = 8;
281 fadt->reset_reg.bit_offset = 0;
282 fadt->reset_reg.resv = 0;
283 fadt->reset_reg.addrl = 0xcf9;
284 fadt->reset_reg.addrh = 0;
285 fadt->reset_value = 6;
286
287 fadt->x_pm1a_evt_blk.space_id = 1;
288 fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8;
289 fadt->x_pm1a_evt_blk.bit_offset = 0;
290 fadt->x_pm1a_evt_blk.resv = 0;
291 fadt->x_pm1a_evt_blk.addrl = pmbase + PM1_STS;
292 fadt->x_pm1a_evt_blk.addrh = 0x0;
293
294 fadt->x_pm1b_evt_blk.space_id = 1;
295 fadt->x_pm1b_evt_blk.bit_width = 0;
296 fadt->x_pm1b_evt_blk.bit_offset = 0;
297 fadt->x_pm1b_evt_blk.resv = 0;
298 fadt->x_pm1b_evt_blk.addrl = 0x0;
299 fadt->x_pm1b_evt_blk.addrh = 0x0;
300
301 fadt->x_pm1a_cnt_blk.space_id = 1;
302 fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8;
303 fadt->x_pm1a_cnt_blk.bit_offset = 0;
304 fadt->x_pm1a_cnt_blk.resv = 0;
305 fadt->x_pm1a_cnt_blk.addrl = pmbase + PM1_CNT;
306 fadt->x_pm1a_cnt_blk.addrh = 0x0;
307
308 fadt->x_pm1b_cnt_blk.space_id = 1;
309 fadt->x_pm1b_cnt_blk.bit_width = 0;
310 fadt->x_pm1b_cnt_blk.bit_offset = 0;
311 fadt->x_pm1b_cnt_blk.resv = 0;
312 fadt->x_pm1b_cnt_blk.addrl = 0x0;
313 fadt->x_pm1b_cnt_blk.addrh = 0x0;
314
315 fadt->x_pm2_cnt_blk.space_id = 1;
316 fadt->x_pm2_cnt_blk.bit_width = fadt->pm2_cnt_len * 8;
317 fadt->x_pm2_cnt_blk.bit_offset = 0;
318 fadt->x_pm2_cnt_blk.resv = 0;
319 fadt->x_pm2_cnt_blk.addrl = pmbase + PM2_CNT;
320 fadt->x_pm2_cnt_blk.addrh = 0x0;
321
Duncan Laurie662b6cb2018-01-30 09:58:07 -0800322 fadt->x_pm_tmr_blk.space_id = 1;
323 fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8;
324 fadt->x_pm_tmr_blk.bit_offset = 0;
325 fadt->x_pm_tmr_blk.resv = 0;
326 fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR;
327 fadt->x_pm_tmr_blk.addrh = 0x0;
Lee Leahyb0005132015-05-12 18:19:47 -0700328
329 fadt->x_gpe0_blk.space_id = 0;
330 fadt->x_gpe0_blk.bit_width = 0;
331 fadt->x_gpe0_blk.bit_offset = 0;
332 fadt->x_gpe0_blk.resv = 0;
333 fadt->x_gpe0_blk.addrl = 0;
334 fadt->x_gpe0_blk.addrh = 0;
335
336 fadt->x_gpe1_blk.space_id = 1;
337 fadt->x_gpe1_blk.bit_width = 0;
338 fadt->x_gpe1_blk.bit_offset = 0;
339 fadt->x_gpe1_blk.resv = 0;
340 fadt->x_gpe1_blk.addrl = 0x0;
341 fadt->x_gpe1_blk.addrh = 0x0;
342}
343
Lee Leahy1d14b3e2015-05-12 18:23:27 -0700344static void generate_c_state_entries(int s0ix_enable, int max_cstate)
Lee Leahyb0005132015-05-12 18:19:47 -0700345{
Lee Leahyb0005132015-05-12 18:19:47 -0700346
Lee Leahy1d14b3e2015-05-12 18:23:27 -0700347 acpi_cstate_t map[max_cstate];
Lee Leahyb0005132015-05-12 18:19:47 -0700348 int *set;
349 int i;
350
Lee Leahy1d14b3e2015-05-12 18:23:27 -0700351 if (s0ix_enable)
Lee Leahyb0005132015-05-12 18:19:47 -0700352 set = cstate_set_s0ix;
353 else
354 set = cstate_set_non_s0ix;
355
Lee Leahy1d14b3e2015-05-12 18:23:27 -0700356 for (i = 0; i < max_cstate; i++) {
Lee Leahyb0005132015-05-12 18:19:47 -0700357 memcpy(&map[i], &cstate_map[set[i]], sizeof(acpi_cstate_t));
358 map[i].ctype = i + 1;
359 }
360
361 /* Generate C-state tables */
Lee Leahy1d14b3e2015-05-12 18:23:27 -0700362 acpigen_write_CST_package(map, ARRAY_SIZE(map));
Lee Leahyb0005132015-05-12 18:19:47 -0700363}
364
365static int calculate_power(int tdp, int p1_ratio, int ratio)
366{
367 u32 m;
368 u32 power;
369
370 /*
371 * M = ((1.1 - ((p1_ratio - ratio) * 0.00625)) / 1.1) ^ 2
372 *
373 * Power = (ratio / p1_ratio) * m * tdp
374 */
375
376 m = (110000 - ((p1_ratio - ratio) * 625)) / 11;
377 m = (m * m) / 1000;
378
379 power = ((ratio * 100000 / p1_ratio) / 100);
380 power *= (m / 100) * (tdp / 1000);
381 power /= 1000;
382
383 return (int)power;
384}
385
Lee Leahy1d14b3e2015-05-12 18:23:27 -0700386static void generate_p_state_entries(int core, int cores_per_package)
Lee Leahyb0005132015-05-12 18:19:47 -0700387{
388 int ratio_min, ratio_max, ratio_turbo, ratio_step;
389 int coord_type, power_max, power_unit, num_entries;
390 int ratio, power, clock, clock_max;
391 msr_t msr;
392
393 /* Determine P-state coordination type from MISC_PWR_MGMT[0] */
394 msr = rdmsr(MSR_MISC_PWR_MGMT);
395 if (msr.lo & MISC_PWR_MGMT_EIST_HW_DIS)
396 coord_type = SW_ANY;
397 else
398 coord_type = HW_ALL;
399
400 /* Get bus ratio limits and calculate clock speeds */
401 msr = rdmsr(MSR_PLATFORM_INFO);
402 ratio_min = (msr.hi >> (40-32)) & 0xff; /* Max Efficiency Ratio */
403
404 /* Determine if this CPU has configurable TDP */
405 if (cpu_config_tdp_levels()) {
406 /* Set max ratio to nominal TDP ratio */
407 msr = rdmsr(MSR_CONFIG_TDP_NOMINAL);
408 ratio_max = msr.lo & 0xff;
409 } else {
410 /* Max Non-Turbo Ratio */
411 ratio_max = (msr.lo >> 8) & 0xff;
412 }
Aamir Bohra1041d392017-06-02 11:56:14 +0530413 clock_max = ratio_max * CONFIG_CPU_BCLK_MHZ;
Lee Leahyb0005132015-05-12 18:19:47 -0700414
415 /* Calculate CPU TDP in mW */
416 msr = rdmsr(MSR_PKG_POWER_SKU_UNIT);
417 power_unit = 2 << ((msr.lo & 0xf) - 1);
418 msr = rdmsr(MSR_PKG_POWER_SKU);
419 power_max = ((msr.lo & 0x7fff) / power_unit) * 1000;
420
421 /* Write _PCT indicating use of FFixedHW */
422 acpigen_write_empty_PCT();
423
424 /* Write _PPC with no limit on supported P-state */
425 acpigen_write_PPC_NVS();
426
427 /* Write PSD indicating configured coordination type */
428 acpigen_write_PSD_package(core, 1, coord_type);
429
430 /* Add P-state entries in _PSS table */
431 acpigen_write_name("_PSS");
432
433 /* Determine ratio points */
434 ratio_step = PSS_RATIO_STEP;
Lee Leahy1d14b3e2015-05-12 18:23:27 -0700435 num_entries = ((ratio_max - ratio_min) / ratio_step) + 1;
436 if (num_entries > PSS_MAX_ENTRIES) {
437 ratio_step += 1;
438 num_entries = ((ratio_max - ratio_min) / ratio_step) + 1;
Lee Leahyb0005132015-05-12 18:19:47 -0700439 }
440
441 /* P[T] is Turbo state if enabled */
442 if (get_turbo_state() == TURBO_ENABLED) {
443 /* _PSS package count including Turbo */
444 acpigen_write_package(num_entries + 2);
445
446 msr = rdmsr(MSR_TURBO_RATIO_LIMIT);
447 ratio_turbo = msr.lo & 0xff;
448
449 /* Add entry for Turbo ratio */
450 acpigen_write_PSS_package(
Lee Leahy1d14b3e2015-05-12 18:23:27 -0700451 clock_max + 1, /* MHz */
452 power_max, /* mW */
453 PSS_LATENCY_TRANSITION, /* lat1 */
454 PSS_LATENCY_BUSMASTER, /* lat2 */
455 ratio_turbo << 8, /* control */
456 ratio_turbo << 8); /* status */
Lee Leahyb0005132015-05-12 18:19:47 -0700457 } else {
458 /* _PSS package count without Turbo */
459 acpigen_write_package(num_entries + 1);
460 }
461
462 /* First regular entry is max non-turbo ratio */
463 acpigen_write_PSS_package(
Lee Leahy1d14b3e2015-05-12 18:23:27 -0700464 clock_max, /* MHz */
465 power_max, /* mW */
466 PSS_LATENCY_TRANSITION, /* lat1 */
467 PSS_LATENCY_BUSMASTER, /* lat2 */
468 ratio_max << 8, /* control */
469 ratio_max << 8); /* status */
Lee Leahyb0005132015-05-12 18:19:47 -0700470
471 /* Generate the remaining entries */
472 for (ratio = ratio_min + ((num_entries - 1) * ratio_step);
473 ratio >= ratio_min; ratio -= ratio_step) {
474
475 /* Calculate power at this ratio */
476 power = calculate_power(power_max, ratio_max, ratio);
Aamir Bohra1041d392017-06-02 11:56:14 +0530477 clock = ratio * CONFIG_CPU_BCLK_MHZ;
Lee Leahyb0005132015-05-12 18:19:47 -0700478
479 acpigen_write_PSS_package(
Lee Leahy1d14b3e2015-05-12 18:23:27 -0700480 clock, /* MHz */
481 power, /* mW */
482 PSS_LATENCY_TRANSITION, /* lat1 */
483 PSS_LATENCY_BUSMASTER, /* lat2 */
484 ratio << 8, /* control */
485 ratio << 8); /* status */
Lee Leahyb0005132015-05-12 18:19:47 -0700486 }
487
488 /* Fix package length */
489 acpigen_pop_len();
490}
491
Lee Leahy1d14b3e2015-05-12 18:23:27 -0700492void generate_cpu_entries(device_t device)
Lee Leahyb0005132015-05-12 18:19:47 -0700493{
Lee Leahy1d14b3e2015-05-12 18:23:27 -0700494 int core_id, cpu_id, pcontrol_blk = ACPI_BASE_ADDRESS, plen = 6;
Lee Leahyb0005132015-05-12 18:19:47 -0700495 int totalcores = dev_count_cpu();
496 int cores_per_package = get_cores_per_package();
497 int numcpus = totalcores/cores_per_package;
Lee Leahy1d14b3e2015-05-12 18:23:27 -0700498 device_t dev = SA_DEV_ROOT;
499 config_t *config = dev->chip_info;
500 int is_s0ix_enable = config->s0ix_enable;
501 int max_c_state;
502
503 if (is_s0ix_enable)
504 max_c_state = ARRAY_SIZE(cstate_set_s0ix);
505 else
506 max_c_state = ARRAY_SIZE(cstate_set_non_s0ix);
Lee Leahyb0005132015-05-12 18:19:47 -0700507
508 printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n",
509 numcpus, cores_per_package);
510
Lee Leahy1d14b3e2015-05-12 18:23:27 -0700511 for (cpu_id = 0; cpu_id < numcpus; cpu_id++) {
512 for (core_id = 0; core_id < cores_per_package; core_id++) {
513 if (core_id > 0) {
Lee Leahyb0005132015-05-12 18:19:47 -0700514 pcontrol_blk = 0;
515 plen = 0;
516 }
517
518 /* Generate processor \_PR.CPUx */
519 acpigen_write_processor(
Lee Leahy1d14b3e2015-05-12 18:23:27 -0700520 cpu_id*cores_per_package+core_id,
Lee Leahyb0005132015-05-12 18:19:47 -0700521 pcontrol_blk, plen);
Lee Leahy1d14b3e2015-05-12 18:23:27 -0700522 /* Generate C-state tables */
523 generate_c_state_entries(is_s0ix_enable,
524 max_c_state);
Lee Leahyb0005132015-05-12 18:19:47 -0700525
Subrata Banik6b45ee42017-05-12 11:43:57 +0530526 if (config->eist_enable)
527 /* Generate P-state tables */
528 generate_p_state_entries(core_id,
529 cores_per_package);
Lee Leahyb0005132015-05-12 18:19:47 -0700530
531 acpigen_pop_len();
532 }
533 }
534}
535
536unsigned long acpi_madt_irq_overrides(unsigned long current)
537{
538 int sci = acpi_sci_irq();
539 acpi_madt_irqoverride_t *irqovr;
540 uint16_t flags = MP_IRQ_TRIGGER_LEVEL;
541
542 /* INT_SRC_OVR */
543 irqovr = (void *)current;
544 current += acpi_create_madt_irqoverride(irqovr, 0, 0, 2, 0);
545
546 if (sci >= 20)
547 flags |= MP_IRQ_POLARITY_LOW;
548 else
549 flags |= MP_IRQ_POLARITY_HIGH;
550
551 /* SCI */
552 irqovr = (void *)current;
553 current += acpi_create_madt_irqoverride(irqovr, 0, sci, sci, flags);
554
555 return current;
556}
Lee Leahy1d14b3e2015-05-12 18:23:27 -0700557
Ravi Sarawadi1483d1f2017-09-28 17:06:01 -0700558unsigned long southbridge_write_acpi_tables(device_t device,
Lee Leahy1d14b3e2015-05-12 18:23:27 -0700559 unsigned long current,
560 struct acpi_rsdp *rsdp)
561{
Duncan Laurie93bbd412017-11-11 20:03:29 -0800562 current = acpi_write_dbg2_pci_uart(rsdp, current,
563 pch_uart_get_debug_controller(),
564 ACPI_ACCESS_SIZE_DWORD_ACCESS);
Lee Leahy1d14b3e2015-05-12 18:23:27 -0700565 current = acpi_write_hpet(device, current, rsdp);
Aaron Durbin07a1b282015-12-10 17:07:38 -0600566 return acpi_align_current(current);
Lee Leahy1d14b3e2015-05-12 18:23:27 -0700567}
568
Ravi Sarawadi1483d1f2017-09-28 17:06:01 -0700569void southbridge_inject_dsdt(device_t device)
Lee Leahy1d14b3e2015-05-12 18:23:27 -0700570{
571 global_nvs_t *gnvs;
572
573 gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
574 if (!gnvs) {
Lee Leahyf4c4ab92017-03-16 17:08:03 -0700575 gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs));
Lee Leahy1d14b3e2015-05-12 18:23:27 -0700576 if (gnvs)
577 memset(gnvs, 0, sizeof(*gnvs));
578 }
579
580 if (gnvs) {
581 acpi_create_gnvs(gnvs);
Duncan Lauriedb54a672015-09-04 14:19:35 -0700582 acpi_mainboard_gnvs(gnvs);
Lee Leahy1d14b3e2015-05-12 18:23:27 -0700583 acpi_save_gnvs((unsigned long)gnvs);
584 /* And tell SMI about it */
585 smm_setup_structures(gnvs, NULL, NULL);
586
587 /* Add it to DSDT. */
588 acpigen_write_scope("\\");
589 acpigen_write_name_dword("NVSA", (u32) gnvs);
590 acpigen_pop_len();
591 }
592}
593
Duncan Lauriea1c8b342015-09-08 16:12:44 -0700594/* Save wake source information for calculating ACPI _SWS values */
595int soc_fill_acpi_wake(uint32_t *pm1, uint32_t **gpe0)
596{
Duncan Laurie95f90202016-10-25 20:07:22 -0700597 const struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC);
598 const struct soc_intel_skylake_config *config = dev->chip_info;
Naresh G Solankia1b35472015-12-11 18:13:02 +0530599 struct chipset_power_state *ps;
Duncan Lauriea1c8b342015-09-08 16:12:44 -0700600 static uint32_t gpe0_sts[GPE0_REG_MAX];
601 uint32_t pm1_en;
Duncan Laurie95f90202016-10-25 20:07:22 -0700602 uint32_t gpe0_std;
Duncan Lauriea1c8b342015-09-08 16:12:44 -0700603 int i;
Aaron Durbin64606ce2016-10-27 09:53:17 -0500604 const int last_index = GPE0_REG_MAX - 1;
Duncan Lauriea1c8b342015-09-08 16:12:44 -0700605
Naresh G Solankia1b35472015-12-11 18:13:02 +0530606 ps = cbmem_find(CBMEM_ID_POWER_STATE);
607 if (ps == NULL)
608 return -1;
609
Duncan Laurie95f90202016-10-25 20:07:22 -0700610 pm1_en = ps->pm1_en;
611 gpe0_std = ps->gpe0_en[3];
612
613 /*
614 * Chipset state in the suspend well (but not RTC) is lost in Deep S3
615 * so enable Deep S3 wake events that are configured by the mainboard
616 */
Duncan Laurie1fe32d62017-04-10 21:02:13 -0700617 if (ps->prev_sleep_state == ACPI_S3 &&
618 (config->deep_s3_enable_ac || config->deep_s3_enable_dc)) {
Duncan Laurie95f90202016-10-25 20:07:22 -0700619 pm1_en |= PWRBTN_STS; /* Always enabled as wake source */
620 if (config->deep_sx_config & DSX_EN_LAN_WAKE_PIN)
621 gpe0_std |= LAN_WAK_EN;
622 if (config->deep_sx_config & DSX_EN_WAKE_PIN)
623 pm1_en |= PCIEXPWAK_STS;
624 }
625
Duncan Lauriea1c8b342015-09-08 16:12:44 -0700626 *pm1 = ps->pm1_sts & pm1_en;
627
628 /* Mask off GPE0 status bits that are not enabled */
629 *gpe0 = &gpe0_sts[0];
Aaron Durbin64606ce2016-10-27 09:53:17 -0500630 for (i = 0; i < last_index; i++)
Duncan Lauriea1c8b342015-09-08 16:12:44 -0700631 gpe0_sts[i] = ps->gpe0_sts[i] & ps->gpe0_en[i];
Aaron Durbin64606ce2016-10-27 09:53:17 -0500632 gpe0_sts[last_index] = ps->gpe0_sts[last_index] & gpe0_std;
Duncan Lauriea1c8b342015-09-08 16:12:44 -0700633
634 return GPE0_REG_MAX;
635}
636
Duncan Lauriedb54a672015-09-04 14:19:35 -0700637__attribute__((weak)) void acpi_mainboard_gnvs(global_nvs_t *gnvs)
Lee Leahy1d14b3e2015-05-12 18:23:27 -0700638{
639}
Naresh G Solankia2d40622016-08-30 20:47:13 +0530640
Aaron Durbinaa090cb2017-09-13 16:01:52 -0600641const char *soc_acpi_name(const struct device *dev)
Naresh G Solankia2d40622016-08-30 20:47:13 +0530642{
643 if (dev->path.type == DEVICE_PATH_DOMAIN)
644 return "PCI0";
645
646 if (dev->path.type != DEVICE_PATH_PCI)
647 return NULL;
648
649 switch (dev->path.pci.devfn) {
650 case SA_DEVFN_ROOT: return "MCHC";
651 case SA_DEVFN_IGD: return "GFX0";
652 case PCH_DEVFN_ISH: return "ISHB";
653 case PCH_DEVFN_XHCI: return "XHCI";
654 case PCH_DEVFN_USBOTG: return "XDCI";
655 case PCH_DEVFN_THERMAL: return "THRM";
656 case PCH_DEVFN_CIO: return "ICIO";
657 case PCH_DEVFN_I2C0: return "I2C0";
658 case PCH_DEVFN_I2C1: return "I2C1";
659 case PCH_DEVFN_I2C2: return "I2C2";
660 case PCH_DEVFN_I2C3: return "I2C3";
Subrata Banik2ee54db2017-03-05 12:37:00 +0530661 case PCH_DEVFN_CSE: return "CSE1";
662 case PCH_DEVFN_CSE_2: return "CSE2";
663 case PCH_DEVFN_CSE_IDER: return "CSED";
664 case PCH_DEVFN_CSE_KT: return "CSKT";
665 case PCH_DEVFN_CSE_3: return "CSE3";
Naresh G Solankia2d40622016-08-30 20:47:13 +0530666 case PCH_DEVFN_SATA: return "SATA";
667 case PCH_DEVFN_UART2: return "UAR2";
668 case PCH_DEVFN_I2C4: return "I2C4";
669 case PCH_DEVFN_I2C5: return "I2C5";
670 case PCH_DEVFN_PCIE1: return "RP01";
671 case PCH_DEVFN_PCIE2: return "RP02";
672 case PCH_DEVFN_PCIE3: return "RP03";
673 case PCH_DEVFN_PCIE4: return "RP04";
674 case PCH_DEVFN_PCIE5: return "RP05";
675 case PCH_DEVFN_PCIE6: return "RP06";
676 case PCH_DEVFN_PCIE7: return "RP07";
677 case PCH_DEVFN_PCIE8: return "RP08";
678 case PCH_DEVFN_PCIE9: return "RP09";
679 case PCH_DEVFN_PCIE10: return "RP10";
680 case PCH_DEVFN_PCIE11: return "RP11";
681 case PCH_DEVFN_PCIE12: return "RP12";
682 case PCH_DEVFN_UART0: return "UAR0";
683 case PCH_DEVFN_UART1: return "UAR1";
684 case PCH_DEVFN_GSPI0: return "SPI0";
685 case PCH_DEVFN_GSPI1: return "SPI1";
686 case PCH_DEVFN_EMMC: return "EMMC";
687 case PCH_DEVFN_SDIO: return "SDIO";
688 case PCH_DEVFN_SDCARD: return "SDXC";
689 case PCH_DEVFN_LPC: return "LPCB";
690 case PCH_DEVFN_P2SB: return "P2SB";
691 case PCH_DEVFN_PMC: return "PMC_";
692 case PCH_DEVFN_HDA: return "HDAS";
693 case PCH_DEVFN_SMBUS: return "SBUS";
694 case PCH_DEVFN_SPI: return "FSPI";
695 case PCH_DEVFN_GBE: return "IGBE";
696 case PCH_DEVFN_TRACEHUB:return "THUB";
697 }
698
699 return NULL;
700}
Furquan Shaikha6f0b272017-05-23 11:53:47 -0700701
702static int acpigen_soc_gpio_op(const char *op, unsigned int gpio_num)
703{
704 /* op (gpio_num) */
705 acpigen_emit_namestring(op);
706 acpigen_write_integer(gpio_num);
707 return 0;
708}
709
710static int acpigen_soc_get_gpio_state(const char *op, unsigned int gpio_num)
711{
712 /* Store (op (gpio_num), Local0) */
713 acpigen_write_store();
714 acpigen_soc_gpio_op(op, gpio_num);
715 acpigen_emit_byte(LOCAL0_OP);
716 return 0;
717}
718
719int acpigen_soc_read_rx_gpio(unsigned int gpio_num)
720{
721 return acpigen_soc_get_gpio_state("\\_SB.PCI0.GRXS", gpio_num);
722}
723
724int acpigen_soc_get_tx_gpio(unsigned int gpio_num)
725{
726 return acpigen_soc_get_gpio_state("\\_SB.PCI0.GTXS", gpio_num);
727}
728
729int acpigen_soc_set_tx_gpio(unsigned int gpio_num)
730{
731 return acpigen_soc_gpio_op("\\_SB.PCI0.STXS", gpio_num);
732}
733
734int acpigen_soc_clear_tx_gpio(unsigned int gpio_num)
735{
736 return acpigen_soc_gpio_op("\\_SB.PCI0.CTXS", gpio_num);
737}