| Stefan Reinauer | 6626d6a | 2012-03-30 15:10:07 -0700 | [diff] [blame^] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | */ |
| 19 | |
| 20 | /* |
| 21 | * The chip could be bootstrap mapped to one of four LPC addresses: |
| 22 | * 0x2e, 0x4e, 0x162e, and 0x164e. |
| 23 | */ |
| 24 | const u16 sio1007_lpc_ports[] = {0x2e, 0x4e, 0x162e, 0x164e}; |
| 25 | |
| 26 | static void sio1007_setreg(u16 lpc_port, u8 reg, u8 value, u8 mask) |
| 27 | { |
| 28 | u8 reg_value; |
| 29 | |
| 30 | outb(reg, lpc_port); |
| 31 | reg_value = inb(lpc_port + 1); |
| 32 | reg_value &= ~mask; |
| 33 | reg_value |= (value & mask); |
| 34 | outb(reg_value, lpc_port + 1); |
| 35 | } |
| 36 | |
| 37 | static int sio1007_enable_uart_at(u16 port) |
| 38 | { |
| 39 | /* Enable config mode. */ |
| 40 | outb(0x55, port); |
| 41 | if (inb(port) != 0x55) |
| 42 | return 0; /* There is no LPC device at this address. */ |
| 43 | |
| 44 | /* Registers 12 and 13 hold config address, look for a match. */ |
| 45 | outb(0x12, port); |
| 46 | if (inb(port + 1) != (port & 0xff)) |
| 47 | return 0; |
| 48 | |
| 49 | outb(0x13, port); |
| 50 | if (inb(port + 1) != (port >> 8)) |
| 51 | return 0; |
| 52 | |
| 53 | /* This must be the sio1007, enable the UART. */ |
| 54 | /* turn on power */ |
| 55 | sio1007_setreg(port, 0x2, 1 << 3, 1 << 3); |
| 56 | /* enable high speed */ |
| 57 | sio1007_setreg(port, 0xc, 1 << 6, 1 << 6); |
| 58 | /* set the base address */ |
| 59 | sio1007_setreg(port, 0x24, CONFIG_TTYS0_BASE >> 2, 0xff); |
| 60 | |
| 61 | /* Disable config mode. */ |
| 62 | outb(0xaa, port); |
| 63 | return 1; |
| 64 | } |