blob: db44650a1de9e095b2bb2185f3694da38e936be7 [file] [log] [blame]
Eric Biederman5cd81732004-03-11 15:01:31 +00001#include <device/pci_def.h>
2#include <device/pci_ids.h>
3#include <device/hypertransport_def.h>
4
5static unsigned ht_lookup_slave_capability(device_t dev)
6{
7 unsigned pos;
8 uint8_t hdr_type;
9
10 hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE);
11 pos = 0;
12 hdr_type &= 0x7f;
13
14 if ((hdr_type == PCI_HEADER_TYPE_NORMAL) ||
Li-Ta Lo4cd79f32004-03-26 21:34:04 +000015 (hdr_type == PCI_HEADER_TYPE_BRIDGE)) {
Eric Biederman5cd81732004-03-11 15:01:31 +000016 pos = PCI_CAPABILITY_LIST;
17 }
18 if (pos > PCI_CAP_LIST_NEXT) {
19 pos = pci_read_config8(dev, pos);
20 }
21 while(pos != 0) { /* loop through the linked list */
22 uint8_t cap;
23 cap = pci_read_config8(dev, pos + PCI_CAP_LIST_ID);
24 if (cap == PCI_CAP_ID_HT) {
25 uint16_t flags;
26
27 flags = pci_read_config16(dev, pos + PCI_CAP_FLAGS);
28 if ((flags >> 13) == 0) {
29 /* Entry is a Slave secondary, success... */
30 break;
31 }
32 }
33 pos = pci_read_config8(dev, pos + PCI_CAP_LIST_NEXT);
34 }
35 return pos;
36}
37
38static void ht_collapse_previous_enumeration(unsigned bus)
39{
40 device_t dev;
41
42 /* Spin through the devices and collapse any previous
43 * hypertransport enumeration.
44 */
45 for(dev = PCI_DEV(bus, 0, 0); dev <= PCI_DEV(bus, 0x1f, 0x7); dev += PCI_DEV(0, 1, 0)) {
46 uint32_t id;
47 unsigned pos, flags;
48
49 id = pci_read_config32(dev, PCI_VENDOR_ID);
50 if ((id == 0xffffffff) || (id == 0x00000000) ||
Li-Ta Lo4cd79f32004-03-26 21:34:04 +000051 (id == 0x0000ffff) || (id == 0xffff0000)) {
Eric Biederman5cd81732004-03-11 15:01:31 +000052 continue;
53 }
54 pos = ht_lookup_slave_capability(dev);
55 if (!pos) {
56 continue;
57 }
58
59 /* Clear the unitid */
60 flags = pci_read_config16(dev, pos + PCI_CAP_FLAGS);
61 flags &= ~0x1f;
62 pci_write_config16(dev, pos + PCI_CAP_FLAGS, flags);
63 }
64}
65
Eric Biederman5cd81732004-03-11 15:01:31 +000066static unsigned ht_read_freq_cap(device_t dev, unsigned pos)
67{
68 /* Handle bugs in valid hypertransport frequency reporting */
69 unsigned freq_cap;
70 uint32_t id;
71
72 freq_cap = pci_read_config16(dev, pos);
73 freq_cap &= ~(1 << HT_FREQ_VENDOR); /* Ignore Vendor HT frequencies */
74
75 id = pci_read_config32(dev, 0);
76
77 /* AMD 8131 Errata 48 */
78 if (id == (PCI_VENDOR_ID_AMD | (PCI_DEVICE_ID_AMD_8131_PCIX << 16))) {
79 freq_cap &= ~(1 << HT_FREQ_800Mhz);
80 }
81 /* AMD 8151 Errata 23 */
82 if (id == (PCI_VENDOR_ID_AMD | (PCI_DEVICE_ID_AMD_8151_SYSCTRL << 16))) {
83 freq_cap &= ~(1 << HT_FREQ_800Mhz);
84 }
85 /* AMD K8 Unsupported 1Ghz? */
86 if (id == (PCI_VENDOR_ID_AMD | (0x1100 << 16))) {
87 freq_cap &= ~(1 << HT_FREQ_1000Mhz);
88 }
89 return freq_cap;
90}
91
Li-Ta Lo4cd79f32004-03-26 21:34:04 +000092#define LINK_OFFS(WIDTH,FREQ,FREQ_CAP) \
Eric Biederman5cd81732004-03-11 15:01:31 +000093 (((WIDTH & 0xff) << 16) | ((FREQ & 0xff) << 8) | (FREQ_CAP & 0xFF))
94
95#define LINK_WIDTH(OFFS) ((OFFS >> 16) & 0xFF)
96#define LINK_FREQ(OFFS) ((OFFS >> 8) & 0xFF)
97#define LINK_FREQ_CAP(OFFS) ((OFFS) & 0xFF)
98
Li-Ta Lo4cd79f32004-03-26 21:34:04 +000099#define PCI_HT_HOST_OFFS LINK_OFFS( \
100 PCI_HT_CAP_HOST_WIDTH, \
101 PCI_HT_CAP_HOST_FREQ, \
102 PCI_HT_CAP_HOST_FREQ_CAP)
Eric Biederman5cd81732004-03-11 15:01:31 +0000103
Li-Ta Lo4cd79f32004-03-26 21:34:04 +0000104#define PCI_HT_SLAVE0_OFFS LINK_OFFS( \
105 PCI_HT_CAP_SLAVE_WIDTH0, \
106 PCI_HT_CAP_SLAVE_FREQ0, \
107 PCI_HT_CAP_SLAVE_FREQ_CAP0)
Eric Biederman5cd81732004-03-11 15:01:31 +0000108
Li-Ta Lo4cd79f32004-03-26 21:34:04 +0000109#define PCI_HT_SLAVE1_OFFS LINK_OFFS( \
110 PCI_HT_CAP_SLAVE_WIDTH1, \
111 PCI_HT_CAP_SLAVE_FREQ1, \
112 PCI_HT_CAP_SLAVE_FREQ_CAP1)
Eric Biederman5cd81732004-03-11 15:01:31 +0000113
114static int ht_optimize_link(
115 device_t dev1, uint8_t pos1, unsigned offs1,
116 device_t dev2, uint8_t pos2, unsigned offs2)
117{
118 static const uint8_t link_width_to_pow2[]= { 3, 4, 0, 5, 1, 2, 0, 0 };
119 static const uint8_t pow2_to_link_width[] = { 0x7, 4, 5, 0, 1, 3 };
120 uint16_t freq_cap1, freq_cap2, freq_cap, freq_mask;
121 uint8_t width_cap1, width_cap2, width_cap, width, old_width, ln_width1, ln_width2;
122 uint8_t freq, old_freq;
123 int needs_reset;
124 /* Set link width and frequency */
125
126 /* Initially assume everything is already optimized and I don't need a reset */
127 needs_reset = 0;
128
129 /* Get the frequency capabilities */
130 freq_cap1 = ht_read_freq_cap(dev1, pos1 + LINK_FREQ_CAP(offs1));
131 freq_cap2 = ht_read_freq_cap(dev2, pos2 + LINK_FREQ_CAP(offs2));
132
133 /* Calculate the highest possible frequency */
134 freq = log2(freq_cap1 & freq_cap2);
135
136 /* See if I am changing the link freqency */
137 old_freq = pci_read_config8(dev1, pos1 + LINK_FREQ(offs1));
138 needs_reset |= old_freq != freq;
139 old_freq = pci_read_config8(dev2, pos2 + LINK_FREQ(offs2));
140 needs_reset |= old_freq != freq;
141
142 /* Set the Calulcated link frequency */
143 pci_write_config8(dev1, pos1 + LINK_FREQ(offs1), freq);
144 pci_write_config8(dev2, pos2 + LINK_FREQ(offs2), freq);
145
146 /* Get the width capabilities */
147 width_cap1 = pci_read_config8(dev1, pos1 + LINK_WIDTH(offs1));
148 width_cap2 = pci_read_config8(dev2, pos2 + LINK_WIDTH(offs2));
149
150 /* Calculate dev1's input width */
151 ln_width1 = link_width_to_pow2[width_cap1 & 7];
152 ln_width2 = link_width_to_pow2[(width_cap2 >> 4) & 7];
153 if (ln_width1 > ln_width2) {
154 ln_width1 = ln_width2;
155 }
156 width = pow2_to_link_width[ln_width1];
157 /* Calculate dev1's output width */
158 ln_width1 = link_width_to_pow2[(width_cap1 >> 4) & 7];
159 ln_width2 = link_width_to_pow2[width_cap2 & 7];
160 if (ln_width1 > ln_width2) {
161 ln_width1 = ln_width2;
162 }
163 width |= pow2_to_link_width[ln_width1] << 4;
164
165 /* See if I am changing dev1's width */
166 old_width = pci_read_config8(dev1, pos1 + LINK_WIDTH(offs1) + 1);
167 needs_reset |= old_width != width;
168
169 /* Set dev1's widths */
170 pci_write_config8(dev1, pos1 + LINK_WIDTH(offs1) + 1, width);
171
172 /* Calculate dev2's width */
173 width = ((width & 0x70) >> 4) | ((width & 0x7) << 4);
174
175 /* See if I am changing dev2's width */
176 old_width = pci_read_config8(dev2, pos2 + LINK_WIDTH(offs2) + 1);
177 needs_reset |= old_width != width;
178
179 /* Set dev2's widths */
180 pci_write_config8(dev2, pos2 + LINK_WIDTH(offs2) + 1, width);
181
182 return needs_reset;
183}
184
185static int ht_setup_chain(device_t udev, unsigned upos)
186{
187 /* Assumption the HT chain that is bus 0 has the HT I/O Hub on it.
188 * On most boards this just happens. If a cpu has multiple
189 * non Coherent links the appropriate bus registers for the
190 * links needs to be programed to point at bus 0.
191 */
192 unsigned next_unitid, last_unitid;
193 int reset_needed;
194 unsigned uoffs;
195
196#warning "FIXME handle multiple chains!"
197
198 /* Make certain the HT bus is not enumerated */
199 ht_collapse_previous_enumeration(0);
200
201 reset_needed = 0;
202 uoffs = PCI_HT_HOST_OFFS;
203 next_unitid = 1;
204 do {
205 uint32_t id;
206 uint8_t pos;
207 unsigned flags, count;
208 device_t dev = PCI_DEV(0, 0, 0);
209 last_unitid = next_unitid;
210
211 id = pci_read_config32(dev, PCI_VENDOR_ID);
212 /* If the chain is enumerated quit */
213 if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
Li-Ta Lo4cd79f32004-03-26 21:34:04 +0000214 (((id >> 16) & 0xffff) == 0xffff) ||
215 (((id >> 16) & 0xffff) == 0x0000)) {
Eric Biederman5cd81732004-03-11 15:01:31 +0000216 break;
217 }
218 pos = ht_lookup_slave_capability(dev);
219 if (!pos) {
220 print_err("HT link capability not found\r\n");
221 break;
222 }
223 /* Setup the Hypertransport link */
224 reset_needed |= ht_optimize_link(udev, upos, uoffs, dev, pos, PCI_HT_SLAVE0_OFFS);
225
226 /* Update the Unitid of the current device */
227 flags = pci_read_config16(dev, pos + PCI_CAP_FLAGS);
228 flags &= ~0x1f; /* mask out the bse Unit ID */
229 flags |= next_unitid & 0x1f;
230 pci_write_config16(dev, pos + PCI_CAP_FLAGS, flags);
231
232 /* Remeber the location of the last device */
233 udev = PCI_DEV(0, next_unitid, 0);
234 upos = pos;
235 uoffs = PCI_HT_SLAVE1_OFFS;
236
237 /* Compute the number of unitids consumed */
238 count = (flags >> 5) & 0x1f;
239 next_unitid += count;
240
241 } while((last_unitid != next_unitid) && (next_unitid <= 0x1f));
242 return reset_needed;
243}
Li-Ta Lo4cd79f32004-03-26 21:34:04 +0000244
Li-Ta Loedeff592004-03-25 17:50:06 +0000245struct ht_chain {
Li-Ta Lo4cd79f32004-03-26 21:34:04 +0000246 device_t udev;
247 unsigned upos;
248 unsigned devreg;
249};
250
251static int ht_setup_chainx(device_t udev, unsigned upos, unsigned next_unitid)
252{
253 unsigned last_unitid;
254 unsigned uoffs;
255 int reset_needed=0;
256
257 uoffs = PCI_HT_HOST_OFFS;
258 do {
259 uint32_t id;
260 uint8_t pos;
261 unsigned flags, count;
262 device_t dev = PCI_DEV(0, 0, 0);
263 last_unitid = next_unitid;
264
265 id = pci_read_config32(dev, PCI_VENDOR_ID);
266 /* If the chain is enumerated quit */
267 if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
268 (((id >> 16) & 0xffff) == 0xffff) ||
269 (((id >> 16) & 0xffff) == 0x0000)) {
270 break;
271 }
272 pos = ht_lookup_slave_capability(dev);
273 if (!pos) {
274 print_err("HT link capability not found\r\n");
275 break;
276 }
277 /* Setup the Hypertransport link */
278 reset_needed |= ht_optimize_link(udev, upos, uoffs, dev, pos, PCI_HT_SLAVE0_OFFS);
279
280 /* Update the Unitid of the current device */
281 flags = pci_read_config16(dev, pos + PCI_CAP_FLAGS);
282 flags &= ~0x1f; /* mask out the bse Unit ID */
283 flags |= next_unitid & 0x1f;
284 pci_write_config16(dev, pos + PCI_CAP_FLAGS, flags);
285
286 /* Remeber the location of the last device */
287 udev = PCI_DEV(0, next_unitid, 0);
288 upos = pos;
289 uoffs = PCI_HT_SLAVE1_OFFS;
290
291 /* Compute the number of unitids consumed */
292 count = (flags >> 5) & 0x1f;
293 next_unitid += count;
294
295 } while((last_unitid != next_unitid) && (next_unitid <= 0x1f));
296 if(reset_needed!=0) next_unitid |= 0xffff0000;
297 return next_unitid;
298}
Li-Ta Loedeff592004-03-25 17:50:06 +0000299
300static int ht_setup_chains(const struct ht_chain *ht_c, int ht_c_num)
Li-Ta Lo4cd79f32004-03-26 21:34:04 +0000301{
302 /* Assumption the HT chain that is bus 0 has the HT I/O Hub on it.
303 * On most boards this just happens. If a cpu has multiple
304 * non Coherent links the appropriate bus registers for the
305 * links needs to be programed to point at bus 0.
306 */
307 unsigned next_unitid;
308 int reset_needed;
309 unsigned upos;
310 device_t udev;
311 int i;
Li-Ta Loedeff592004-03-25 17:50:06 +0000312
Li-Ta Lo4cd79f32004-03-26 21:34:04 +0000313 /* Make certain the HT bus is not enumerated */
314 ht_collapse_previous_enumeration(0);
Li-Ta Loedeff592004-03-25 17:50:06 +0000315
Li-Ta Lo4cd79f32004-03-26 21:34:04 +0000316 reset_needed = 0;
317 next_unitid = 1;
Li-Ta Loedeff592004-03-25 17:50:06 +0000318
319
Li-Ta Lo4cd79f32004-03-26 21:34:04 +0000320 for(i=0;i<ht_c_num;i++) {
321 uint32_t reg;
322 uint8_t reg8;
323 reg = pci_read_config32(PCI_DEV(0,0x18,1), ht_c[i].devreg);
324 reg |= (0xff<<24) | 7;
325 reg &= ~(0xff<<16);
326 pci_write_config32(PCI_DEV(0,0x18,1), ht_c[i].devreg, reg);
Li-Ta Loedeff592004-03-25 17:50:06 +0000327
Li-Ta Loedeff592004-03-25 17:50:06 +0000328#if CONFIG_MAX_CPUS > 1
Li-Ta Lo4cd79f32004-03-26 21:34:04 +0000329 pci_write_config32(PCI_DEV(0,0x19,1), ht_c[i].devreg, reg);
Li-Ta Loedeff592004-03-25 17:50:06 +0000330#endif
331#if CONFIG_MAX_CPUS > 2
Li-Ta Lo4cd79f32004-03-26 21:34:04 +0000332 pci_write_config32(PCI_DEV(0,0x1a,1), ht_c[i].devreg, reg);
333 pci_write_config32(PCI_DEV(0,0x1b,1), ht_c[i].devreg, reg);
Li-Ta Loedeff592004-03-25 17:50:06 +0000334#endif
335
Li-Ta Lo4cd79f32004-03-26 21:34:04 +0000336 //Store dev min
337 reg8 = next_unitid & 0xff ;
338 upos = ht_c[i].upos;
339 udev = ht_c[i].udev;
Li-Ta Loedeff592004-03-25 17:50:06 +0000340
Li-Ta Lo4cd79f32004-03-26 21:34:04 +0000341 next_unitid = ht_setup_chainx(udev,upos,next_unitid);
342 if((next_unitid & 0xffff0000) == 0xffff0000) {
343 reset_needed |= 1;
344 next_unitid &=0x0000ffff;
345 }
Li-Ta Loedeff592004-03-25 17:50:06 +0000346
Li-Ta Lo4cd79f32004-03-26 21:34:04 +0000347 //set dev min
348 pci_write_config8(PCI_DEV(0,0x18,1), ht_c[i].devreg+2, reg8);
Li-Ta Loedeff592004-03-25 17:50:06 +0000349#if CONFIG_MAX_CPUS > 1
Li-Ta Lo4cd79f32004-03-26 21:34:04 +0000350 pci_write_config8(PCI_DEV(0,0x19,1), ht_c[i].devreg+2, reg8);
Li-Ta Loedeff592004-03-25 17:50:06 +0000351#endif
352#if CONFIG_MAX_CPUS > 2
Li-Ta Lo4cd79f32004-03-26 21:34:04 +0000353 pci_write_config8(PCI_DEV(0,0x1a,1), ht_c[i].devreg+2, reg8);
354 pci_write_config8(PCI_DEV(0,0x1b,1), ht_c[i].devreg+2, reg8);
Li-Ta Loedeff592004-03-25 17:50:06 +0000355#endif
Li-Ta Lo4cd79f32004-03-26 21:34:04 +0000356
357 //Set dev max
358 reg8 = (next_unitid-1) & 0xff ;
359 pci_write_config8(PCI_DEV(0,0x18,1), ht_c[i].devreg+3, reg8);
360#if CONFIG_MAX_CPUS > 1
361 pci_write_config8(PCI_DEV(0,0x19,1), ht_c[i].devreg+3, reg8);
Li-Ta Loedeff592004-03-25 17:50:06 +0000362#endif
363#if CONFIG_MAX_CPUS > 2
Li-Ta Lo4cd79f32004-03-26 21:34:04 +0000364 pci_write_config8(PCI_DEV(0,0x1a,1), ht_c[i].devreg+3, reg8);
365 pci_write_config8(PCI_DEV(0,0x1b,1), ht_c[i].devreg+3, reg8);
Li-Ta Loedeff592004-03-25 17:50:06 +0000366#endif
Li-Ta Lo4cd79f32004-03-26 21:34:04 +0000367 }
Li-Ta Loedeff592004-03-25 17:50:06 +0000368
Li-Ta Lo4cd79f32004-03-26 21:34:04 +0000369 return reset_needed;
Li-Ta Loedeff592004-03-25 17:50:06 +0000370}