Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2014 Google Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | */ |
| 19 | |
| 20 | #include <arch/io.h> |
| 21 | #include <cbmem.h> |
| 22 | #include <console/console.h> |
| 23 | #include <device/device.h> |
| 24 | #include <device/pci.h> |
| 25 | #include <device/pciexp.h> |
| 26 | #include <device/pci_ids.h> |
| 27 | #include <stdlib.h> |
| 28 | #include <broadwell/iobp.h> |
| 29 | #include <broadwell/nvs.h> |
| 30 | #include <broadwell/pch.h> |
| 31 | #include <broadwell/ramstage.h> |
| 32 | #include <broadwell/rcba.h> |
| 33 | #include <broadwell/serialio.h> |
| 34 | #include <chip.h> |
| 35 | |
| 36 | /* Set D3Hot Power State in ACPI mode */ |
| 37 | static void serialio_enable_d3hot(struct device *dev) |
| 38 | { |
| 39 | u32 reg32 = pci_read_config32(dev, PCH_PCS); |
| 40 | reg32 |= PCH_PCS_PS_D3HOT; |
| 41 | pci_write_config32(dev, PCH_PCS, reg32); |
| 42 | } |
| 43 | |
| 44 | /* Enable clock in PCI mode */ |
| 45 | static void serialio_enable_clock(struct resource *bar0) |
| 46 | { |
| 47 | u32 reg32 = read32(bar0->base + SIO_REG_PPR_CLOCK); |
| 48 | reg32 |= SIO_REG_PPR_CLOCK_EN; |
| 49 | write32(bar0->base + SIO_REG_PPR_CLOCK, reg32); |
| 50 | } |
| 51 | |
| 52 | /* Put Serial IO D21:F0-F6 device into desired mode. */ |
| 53 | static void serialio_d21_mode(int sio_index, int int_pin, int acpi_mode) |
| 54 | { |
| 55 | u32 portctrl = SIO_IOBP_PORTCTRL_PM_CAP_PRSNT; |
| 56 | |
| 57 | /* Snoop select 1. */ |
| 58 | portctrl |= SIO_IOBP_PORTCTRL_SNOOP_SELECT(1); |
| 59 | |
| 60 | /* Set interrupt pin. */ |
| 61 | portctrl |= SIO_IOBP_PORTCTRL_INT_PIN(int_pin); |
| 62 | |
| 63 | if (acpi_mode) { |
| 64 | /* Enable ACPI interrupt mode. */ |
| 65 | portctrl |= SIO_IOBP_PORTCTRL_ACPI_IRQ_EN; |
| 66 | |
| 67 | /* Disable PCI config space. */ |
| 68 | portctrl |= SIO_IOBP_PORTCTRL_PCI_CONF_DIS; |
| 69 | } |
| 70 | |
| 71 | pch_iobp_update(SIO_IOBP_PORTCTRLX(sio_index), 0, portctrl); |
| 72 | } |
| 73 | |
| 74 | /* Put Serial IO D23:F0 device into desired mode. */ |
| 75 | static void serialio_d23_mode(int acpi_mode) |
| 76 | { |
| 77 | u32 portctrl = 0; |
| 78 | |
| 79 | /* Snoop select 1. */ |
| 80 | pch_iobp_update(SIO_IOBP_PORTCTRL1, 0, |
| 81 | SIO_IOBP_PORTCTRL1_SNOOP_SELECT(1)); |
| 82 | |
| 83 | if (acpi_mode) { |
| 84 | /* Enable ACPI interrupt mode. */ |
| 85 | portctrl |= SIO_IOBP_PORTCTRL0_ACPI_IRQ_EN; |
| 86 | |
| 87 | /* Disable PCI config space. */ |
| 88 | portctrl |= SIO_IOBP_PORTCTRL0_PCI_CONF_DIS; |
| 89 | } |
| 90 | |
| 91 | pch_iobp_update(SIO_IOBP_PORTCTRL0, 0, portctrl); |
| 92 | } |
| 93 | |
| 94 | /* Enable LTR Auto Mode for D21:F1-F6. */ |
| 95 | static void serialio_d21_ltr(struct resource *bar0) |
| 96 | { |
| 97 | u32 reg; |
| 98 | |
| 99 | /* 1. Program BAR0 + 808h[2] = 0b */ |
| 100 | reg = read32(bar0->base + SIO_REG_PPR_GEN); |
| 101 | reg &= ~SIO_REG_PPR_GEN_LTR_MODE_MASK; |
| 102 | write32(bar0->base + SIO_REG_PPR_GEN, reg); |
| 103 | |
| 104 | /* 2. Program BAR0 + 804h[1:0] = 00b */ |
| 105 | reg = read32(bar0->base + SIO_REG_PPR_RST); |
| 106 | reg &= ~SIO_REG_PPR_RST_ASSERT; |
| 107 | write32(bar0->base + SIO_REG_PPR_RST, reg); |
| 108 | |
| 109 | /* 3. Program BAR0 + 804h[1:0] = 11b */ |
| 110 | reg = read32(bar0->base + SIO_REG_PPR_RST); |
| 111 | reg |= SIO_REG_PPR_RST_ASSERT; |
| 112 | write32(bar0->base + SIO_REG_PPR_RST, reg); |
| 113 | |
| 114 | /* 4. Program BAR0 + 814h[31:0] = 00000000h */ |
| 115 | write32(bar0->base + SIO_REG_AUTO_LTR, 0); |
| 116 | } |
| 117 | |
| 118 | /* Enable LTR Auto Mode for D23:F0. */ |
| 119 | static void serialio_d23_ltr(struct resource *bar0) |
| 120 | { |
| 121 | u32 reg; |
| 122 | |
| 123 | /* Program BAR0 + 1008h[2] = 1b */ |
| 124 | reg = read32(bar0->base + SIO_REG_SDIO_PPR_GEN); |
| 125 | reg |= SIO_REG_PPR_GEN_LTR_MODE_MASK; |
| 126 | write32(bar0->base + SIO_REG_SDIO_PPR_GEN, reg); |
| 127 | |
| 128 | /* Program BAR0 + 1010h = 0x00000000 */ |
| 129 | write32(bar0->base + SIO_REG_SDIO_PPR_SW_LTR, 0); |
| 130 | |
| 131 | /* Program BAR0 + 3Ch[30] = 1b */ |
| 132 | reg = read32(bar0->base + SIO_REG_SDIO_PPR_CMD12); |
| 133 | reg |= SIO_REG_SDIO_PPR_CMD12_B30; |
| 134 | write32(bar0->base + SIO_REG_SDIO_PPR_CMD12, reg); |
| 135 | } |
| 136 | |
| 137 | /* Select I2C voltage of 1.8V or 3.3V. */ |
| 138 | static void serialio_i2c_voltage_sel(struct resource *bar0, u8 voltage) |
| 139 | { |
| 140 | u32 reg32 = read32(bar0->base + SIO_REG_PPR_GEN); |
| 141 | reg32 &= ~SIO_REG_PPR_GEN_VOLTAGE_MASK; |
| 142 | reg32 |= SIO_REG_PPR_GEN_VOLTAGE(voltage); |
| 143 | write32(bar0->base + SIO_REG_PPR_GEN, reg32); |
| 144 | } |
| 145 | |
| 146 | /* Init sequence to be run once, done as part of D21:F0 (SDMA) init. */ |
| 147 | static void serialio_init_once(int acpi_mode) |
| 148 | { |
| 149 | if (acpi_mode) { |
| 150 | /* Enable ACPI IRQ for IRQ13, IRQ7, IRQ6, IRQ5 in RCBA. */ |
| 151 | RCBA32_OR(ACPIIRQEN, (1 << 13)|(1 << 7)|(1 << 6)|(1 << 5)); |
| 152 | } |
| 153 | |
| 154 | /* Program IOBP CB000154h[12,9:8,4:0] = 1001100011111b. */ |
| 155 | pch_iobp_update(SIO_IOBP_GPIODF, ~0x0000131f, 0x0000131f); |
| 156 | |
| 157 | /* Program IOBP CB000180h[5:0] = 111111b (undefined register) */ |
| 158 | pch_iobp_update(0xcb000180, ~0x0000003f, 0x0000003f); |
| 159 | } |
| 160 | |
| 161 | static void serialio_init(struct device *dev) |
| 162 | { |
| 163 | config_t *config = dev->chip_info; |
| 164 | struct resource *bar0, *bar1; |
| 165 | int sio_index = -1; |
| 166 | u32 reg32; |
| 167 | |
| 168 | printk(BIOS_DEBUG, "Initializing Serial IO device\n"); |
| 169 | |
| 170 | /* Ensure memory and bus master are enabled */ |
| 171 | reg32 = pci_read_config32(dev, PCI_COMMAND); |
| 172 | reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; |
| 173 | pci_write_config32(dev, PCI_COMMAND, reg32); |
| 174 | |
| 175 | /* Find BAR0 and BAR1 */ |
| 176 | bar0 = find_resource(dev, PCI_BASE_ADDRESS_0); |
| 177 | if (!bar0) |
| 178 | return; |
| 179 | bar1 = find_resource(dev, PCI_BASE_ADDRESS_1); |
| 180 | if (!bar1) |
| 181 | return; |
| 182 | |
| 183 | if (!config->sio_acpi_mode) |
| 184 | serialio_enable_clock(bar0); |
| 185 | else if (dev->path.pci.devfn != PCI_DEVFN(21, 0)) |
| 186 | serialio_enable_d3hot(dev); /* all but SDMA */ |
| 187 | |
| 188 | switch (dev->path.pci.devfn) { |
| 189 | case PCI_DEVFN(21, 0): /* SDMA */ |
| 190 | sio_index = SIO_ID_SDMA; |
| 191 | serialio_init_once(config->sio_acpi_mode); |
| 192 | serialio_d21_mode(sio_index, SIO_PIN_INTB, |
| 193 | config->sio_acpi_mode); |
| 194 | break; |
| 195 | case PCI_DEVFN(21, 1): /* I2C0 */ |
| 196 | sio_index = SIO_ID_I2C0; |
| 197 | serialio_d21_ltr(bar0); |
| 198 | serialio_i2c_voltage_sel(bar0, config->sio_i2c0_voltage); |
| 199 | serialio_d21_mode(sio_index, SIO_PIN_INTC, |
| 200 | config->sio_acpi_mode); |
| 201 | break; |
| 202 | case PCI_DEVFN(21, 2): /* I2C1 */ |
| 203 | sio_index = SIO_ID_I2C1; |
| 204 | serialio_d21_ltr(bar0); |
| 205 | serialio_i2c_voltage_sel(bar0, config->sio_i2c1_voltage); |
| 206 | serialio_d21_mode(sio_index, SIO_PIN_INTC, |
| 207 | config->sio_acpi_mode); |
| 208 | break; |
| 209 | case PCI_DEVFN(21, 3): /* SPI0 */ |
| 210 | sio_index = SIO_ID_SPI0; |
| 211 | serialio_d21_ltr(bar0); |
| 212 | serialio_d21_mode(sio_index, SIO_PIN_INTC, |
| 213 | config->sio_acpi_mode); |
| 214 | break; |
| 215 | case PCI_DEVFN(21, 4): /* SPI1 */ |
| 216 | sio_index = SIO_ID_SPI1; |
| 217 | serialio_d21_ltr(bar0); |
| 218 | serialio_d21_mode(sio_index, SIO_PIN_INTC, |
| 219 | config->sio_acpi_mode); |
| 220 | break; |
| 221 | case PCI_DEVFN(21, 5): /* UART0 */ |
| 222 | sio_index = SIO_ID_UART0; |
| 223 | serialio_d21_ltr(bar0); |
| 224 | serialio_d21_mode(sio_index, SIO_PIN_INTD, |
| 225 | config->sio_acpi_mode); |
| 226 | break; |
| 227 | case PCI_DEVFN(21, 6): /* UART1 */ |
| 228 | sio_index = SIO_ID_UART1; |
| 229 | serialio_d21_ltr(bar0); |
| 230 | serialio_d21_mode(sio_index, SIO_PIN_INTD, |
| 231 | config->sio_acpi_mode); |
| 232 | break; |
| 233 | case PCI_DEVFN(23, 0): /* SDIO */ |
| 234 | sio_index = SIO_ID_SDIO; |
| 235 | serialio_d23_ltr(bar0); |
| 236 | serialio_d23_mode(config->sio_acpi_mode); |
| 237 | break; |
| 238 | default: |
| 239 | return; |
| 240 | } |
| 241 | |
| 242 | if (config->sio_acpi_mode) { |
| 243 | global_nvs_t *gnvs; |
| 244 | |
| 245 | /* Find ACPI NVS to update BARs */ |
| 246 | gnvs = (global_nvs_t *)cbmem_find(CBMEM_ID_ACPI_GNVS); |
| 247 | if (!gnvs) { |
| 248 | printk(BIOS_ERR, "Unable to locate Global NVS\n"); |
| 249 | return; |
| 250 | } |
| 251 | |
| 252 | /* Save BAR0 and BAR1 to ACPI NVS */ |
| 253 | gnvs->dev.bar0[sio_index] = (u32)bar0->base; |
| 254 | gnvs->dev.bar1[sio_index] = (u32)bar1->base; |
| 255 | } |
| 256 | } |
| 257 | |
| 258 | static void serialio_set_resources(struct device *dev) |
| 259 | { |
| 260 | pci_dev_set_resources(dev); |
| 261 | |
| 262 | #if CONFIG_INTEL_PCH_UART_CONSOLE |
| 263 | /* Update UART base address if used for debug */ |
| 264 | if (serialio_uart_is_debug(dev)) { |
| 265 | struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0); |
| 266 | if (res) |
| 267 | uartmem_setbaseaddr(res->base); |
| 268 | } |
| 269 | #endif |
| 270 | } |
| 271 | |
| 272 | static struct device_operations device_ops = { |
| 273 | .read_resources = &pci_dev_read_resources, |
| 274 | .set_resources = &serialio_set_resources, |
| 275 | .enable_resources = &pci_dev_enable_resources, |
| 276 | .init = &serialio_init, |
| 277 | .ops_pci = &broadwell_pci_ops, |
| 278 | }; |
| 279 | |
| 280 | static const unsigned short pci_device_ids[] = { |
| 281 | 0x9c60, 0x9ce0, /* 0:15.0 - SDMA */ |
| 282 | 0x9c61, 0x9ce1, /* 0:15.1 - I2C0 */ |
| 283 | 0x9c62, 0x9ce2, /* 0:15.2 - I2C1 */ |
| 284 | 0x9c65, 0x9ce5, /* 0:15.3 - SPI0 */ |
| 285 | 0x9c66, 0x9ce6, /* 0:15.4 - SPI1 */ |
| 286 | 0x9c63, 0x9ce3, /* 0:15.5 - UART0 */ |
| 287 | 0x9c64, 0x9ce4, /* 0:15.6 - UART1 */ |
| 288 | 0x9c35, 0x9cb5, /* 0:17.0 - SDIO */ |
| 289 | 0 |
| 290 | }; |
| 291 | |
| 292 | static const struct pci_driver pch_pcie __pci_driver = { |
| 293 | .ops = &device_ops, |
| 294 | .vendor = PCI_VENDOR_ID_INTEL, |
| 295 | .devices = pci_device_ids, |
| 296 | }; |