Mondrian nuessle | 5b34bdd | 2009-04-22 20:34:05 +0000 | [diff] [blame^] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2006 Tyan |
| 5 | * Copyright (C) 2006 AMD |
| 6 | * Written by Yinghai Lu <yinghailu@gmail.com> for Tyan and AMD. |
| 7 | * |
| 8 | * Copyright (C) 2007 University of Mannheim |
| 9 | * Written by Philipp Degler <pdegler@rumms.uni-mannheim.de> for University of Mannheim |
| 10 | * Copyright (C) 2009 University of Heidelberg |
| 11 | * Written by Mondrian Nuessle <nuessle@uni-heidelberg.de> for University of Heidelberg |
| 12 | * |
| 13 | * This program is free software; you can redistribute it and/or modify |
| 14 | * it under the terms of the GNU General Public License as published by |
| 15 | * the Free Software Foundation; either version 2 of the License, or |
| 16 | * (at your option) any later version. |
| 17 | * |
| 18 | * This program is distributed in the hope that it will be useful, |
| 19 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 20 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 21 | * GNU General Public License for more details. |
| 22 | * |
| 23 | * You should have received a copy of the GNU General Public License |
| 24 | * along with this program; if not, write to the Free Software |
| 25 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 26 | */ |
| 27 | |
| 28 | #define ASSEMBLY 1 |
| 29 | #define __ROMCC__ |
| 30 | |
| 31 | #define RAMINIT_SYSINFO 1 |
| 32 | |
| 33 | #define K8_ALLOCATE_IO_RANGE 1 |
| 34 | //#define K8_SCAN_PCI_BUS 1 |
| 35 | |
| 36 | #define QRANK_DIMM_SUPPORT 1 |
| 37 | |
| 38 | #if CONFIG_LOGICAL_CPUS==1 |
| 39 | #define SET_NB_CFG_54 1 |
| 40 | #endif |
| 41 | |
| 42 | //used by init_cpus and fidvid |
| 43 | #define K8_SET_FIDVID 0 |
| 44 | //if we want to wait for core1 done before DQS training, set it to 0 |
| 45 | #define K8_SET_FIDVID_CORE0_ONLY 1 |
| 46 | |
| 47 | #if K8_REV_F_SUPPORT == 1 |
| 48 | #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 |
| 49 | #endif |
| 50 | |
| 51 | #define DBGP_DEFAULT 7 |
| 52 | |
| 53 | #include <stdint.h> |
| 54 | #include <device/pci_def.h> |
| 55 | #include <device/pci_ids.h> |
| 56 | #include <arch/io.h> |
| 57 | #include <device/pnp_def.h> |
| 58 | #include <arch/romcc_io.h> |
| 59 | #include <cpu/x86/lapic.h> |
| 60 | #include "option_table.h" |
| 61 | #include "pc80/mc146818rtc_early.c" |
| 62 | |
| 63 | |
| 64 | #if USE_FAILOVER_IMAGE==0 |
| 65 | #include "pc80/serial.c" |
| 66 | #include "arch/i386/lib/console.c" |
| 67 | #include "ram/ramtest.c" |
| 68 | |
| 69 | #include <cpu/amd/model_fxx_rev.h> |
| 70 | |
| 71 | #include "southbridge/broadcom/bcm5785/bcm5785_early_smbus.c" |
| 72 | #include "northbridge/amd/amdk8/raminit.h" |
| 73 | #include "cpu/amd/model_fxx/apic_timer.c" |
| 74 | #include "lib/delay.c" |
| 75 | |
| 76 | #endif |
| 77 | |
| 78 | #include "cpu/x86/lapic/boot_cpu.c" |
| 79 | #include "northbridge/amd/amdk8/reset_test.c" |
| 80 | |
| 81 | #include "superio/serverengines/pilot/pilot_early_serial.c" |
| 82 | #include "superio/serverengines/pilot/pilot_early_init.c" |
| 83 | #include "superio/nsc/pc87417/pc87417_early_serial.c" |
| 84 | |
| 85 | |
| 86 | #if USE_FAILOVER_IMAGE==0 |
| 87 | |
| 88 | #include "cpu/x86/bist.h" |
| 89 | |
| 90 | #if CONFIG_USE_INIT == 0 |
| 91 | #include "lib/memcpy.c" |
| 92 | #endif |
| 93 | |
| 94 | #include "northbridge/amd/amdk8/debug.c" |
| 95 | |
| 96 | #include "cpu/amd/mtrr/amd_earlymtrr.c" |
| 97 | |
| 98 | #include "northbridge/amd/amdk8/setup_resource_map.c" |
| 99 | |
| 100 | #define SERIAL_DEV PNP_DEV(0x2e, PILOT_SP1) |
| 101 | #define RTC_DEV PNP_DEV(0x4e, PC87417_RTC) |
| 102 | |
| 103 | #include "southbridge/broadcom/bcm5785/bcm5785_early_setup.c" |
| 104 | |
| 105 | static void memreset_setup(void) |
| 106 | { |
| 107 | } |
| 108 | |
| 109 | static void memreset(int controllers, const struct mem_controller *ctrl) |
| 110 | { |
| 111 | } |
| 112 | |
| 113 | static inline void activate_spd_rom(const struct mem_controller *ctrl) |
| 114 | { |
| 115 | #define SMBUS_SWITCH1 0x70 |
| 116 | #define SMBUS_SWITCH2 0x72 |
| 117 | unsigned device = (ctrl->channel0[0]) >> 8; |
| 118 | smbus_send_byte(SMBUS_SWITCH1, device & 0x0f); |
| 119 | smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f ); |
| 120 | } |
| 121 | |
| 122 | static inline int spd_read_byte(unsigned device, unsigned address) |
| 123 | { |
| 124 | return smbus_read_byte(device, address); |
| 125 | } |
| 126 | |
| 127 | #include "northbridge/amd/amdk8/amdk8_f.h" |
| 128 | #include "northbridge/amd/amdk8/coherent_ht.c" |
| 129 | |
| 130 | #include "northbridge/amd/amdk8/incoherent_ht.c" |
| 131 | |
| 132 | #include "northbridge/amd/amdk8/raminit_f.c" |
| 133 | |
| 134 | #include "sdram/generic_sdram.c" |
| 135 | |
| 136 | //#include "resourcemap.c" |
| 137 | |
| 138 | #include "cpu/amd/dualcore/dualcore.c" |
| 139 | |
| 140 | //first node |
| 141 | #define DIMM0 0x50 |
| 142 | #define DIMM1 0x51 |
| 143 | #define DIMM2 0x52 |
| 144 | #define DIMM3 0x53 |
| 145 | //second node |
| 146 | #define DIMM4 0x54 |
| 147 | #define DIMM5 0x55 |
| 148 | #define DIMM6 0x56 |
| 149 | #define DIMM7 0x57 |
| 150 | |
| 151 | |
| 152 | #include "cpu/amd/car/copy_and_run.c" |
| 153 | |
| 154 | #include "cpu/amd/car/post_cache_as_ram.c" |
| 155 | |
| 156 | #include "cpu/amd/model_fxx/init_cpus.c" |
| 157 | |
| 158 | #include "cpu/amd/model_fxx/fidvid.c" |
| 159 | |
| 160 | #endif |
| 161 | |
| 162 | #if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE == 1)) |
| 163 | |
| 164 | #include "northbridge/amd/amdk8/early_ht.c" |
| 165 | |
| 166 | #if 0 |
| 167 | #include "ipmi.c" |
| 168 | |
| 169 | static void setup_early_ipmi_serial() |
| 170 | { |
| 171 | unsigned char result; |
| 172 | char channel_access[]={0x06<<2,0x40,0x04,0x80,0x05}; |
| 173 | char serialmodem_conf[]={0x0c<<2,0x10,0x04,0x08,0x00,0x0f}; |
| 174 | char serial_mux1[]={0x0c<<2,0x12,0x04,0x06}; |
| 175 | char serial_mux2[]={0x0c<<2,0x12,0x04,0x03}; |
| 176 | char serial_mux3[]={0x0c<<2,0x12,0x04,0x07}; |
| 177 | |
| 178 | // earlydbg(0x0d); |
| 179 | //set channel access system only |
| 180 | ipmi_request(5,channel_access); |
| 181 | // earlydbg(result); |
| 182 | /* |
| 183 | //Set serial/modem config |
| 184 | result=ipmi_request(6,serialmodem_conf); |
| 185 | earlydbg(result); |
| 186 | |
| 187 | //Set serial mux 1 |
| 188 | result=ipmi_request(4,serial_mux1); |
| 189 | earlydbg(result); |
| 190 | |
| 191 | //Set serial mux 2 |
| 192 | result=ipmi_request(4,serial_mux2); |
| 193 | earlydbg(result); |
| 194 | |
| 195 | //Set serial mux 3 |
| 196 | result=ipmi_request(4,serial_mux3); |
| 197 | earlydbg(result); |
| 198 | */ |
| 199 | // earlydbg(0x0e); |
| 200 | |
| 201 | } |
| 202 | #endif |
| 203 | |
| 204 | |
| 205 | void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) |
| 206 | { |
| 207 | /* Is this a cpu only reset? Is this a secondary cpu? */ |
| 208 | if ((cpu_init_detectedx) || (!boot_cpu())) { |
| 209 | if (last_boot_normal()) { // RTC already inited |
| 210 | goto normal_image; //normal_image; |
| 211 | } else { |
| 212 | goto fallback_image; |
| 213 | } |
| 214 | } |
| 215 | |
| 216 | /* Nothing special needs to be done to find bus 0 */ |
| 217 | /* Allow the HT devices to be found */ |
| 218 | |
| 219 | enumerate_ht_chain(); |
| 220 | bcm5785_enable_rom(); |
| 221 | bcm5785_enable_lpc(); |
| 222 | //enable RTC |
| 223 | pc87417_enable_dev(RTC_DEV); |
| 224 | |
| 225 | /* Is this a deliberate reset by the bios */ |
| 226 | |
| 227 | if (bios_reset_detected() && last_boot_normal()) { |
| 228 | goto normal_image; |
| 229 | } |
| 230 | /* This is the primary cpu how should I boot? */ |
| 231 | else if (do_normal_boot()) { |
| 232 | goto normal_image; |
| 233 | } |
| 234 | else { |
| 235 | goto fallback_image; |
| 236 | } |
| 237 | normal_image: |
| 238 | __asm__ volatile ("jmp __normal_image" |
| 239 | : /* outputs */ |
| 240 | : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ |
| 241 | ); |
| 242 | |
| 243 | fallback_image: |
| 244 | #if HAVE_FAILOVER_BOOT==1 |
| 245 | __asm__ volatile ("jmp __fallback_image" |
| 246 | : /* outputs */ |
| 247 | : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ |
| 248 | ) |
| 249 | #endif |
| 250 | ; |
| 251 | |
| 252 | } |
| 253 | #endif |
| 254 | |
| 255 | void real_main(unsigned long bist, unsigned long cpu_init_detectedx); |
| 256 | |
| 257 | void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) |
| 258 | { |
| 259 | #if HAVE_FAILOVER_BOOT==1 |
| 260 | #if USE_FAILOVER_IMAGE==1 |
| 261 | failover_process(bist, cpu_init_detectedx); |
| 262 | #else |
| 263 | real_main(bist, cpu_init_detectedx); |
| 264 | #endif |
| 265 | #else |
| 266 | #if USE_FALLBACK_IMAGE == 1 |
| 267 | failover_process(bist, cpu_init_detectedx); |
| 268 | #endif |
| 269 | real_main(bist, cpu_init_detectedx); |
| 270 | #endif |
| 271 | } |
| 272 | |
| 273 | #if USE_FAILOVER_IMAGE==0 |
| 274 | |
| 275 | void real_main(unsigned long bist, unsigned long cpu_init_detectedx) |
| 276 | { |
| 277 | static const uint16_t spd_addr[] = { |
| 278 | //first node |
| 279 | DIMM0, DIMM2, 0, 0, |
| 280 | DIMM1, DIMM3, 0, 0, |
| 281 | #if CONFIG_MAX_PHYSICAL_CPUS > 1 |
| 282 | //second node |
| 283 | DIMM4, DIMM6, 0, 0, |
| 284 | DIMM5, DIMM7, 0, 0, |
| 285 | #endif |
| 286 | |
| 287 | }; |
| 288 | |
| 289 | struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); |
| 290 | |
| 291 | int needs_reset; |
| 292 | unsigned bsp_apicid = 0; |
| 293 | |
| 294 | |
| 295 | if (bist == 0) { |
| 296 | bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); |
| 297 | } |
| 298 | |
| 299 | pilot_enable_serial(SERIAL_DEV, TTYS0_BASE); |
| 300 | |
| 301 | //setup_mp_resource_map(); |
| 302 | |
| 303 | uart_init(); |
| 304 | |
| 305 | /* Halt if there was a built in self test failure */ |
| 306 | report_bist_failure(bist); |
| 307 | |
| 308 | |
| 309 | console_init(); |
| 310 | // setup_early_ipmi_serial(); |
| 311 | pilot_early_init(SERIAL_DEV); //config port is being taken from SERIAL_DEV |
| 312 | print_debug("*sysinfo range: ["); print_debug_hex32(sysinfo); print_debug(","); print_debug_hex32((unsigned long)sysinfo+sizeof(struct sys_info)); print_debug(")\r\n"); |
| 313 | |
| 314 | print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n"); |
| 315 | |
| 316 | #if MEM_TRAIN_SEQ == 1 |
| 317 | set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram |
| 318 | #endif |
| 319 | setup_coherent_ht_domain(); |
| 320 | |
| 321 | wait_all_core0_started(); |
| 322 | #if CONFIG_LOGICAL_CPUS==1 |
| 323 | // It is said that we should start core1 after all core0 launched |
| 324 | /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, |
| 325 | * So here need to make sure last core0 is started, esp for two way system, |
| 326 | * (there may be apic id conflicts in that case) |
| 327 | */ |
| 328 | start_other_cores(); |
| 329 | wait_all_other_cores_started(bsp_apicid); |
| 330 | #endif |
| 331 | |
| 332 | /* it will set up chains and store link pair for optimization later */ |
| 333 | ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn |
| 334 | bcm5785_early_setup(); |
| 335 | |
| 336 | #if K8_SET_FIDVID == 1 |
| 337 | { |
| 338 | msr_t msr; |
| 339 | msr=rdmsr(0xc0010042); |
| 340 | print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n"); |
| 341 | } |
| 342 | enable_fid_change(); |
| 343 | enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); |
| 344 | init_fidvid_bsp(bsp_apicid); |
| 345 | // show final fid and vid |
| 346 | { |
| 347 | msr_t msr; |
| 348 | msr=rdmsr(0xc0010042); |
| 349 | print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n"); |
| 350 | } |
| 351 | #endif |
| 352 | |
| 353 | needs_reset = optimize_link_coherent_ht(); |
| 354 | needs_reset |= optimize_link_incoherent_ht(sysinfo); |
| 355 | |
| 356 | // fidvid change will issue one LDTSTOP and the HT change will be effective too |
| 357 | if (needs_reset) { |
| 358 | print_info("ht reset -\r\n"); |
| 359 | soft_reset(); |
| 360 | } |
| 361 | |
| 362 | allow_all_aps_stop(bsp_apicid); |
| 363 | |
| 364 | //It's the time to set ctrl in sysinfo now; |
| 365 | fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); |
| 366 | enable_smbus(); |
| 367 | |
| 368 | memreset_setup(); |
| 369 | //do we need apci timer, tsc...., only debug need it for better output |
| 370 | /* all ap stopped? */ |
| 371 | // init_timer(); // Need to use TMICT to synconize FID/VID |
| 372 | |
| 373 | sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); |
| 374 | |
| 375 | post_cache_as_ram(); |
| 376 | |
| 377 | } |
| 378 | |
| 379 | #endif |