Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011 Chromium OS Authors |
| 5 | * Copyright (C) 2013 Vladimir Serbinenko |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 19 | */ |
| 20 | |
| 21 | #include <arch/io.h> |
| 22 | #include <console/console.h> |
| 23 | #include <delay.h> |
| 24 | #include <device/device.h> |
| 25 | #include <device/pci.h> |
| 26 | #include <device/pci_ids.h> |
| 27 | #include <string.h> |
| 28 | #include <device/pci_ops.h> |
| 29 | #include <cpu/x86/msr.h> |
| 30 | #include <cpu/x86/mtrr.h> |
Vladimir Serbinenko | 1315730 | 2014-02-19 22:18:08 +0100 | [diff] [blame] | 31 | #include <drivers/intel/gma/edid.h> |
| 32 | #include <drivers/intel/gma/i915.h> |
| 33 | #include <pc80/vga.h> |
| 34 | #include <pc80/vga_io.h> |
| 35 | |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 36 | |
| 37 | #include "chip.h" |
| 38 | #include "nehalem.h" |
| 39 | |
| 40 | struct gt_powermeter { |
| 41 | u16 reg; |
| 42 | u32 value; |
| 43 | }; |
| 44 | |
| 45 | static const struct gt_powermeter snb_pm_gt1[] = { |
| 46 | {0xa200, 0xcc000000}, |
| 47 | {0xa204, 0x07000040}, |
| 48 | {0xa208, 0x0000fe00}, |
| 49 | {0xa20c, 0x00000000}, |
| 50 | {0xa210, 0x17000000}, |
| 51 | {0xa214, 0x00000021}, |
| 52 | {0xa218, 0x0817fe19}, |
| 53 | {0xa21c, 0x00000000}, |
| 54 | {0xa220, 0x00000000}, |
| 55 | {0xa224, 0xcc000000}, |
| 56 | {0xa228, 0x07000040}, |
| 57 | {0xa22c, 0x0000fe00}, |
| 58 | {0xa230, 0x00000000}, |
| 59 | {0xa234, 0x17000000}, |
| 60 | {0xa238, 0x00000021}, |
| 61 | {0xa23c, 0x0817fe19}, |
| 62 | {0xa240, 0x00000000}, |
| 63 | {0xa244, 0x00000000}, |
| 64 | {0xa248, 0x8000421e}, |
| 65 | {0} |
| 66 | }; |
| 67 | |
| 68 | static const struct gt_powermeter snb_pm_gt2[] = { |
| 69 | {0xa200, 0x330000a6}, |
| 70 | {0xa204, 0x402d0031}, |
| 71 | {0xa208, 0x00165f83}, |
| 72 | {0xa20c, 0xf1000000}, |
| 73 | {0xa210, 0x00000000}, |
| 74 | {0xa214, 0x00160016}, |
| 75 | {0xa218, 0x002a002b}, |
| 76 | {0xa21c, 0x00000000}, |
| 77 | {0xa220, 0x00000000}, |
| 78 | {0xa224, 0x330000a6}, |
| 79 | {0xa228, 0x402d0031}, |
| 80 | {0xa22c, 0x00165f83}, |
| 81 | {0xa230, 0xf1000000}, |
| 82 | {0xa234, 0x00000000}, |
| 83 | {0xa238, 0x00160016}, |
| 84 | {0xa23c, 0x002a002b}, |
| 85 | {0xa240, 0x00000000}, |
| 86 | {0xa244, 0x00000000}, |
| 87 | {0xa248, 0x8000421e}, |
| 88 | {0} |
| 89 | }; |
| 90 | |
| 91 | static const struct gt_powermeter ivb_pm_gt1[] = { |
| 92 | {0xa800, 0x00000000}, |
| 93 | {0xa804, 0x00021c00}, |
| 94 | {0xa808, 0x00000403}, |
| 95 | {0xa80c, 0x02001700}, |
| 96 | {0xa810, 0x05000200}, |
| 97 | {0xa814, 0x00000000}, |
| 98 | {0xa818, 0x00690500}, |
| 99 | {0xa81c, 0x0000007f}, |
| 100 | {0xa820, 0x01002501}, |
| 101 | {0xa824, 0x00000300}, |
| 102 | {0xa828, 0x01000331}, |
| 103 | {0xa82c, 0x0000000c}, |
| 104 | {0xa830, 0x00010016}, |
| 105 | {0xa834, 0x01100101}, |
| 106 | {0xa838, 0x00010103}, |
| 107 | {0xa83c, 0x00041300}, |
| 108 | {0xa840, 0x00000b30}, |
| 109 | {0xa844, 0x00000000}, |
| 110 | {0xa848, 0x7f000000}, |
| 111 | {0xa84c, 0x05000008}, |
| 112 | {0xa850, 0x00000001}, |
| 113 | {0xa854, 0x00000004}, |
| 114 | {0xa858, 0x00000007}, |
| 115 | {0xa85c, 0x00000000}, |
| 116 | {0xa860, 0x00010000}, |
| 117 | {0xa248, 0x0000221e}, |
| 118 | {0xa900, 0x00000000}, |
| 119 | {0xa904, 0x00001c00}, |
| 120 | {0xa908, 0x00000000}, |
| 121 | {0xa90c, 0x06000000}, |
| 122 | {0xa910, 0x09000200}, |
| 123 | {0xa914, 0x00000000}, |
| 124 | {0xa918, 0x00590000}, |
| 125 | {0xa91c, 0x00000000}, |
| 126 | {0xa920, 0x04002501}, |
| 127 | {0xa924, 0x00000100}, |
| 128 | {0xa928, 0x03000410}, |
| 129 | {0xa92c, 0x00000000}, |
| 130 | {0xa930, 0x00020000}, |
| 131 | {0xa934, 0x02070106}, |
| 132 | {0xa938, 0x00010100}, |
| 133 | {0xa93c, 0x00401c00}, |
| 134 | {0xa940, 0x00000000}, |
| 135 | {0xa944, 0x00000000}, |
| 136 | {0xa948, 0x10000e00}, |
| 137 | {0xa94c, 0x02000004}, |
| 138 | {0xa950, 0x00000001}, |
| 139 | {0xa954, 0x00000004}, |
| 140 | {0xa960, 0x00060000}, |
| 141 | {0xaa3c, 0x00001c00}, |
| 142 | {0xaa54, 0x00000004}, |
| 143 | {0xaa60, 0x00060000}, |
| 144 | {0} |
| 145 | }; |
| 146 | |
| 147 | static const struct gt_powermeter ivb_pm_gt2[] = { |
| 148 | {0xa800, 0x10000000}, |
| 149 | {0xa804, 0x00033800}, |
| 150 | {0xa808, 0x00000902}, |
| 151 | {0xa80c, 0x0c002f00}, |
| 152 | {0xa810, 0x12000400}, |
| 153 | {0xa814, 0x00000000}, |
| 154 | {0xa818, 0x00d20800}, |
| 155 | {0xa81c, 0x00000002}, |
| 156 | {0xa820, 0x03004b02}, |
| 157 | {0xa824, 0x00000600}, |
| 158 | {0xa828, 0x07000773}, |
| 159 | {0xa82c, 0x00000000}, |
| 160 | {0xa830, 0x00010032}, |
| 161 | {0xa834, 0x1520040d}, |
| 162 | {0xa838, 0x00020105}, |
| 163 | {0xa83c, 0x00083700}, |
| 164 | {0xa840, 0x0000151d}, |
| 165 | {0xa844, 0x00000000}, |
| 166 | {0xa848, 0x20001b00}, |
| 167 | {0xa84c, 0x0a000010}, |
| 168 | {0xa850, 0x00000000}, |
| 169 | {0xa854, 0x00000008}, |
| 170 | {0xa858, 0x00000008}, |
| 171 | {0xa85c, 0x00000000}, |
| 172 | {0xa860, 0x00020000}, |
| 173 | {0xa248, 0x0000221e}, |
| 174 | {0xa900, 0x00000000}, |
| 175 | {0xa904, 0x00003500}, |
| 176 | {0xa908, 0x00000000}, |
| 177 | {0xa90c, 0x0c000000}, |
| 178 | {0xa910, 0x12000500}, |
| 179 | {0xa914, 0x00000000}, |
| 180 | {0xa918, 0x00b20000}, |
| 181 | {0xa91c, 0x00000000}, |
| 182 | {0xa920, 0x08004b02}, |
| 183 | {0xa924, 0x00000200}, |
| 184 | {0xa928, 0x07000820}, |
| 185 | {0xa92c, 0x00000000}, |
| 186 | {0xa930, 0x00030000}, |
| 187 | {0xa934, 0x050f020d}, |
| 188 | {0xa938, 0x00020300}, |
| 189 | {0xa93c, 0x00903900}, |
| 190 | {0xa940, 0x00000000}, |
| 191 | {0xa944, 0x00000000}, |
| 192 | {0xa948, 0x20001b00}, |
| 193 | {0xa94c, 0x0a000010}, |
| 194 | {0xa950, 0x00000000}, |
| 195 | {0xa954, 0x00000008}, |
| 196 | {0xa960, 0x00110000}, |
| 197 | {0xaa3c, 0x00003900}, |
| 198 | {0xaa54, 0x00000008}, |
| 199 | {0xaa60, 0x00110000}, |
| 200 | {0} |
| 201 | }; |
| 202 | |
| 203 | static const struct gt_powermeter ivb_pm_gt2_17w[] = { |
| 204 | {0xa800, 0x20000000}, |
| 205 | {0xa804, 0x000e3800}, |
| 206 | {0xa808, 0x00000806}, |
| 207 | {0xa80c, 0x0c002f00}, |
| 208 | {0xa810, 0x0c000800}, |
| 209 | {0xa814, 0x00000000}, |
| 210 | {0xa818, 0x00d20d00}, |
| 211 | {0xa81c, 0x000000ff}, |
| 212 | {0xa820, 0x03004b02}, |
| 213 | {0xa824, 0x00000600}, |
| 214 | {0xa828, 0x07000773}, |
| 215 | {0xa82c, 0x00000000}, |
| 216 | {0xa830, 0x00020032}, |
| 217 | {0xa834, 0x1520040d}, |
| 218 | {0xa838, 0x00020105}, |
| 219 | {0xa83c, 0x00083700}, |
| 220 | {0xa840, 0x000016ff}, |
| 221 | {0xa844, 0x00000000}, |
| 222 | {0xa848, 0xff000000}, |
| 223 | {0xa84c, 0x0a000010}, |
| 224 | {0xa850, 0x00000002}, |
| 225 | {0xa854, 0x00000008}, |
| 226 | {0xa858, 0x0000000f}, |
| 227 | {0xa85c, 0x00000000}, |
| 228 | {0xa860, 0x00020000}, |
| 229 | {0xa248, 0x0000221e}, |
| 230 | {0xa900, 0x00000000}, |
| 231 | {0xa904, 0x00003800}, |
| 232 | {0xa908, 0x00000000}, |
| 233 | {0xa90c, 0x0c000000}, |
| 234 | {0xa910, 0x12000800}, |
| 235 | {0xa914, 0x00000000}, |
| 236 | {0xa918, 0x00b20000}, |
| 237 | {0xa91c, 0x00000000}, |
| 238 | {0xa920, 0x08004b02}, |
| 239 | {0xa924, 0x00000300}, |
| 240 | {0xa928, 0x01000820}, |
| 241 | {0xa92c, 0x00000000}, |
| 242 | {0xa930, 0x00030000}, |
| 243 | {0xa934, 0x15150406}, |
| 244 | {0xa938, 0x00020300}, |
| 245 | {0xa93c, 0x00903900}, |
| 246 | {0xa940, 0x00000000}, |
| 247 | {0xa944, 0x00000000}, |
| 248 | {0xa948, 0x20001b00}, |
| 249 | {0xa94c, 0x0a000010}, |
| 250 | {0xa950, 0x00000000}, |
| 251 | {0xa954, 0x00000008}, |
| 252 | {0xa960, 0x00110000}, |
| 253 | {0xaa3c, 0x00003900}, |
| 254 | {0xaa54, 0x00000008}, |
| 255 | {0xaa60, 0x00110000}, |
| 256 | {0} |
| 257 | }; |
| 258 | |
| 259 | static const struct gt_powermeter ivb_pm_gt2_35w[] = { |
| 260 | {0xa800, 0x00000000}, |
| 261 | {0xa804, 0x00030400}, |
| 262 | {0xa808, 0x00000806}, |
| 263 | {0xa80c, 0x0c002f00}, |
| 264 | {0xa810, 0x0c000300}, |
| 265 | {0xa814, 0x00000000}, |
| 266 | {0xa818, 0x00d20d00}, |
| 267 | {0xa81c, 0x000000ff}, |
| 268 | {0xa820, 0x03004b02}, |
| 269 | {0xa824, 0x00000600}, |
| 270 | {0xa828, 0x07000773}, |
| 271 | {0xa82c, 0x00000000}, |
| 272 | {0xa830, 0x00020032}, |
| 273 | {0xa834, 0x1520040d}, |
| 274 | {0xa838, 0x00020105}, |
| 275 | {0xa83c, 0x00083700}, |
| 276 | {0xa840, 0x000016ff}, |
| 277 | {0xa844, 0x00000000}, |
| 278 | {0xa848, 0xff000000}, |
| 279 | {0xa84c, 0x0a000010}, |
| 280 | {0xa850, 0x00000001}, |
| 281 | {0xa854, 0x00000008}, |
| 282 | {0xa858, 0x00000008}, |
| 283 | {0xa85c, 0x00000000}, |
| 284 | {0xa860, 0x00020000}, |
| 285 | {0xa248, 0x0000221e}, |
| 286 | {0xa900, 0x00000000}, |
| 287 | {0xa904, 0x00003800}, |
| 288 | {0xa908, 0x00000000}, |
| 289 | {0xa90c, 0x0c000000}, |
| 290 | {0xa910, 0x12000800}, |
| 291 | {0xa914, 0x00000000}, |
| 292 | {0xa918, 0x00b20000}, |
| 293 | {0xa91c, 0x00000000}, |
| 294 | {0xa920, 0x08004b02}, |
| 295 | {0xa924, 0x00000300}, |
| 296 | {0xa928, 0x01000820}, |
| 297 | {0xa92c, 0x00000000}, |
| 298 | {0xa930, 0x00030000}, |
| 299 | {0xa934, 0x15150406}, |
| 300 | {0xa938, 0x00020300}, |
| 301 | {0xa93c, 0x00903900}, |
| 302 | {0xa940, 0x00000000}, |
| 303 | {0xa944, 0x00000000}, |
| 304 | {0xa948, 0x20001b00}, |
| 305 | {0xa94c, 0x0a000010}, |
| 306 | {0xa950, 0x00000000}, |
| 307 | {0xa954, 0x00000008}, |
| 308 | {0xa960, 0x00110000}, |
| 309 | {0xaa3c, 0x00003900}, |
| 310 | {0xaa54, 0x00000008}, |
| 311 | {0xaa60, 0x00110000}, |
| 312 | {0} |
| 313 | }; |
| 314 | |
| 315 | /* some vga option roms are used for several chipsets but they only have one |
| 316 | * PCI ID in their header. If we encounter such an option rom, we need to do |
| 317 | * the mapping ourselfes |
| 318 | */ |
| 319 | |
| 320 | u32 map_oprom_vendev(u32 vendev) |
| 321 | { |
| 322 | u32 new_vendev = vendev; |
| 323 | |
| 324 | /* none curently. */ |
| 325 | |
| 326 | return new_vendev; |
| 327 | } |
| 328 | |
| 329 | static struct resource *gtt_res = NULL; |
| 330 | |
| 331 | static inline u32 gtt_read(u32 reg) |
| 332 | { |
| 333 | return read32(gtt_res->base + reg); |
| 334 | } |
| 335 | |
| 336 | static inline void gtt_write(u32 reg, u32 data) |
| 337 | { |
| 338 | write32(gtt_res->base + reg, data); |
| 339 | } |
| 340 | |
| 341 | static inline void gtt_write_powermeter(const struct gt_powermeter *pm) |
| 342 | { |
| 343 | for (; pm && pm->reg; pm++) |
| 344 | gtt_write(pm->reg, pm->value); |
| 345 | } |
| 346 | |
| 347 | #define GTT_RETRY 1000 |
| 348 | static int gtt_poll(u32 reg, u32 mask, u32 value) |
| 349 | { |
| 350 | unsigned try = GTT_RETRY; |
| 351 | u32 data; |
| 352 | |
| 353 | while (try--) { |
| 354 | data = gtt_read(reg); |
| 355 | if ((data & mask) == value) |
| 356 | return 1; |
| 357 | udelay(10); |
| 358 | } |
| 359 | |
| 360 | printk(BIOS_ERR, "GT init timeout\n"); |
| 361 | return 0; |
| 362 | } |
| 363 | |
| 364 | static void gma_pm_init_pre_vbios(struct device *dev) |
| 365 | { |
| 366 | u32 reg32; |
| 367 | |
| 368 | printk(BIOS_DEBUG, "GT Power Management Init\n"); |
| 369 | |
| 370 | gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0); |
| 371 | if (!gtt_res || !gtt_res->base) |
| 372 | return; |
| 373 | |
| 374 | if (bridge_silicon_revision() < IVB_STEP_C0) { |
| 375 | /* 1: Enable force wake */ |
| 376 | gtt_write(0xa18c, 0x00000001); |
| 377 | gtt_poll(0x130090, (1 << 0), (1 << 0)); |
| 378 | } else { |
| 379 | gtt_write(0xa180, 1 << 5); |
| 380 | gtt_write(0xa188, 0xffff0001); |
| 381 | gtt_poll(0x130040, (1 << 0), (1 << 0)); |
| 382 | } |
| 383 | |
| 384 | if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) { |
| 385 | /* 1d: Set GTT+0x42004 [15:14]=11 (SnB C1+) */ |
| 386 | reg32 = gtt_read(0x42004); |
| 387 | reg32 |= (1 << 14) | (1 << 15); |
| 388 | gtt_write(0x42004, reg32); |
| 389 | } |
| 390 | |
| 391 | if (bridge_silicon_revision() >= IVB_STEP_A0) { |
| 392 | /* Display Reset Acknowledge Settings */ |
| 393 | reg32 = gtt_read(0x45010); |
| 394 | reg32 |= (1 << 1) | (1 << 0); |
| 395 | gtt_write(0x45010, reg32); |
| 396 | } |
| 397 | |
| 398 | /* 2: Get GT SKU from GTT+0x911c[13] */ |
| 399 | reg32 = gtt_read(0x911c); |
| 400 | if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) { |
| 401 | if (reg32 & (1 << 13)) { |
| 402 | printk(BIOS_DEBUG, "SNB GT1 Power Meter Weights\n"); |
| 403 | gtt_write_powermeter(snb_pm_gt1); |
| 404 | } else { |
| 405 | printk(BIOS_DEBUG, "SNB GT2 Power Meter Weights\n"); |
| 406 | gtt_write_powermeter(snb_pm_gt2); |
| 407 | } |
| 408 | } else { |
| 409 | u32 unit = MCHBAR32(0x5938) & 0xf; |
| 410 | |
| 411 | if (reg32 & (1 << 13)) { |
| 412 | /* GT1 SKU */ |
| 413 | printk(BIOS_DEBUG, "IVB GT1 Power Meter Weights\n"); |
| 414 | gtt_write_powermeter(ivb_pm_gt1); |
| 415 | } else { |
| 416 | /* GT2 SKU */ |
| 417 | u32 tdp = MCHBAR32(0x5930) & 0x7fff; |
| 418 | tdp /= (1 << unit); |
| 419 | |
| 420 | if (tdp <= 17) { |
| 421 | /* <=17W ULV */ |
| 422 | printk(BIOS_DEBUG, "IVB GT2 17W " |
| 423 | "Power Meter Weights\n"); |
| 424 | gtt_write_powermeter(ivb_pm_gt2_17w); |
| 425 | } else if ((tdp >= 25) && (tdp <= 35)) { |
| 426 | /* 25W-35W */ |
| 427 | printk(BIOS_DEBUG, "IVB GT2 25W-35W " |
| 428 | "Power Meter Weights\n"); |
| 429 | gtt_write_powermeter(ivb_pm_gt2_35w); |
| 430 | } else { |
| 431 | /* All others */ |
| 432 | printk(BIOS_DEBUG, "IVB GT2 35W " |
| 433 | "Power Meter Weights\n"); |
| 434 | gtt_write_powermeter(ivb_pm_gt2_35w); |
| 435 | } |
| 436 | } |
| 437 | } |
| 438 | |
| 439 | /* 3: Gear ratio map */ |
| 440 | gtt_write(0xa004, 0x00000010); |
| 441 | |
| 442 | /* 4: GFXPAUSE */ |
| 443 | gtt_write(0xa000, 0x00070020); |
| 444 | |
| 445 | /* 5: Dynamic EU trip control */ |
| 446 | gtt_write(0xa080, 0x00000004); |
| 447 | |
| 448 | /* 6: ECO bits */ |
| 449 | reg32 = gtt_read(0xa180); |
| 450 | reg32 |= (1 << 26) | (1 << 31); |
| 451 | /* (bit 20=1 for SNB step D1+ / IVB A0+) */ |
| 452 | if (bridge_silicon_revision() >= SNB_STEP_D1) |
| 453 | reg32 |= (1 << 20); |
| 454 | gtt_write(0xa180, reg32); |
| 455 | |
| 456 | /* 6a: for SnB step D2+ only */ |
| 457 | if (((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) && |
| 458 | (bridge_silicon_revision() >= SNB_STEP_D2)) { |
| 459 | reg32 = gtt_read(0x9400); |
| 460 | reg32 |= (1 << 7); |
| 461 | gtt_write(0x9400, reg32); |
| 462 | |
| 463 | reg32 = gtt_read(0x941c); |
| 464 | reg32 &= 0xf; |
| 465 | reg32 |= (1 << 1); |
| 466 | gtt_write(0x941c, reg32); |
| 467 | gtt_poll(0x941c, (1 << 1), (0 << 1)); |
| 468 | } |
| 469 | |
| 470 | if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_IVB) { |
| 471 | reg32 = gtt_read(0x907c); |
| 472 | reg32 |= (1 << 16); |
| 473 | gtt_write(0x907c, reg32); |
| 474 | |
| 475 | /* 6b: Clocking reset controls */ |
| 476 | gtt_write(0x9424, 0x00000001); |
| 477 | } else { |
| 478 | /* 6b: Clocking reset controls */ |
| 479 | gtt_write(0x9424, 0x00000000); |
| 480 | } |
| 481 | |
| 482 | /* 7 */ |
| 483 | if (gtt_poll(0x138124, (1 << 31), (0 << 31))) { |
| 484 | gtt_write(0x138128, 0x00000029); /* Mailbox Data */ |
| 485 | gtt_write(0x138124, 0x80000004); /* Mailbox Cmd for RC6 VID */ |
| 486 | if (gtt_poll(0x138124, (1 << 31), (0 << 31))) |
| 487 | gtt_write(0x138124, 0x8000000a); |
| 488 | gtt_poll(0x138124, (1 << 31), (0 << 31)); |
| 489 | } |
| 490 | |
| 491 | /* 8 */ |
| 492 | gtt_write(0xa090, 0x00000000); /* RC Control */ |
| 493 | gtt_write(0xa098, 0x03e80000); /* RC1e Wake Rate Limit */ |
| 494 | gtt_write(0xa09c, 0x0028001e); /* RC6/6p Wake Rate Limit */ |
| 495 | gtt_write(0xa0a0, 0x0000001e); /* RC6pp Wake Rate Limit */ |
| 496 | gtt_write(0xa0a8, 0x0001e848); /* RC Evaluation Interval */ |
| 497 | gtt_write(0xa0ac, 0x00000019); /* RC Idle Hysteresis */ |
| 498 | |
| 499 | /* 9 */ |
| 500 | gtt_write(0x2054, 0x0000000a); /* Render Idle Max Count */ |
| 501 | gtt_write(0x12054, 0x0000000a); /* Video Idle Max Count */ |
| 502 | gtt_write(0x22054, 0x0000000a); /* Blitter Idle Max Count */ |
| 503 | |
| 504 | /* 10 */ |
| 505 | gtt_write(0xa0b0, 0x00000000); /* Unblock Ack to Busy */ |
| 506 | gtt_write(0xa0b4, 0x000003e8); /* RC1e Threshold */ |
| 507 | gtt_write(0xa0b8, 0x0000c350); /* RC6 Threshold */ |
| 508 | gtt_write(0xa0bc, 0x000186a0); /* RC6p Threshold */ |
| 509 | gtt_write(0xa0c0, 0x0000fa00); /* RC6pp Threshold */ |
| 510 | |
| 511 | /* 11 */ |
| 512 | gtt_write(0xa010, 0x000f4240); /* RP Down Timeout */ |
| 513 | gtt_write(0xa014, 0x12060000); /* RP Interrupt Limits */ |
| 514 | gtt_write(0xa02c, 0x00015f90); /* RP Up Threshold */ |
| 515 | gtt_write(0xa030, 0x000186a0); /* RP Down Threshold */ |
| 516 | gtt_write(0xa068, 0x000186a0); /* RP Up EI */ |
| 517 | gtt_write(0xa06c, 0x000493e0); /* RP Down EI */ |
| 518 | gtt_write(0xa070, 0x0000000a); /* RP Idle Hysteresis */ |
| 519 | |
| 520 | /* 11a: Enable Render Standby (RC6) */ |
| 521 | if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_IVB) { |
| 522 | /* |
| 523 | * IvyBridge should also support DeepRenderStandby. |
| 524 | * |
| 525 | * Unfortunately it does not work reliably on all SKUs so |
| 526 | * disable it here and it can be enabled by the kernel. |
| 527 | */ |
| 528 | gtt_write(0xa090, 0x88040000); /* HW RC Control */ |
| 529 | } else { |
| 530 | gtt_write(0xa090, 0x88040000); /* HW RC Control */ |
| 531 | } |
| 532 | |
| 533 | /* 12: Normal Frequency Request */ |
| 534 | /* RPNFREQ_VAL comes from MCHBAR 0x5998 23:16 (8 bits!? use 7) */ |
| 535 | reg32 = MCHBAR32(0x5998); |
| 536 | reg32 >>= 16; |
| 537 | reg32 &= 0xef; |
| 538 | reg32 <<= 25; |
| 539 | gtt_write(0xa008, reg32); |
| 540 | |
| 541 | /* 13: RP Control */ |
| 542 | gtt_write(0xa024, 0x00000592); |
| 543 | |
| 544 | /* 14: Enable PM Interrupts */ |
| 545 | gtt_write(0x4402c, 0x03000076); |
| 546 | |
| 547 | /* Clear 0x6c024 [8:6] */ |
| 548 | reg32 = gtt_read(0x6c024); |
| 549 | reg32 &= ~0x000001c0; |
| 550 | gtt_write(0x6c024, reg32); |
| 551 | } |
| 552 | |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 553 | static void gma_pm_init_post_vbios(struct device *dev) |
| 554 | { |
| 555 | struct northbridge_intel_nehalem_config *conf = dev->chip_info; |
| 556 | u32 reg32; |
| 557 | |
| 558 | printk(BIOS_DEBUG, "GT Power Management Init (post VBIOS)\n"); |
| 559 | |
| 560 | /* 15: Deassert Force Wake */ |
| 561 | if (bridge_silicon_revision() < IVB_STEP_C0) { |
| 562 | gtt_write(0xa18c, gtt_read(0xa18c) & ~1); |
| 563 | gtt_poll(0x130090, (1 << 0), (0 << 0)); |
| 564 | } else { |
| 565 | gtt_write(0xa188, 0x1fffe); |
| 566 | if (gtt_poll(0x130040, (1 << 0), (0 << 0))) |
| 567 | gtt_write(0xa188, gtt_read(0xa188) | 1); |
| 568 | } |
| 569 | |
| 570 | /* 16: SW RC Control */ |
| 571 | gtt_write(0xa094, 0x00060000); |
| 572 | |
| 573 | /* Setup Digital Port Hotplug */ |
| 574 | reg32 = gtt_read(0xc4030); |
| 575 | if (!reg32) { |
| 576 | reg32 = (conf->gpu_dp_b_hotplug & 0x7) << 2; |
| 577 | reg32 |= (conf->gpu_dp_c_hotplug & 0x7) << 10; |
| 578 | reg32 |= (conf->gpu_dp_d_hotplug & 0x7) << 18; |
| 579 | gtt_write(0xc4030, reg32); |
| 580 | } |
| 581 | |
| 582 | /* Setup Panel Power On Delays */ |
| 583 | reg32 = gtt_read(0xc7208); |
| 584 | if (!reg32) { |
| 585 | reg32 = (conf->gpu_panel_port_select & 0x3) << 30; |
| 586 | reg32 |= (conf->gpu_panel_power_up_delay & 0x1fff) << 16; |
| 587 | reg32 |= (conf->gpu_panel_power_backlight_on_delay & 0x1fff); |
| 588 | gtt_write(0xc7208, reg32); |
| 589 | } |
| 590 | |
| 591 | /* Setup Panel Power Off Delays */ |
| 592 | reg32 = gtt_read(0xc720c); |
| 593 | if (!reg32) { |
| 594 | reg32 = (conf->gpu_panel_power_down_delay & 0x1fff) << 16; |
| 595 | reg32 |= (conf->gpu_panel_power_backlight_off_delay & 0x1fff); |
| 596 | gtt_write(0xc720c, reg32); |
| 597 | } |
| 598 | |
| 599 | /* Setup Panel Power Cycle Delay */ |
| 600 | if (conf->gpu_panel_power_cycle_delay) { |
| 601 | reg32 = gtt_read(0xc7210); |
| 602 | reg32 &= ~0xff; |
| 603 | reg32 |= conf->gpu_panel_power_cycle_delay & 0xff; |
| 604 | gtt_write(0xc7210, reg32); |
| 605 | } |
| 606 | |
| 607 | /* Enable Backlight if needed */ |
| 608 | if (conf->gpu_cpu_backlight) { |
| 609 | gtt_write(0x48250, (1 << 31)); |
| 610 | gtt_write(0x48254, conf->gpu_cpu_backlight); |
| 611 | } |
| 612 | if (conf->gpu_pch_backlight) { |
| 613 | gtt_write(0xc8250, (1 << 31)); |
| 614 | gtt_write(0xc8254, conf->gpu_pch_backlight); |
| 615 | } |
| 616 | } |
| 617 | |
Vladimir Serbinenko | 1315730 | 2014-02-19 22:18:08 +0100 | [diff] [blame] | 618 | #if IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) |
| 619 | |
| 620 | static void train_link(u32 mmio) |
| 621 | { |
| 622 | /* Clear interrupts. */ |
| 623 | write32(mmio + DEIIR, 0xffffffff); |
| 624 | |
| 625 | write32(mmio + 0x000f0018, 0x000000ff); |
| 626 | write32(mmio + 0x000f1018, 0x000000ff); |
| 627 | write32(mmio + 0x000f000c, 0x001a2050); |
| 628 | write32(mmio + 0x00060100, 0x001c4000); |
| 629 | write32(mmio + 0x00060100, 0x801c4000); |
| 630 | write32(mmio + 0x000f000c, 0x801a2050); |
| 631 | write32(mmio + 0x00060100, 0x801c4000); |
| 632 | write32(mmio + 0x000f000c, 0x801a2050); |
| 633 | mdelay(1); |
| 634 | |
| 635 | read32(mmio + 0x000f0014); // = 0x00000100 |
| 636 | write32(mmio + 0x000f0014, 0x00000100); |
| 637 | write32(mmio + 0x00060100, 0x901c4000); |
| 638 | write32(mmio + 0x000f000c, 0x901a2050); |
| 639 | mdelay(1); |
| 640 | read32(mmio + 0x000f0014); // = 0x00000600 |
| 641 | } |
| 642 | |
| 643 | static void power_port(u32 mmio) |
| 644 | { |
| 645 | read32(mmio + 0x000e1100); // = 0x00000000 |
| 646 | write32(mmio + 0x000e1100, 0x00000000); |
| 647 | write32(mmio + 0x000e1100, 0x00010000); |
| 648 | read32(mmio + 0x000e1100); // = 0x00010000 |
| 649 | read32(mmio + 0x000e1100); // = 0x00010000 |
| 650 | read32(mmio + 0x000e1100); // = 0x00000000 |
| 651 | write32(mmio + 0x000e1100, 0x00000000); |
| 652 | read32(mmio + 0x000e1100); // = 0x00000000 |
| 653 | read32(mmio + 0x000e4200); // = 0x0000001c |
| 654 | write32(mmio + 0x000e4210, 0x8004003e); |
| 655 | write32(mmio + 0x000e4214, 0x80060002); |
| 656 | write32(mmio + 0x000e4218, 0x01000000); |
| 657 | read32(mmio + 0x000e4210); // = 0x5144003e |
| 658 | write32(mmio + 0x000e4210, 0x5344003e); |
| 659 | read32(mmio + 0x000e4210); // = 0x0144003e |
| 660 | write32(mmio + 0x000e4210, 0x8074003e); |
| 661 | read32(mmio + 0x000e4210); // = 0x5144003e |
| 662 | read32(mmio + 0x000e4210); // = 0x5144003e |
| 663 | write32(mmio + 0x000e4210, 0x5344003e); |
| 664 | read32(mmio + 0x000e4210); // = 0x0144003e |
| 665 | write32(mmio + 0x000e4210, 0x8074003e); |
| 666 | read32(mmio + 0x000e4210); // = 0x5144003e |
| 667 | read32(mmio + 0x000e4210); // = 0x5144003e |
| 668 | write32(mmio + 0x000e4210, 0x5344003e); |
| 669 | read32(mmio + 0x000e4210); // = 0x0144003e |
| 670 | write32(mmio + 0x000e4210, 0x8074003e); |
| 671 | read32(mmio + 0x000e4210); // = 0x5144003e |
| 672 | read32(mmio + 0x000e4210); // = 0x5144003e |
| 673 | write32(mmio + 0x000e4210, 0x5344003e); |
| 674 | write32(mmio + 0x000e4f00, 0x0100030c); |
| 675 | write32(mmio + 0x000e4f04, 0x00b8230c); |
| 676 | write32(mmio + 0x000e4f08, 0x06f8930c); |
| 677 | write32(mmio + 0x000e4f0c, 0x09f8e38e); |
| 678 | write32(mmio + 0x000e4f10, 0x00b8030c); |
| 679 | write32(mmio + 0x000e4f14, 0x0b78830c); |
| 680 | write32(mmio + 0x000e4f18, 0x0ff8d3cf); |
| 681 | write32(mmio + 0x000e4f1c, 0x01e8030c); |
| 682 | write32(mmio + 0x000e4f20, 0x0ff863cf); |
| 683 | write32(mmio + 0x000e4f24, 0x0ff803cf); |
| 684 | write32(mmio + 0x000c4030, 0x00001000); |
| 685 | read32(mmio + 0x000c4000); // = 0x00000000 |
| 686 | write32(mmio + 0x000c4030, 0x00001000); |
| 687 | read32(mmio + 0x000e1150); // = 0x0000001c |
| 688 | write32(mmio + 0x000e1150, 0x0000089c); |
| 689 | write32(mmio + 0x000fcc00, 0x01986f00); |
| 690 | write32(mmio + 0x000fcc0c, 0x01986f00); |
| 691 | write32(mmio + 0x000fcc18, 0x01986f00); |
| 692 | write32(mmio + 0x000fcc24, 0x01986f00); |
| 693 | read32(mmio + 0x000c4000); // = 0x00000000 |
| 694 | read32(mmio + 0x000e1180); // = 0x40000002 |
| 695 | } |
| 696 | |
| 697 | static void intel_gma_init(const struct northbridge_intel_nehalem_config *info, |
| 698 | u32 mmio, u32 physbase, u16 piobase, u32 lfb) |
| 699 | { |
| 700 | int i; |
| 701 | u8 edid_data[128]; |
| 702 | struct edid edid; |
| 703 | u32 hactive, vactive, right_border, bottom_border; |
| 704 | int hpolarity, vpolarity; |
| 705 | u32 vsync, hsync, vblank, hblank, hfront_porch, vfront_porch; |
| 706 | u32 candp1, candn; |
| 707 | u32 best_delta = 0xffffffff; |
| 708 | u32 target_frequency; |
| 709 | u32 pixel_p1 = 1; |
| 710 | u32 pixel_n = 1; |
| 711 | u32 pixel_m1 = 1; |
| 712 | u32 pixel_m2 = 1; |
| 713 | u32 link_frequency = info->gpu_link_frequency_270_mhz ? 270000 : 162000; |
| 714 | u32 data_m1; |
| 715 | u32 data_n1 = 0x00800000; |
| 716 | u32 link_m1; |
| 717 | u32 link_n1 = 0x00080000; |
| 718 | |
| 719 | write32(mmio + 0x00070080, 0x00000000); |
| 720 | write32(mmio + DSPCNTR(0), 0x00000000); |
| 721 | write32(mmio + 0x00071180, 0x00000000); |
| 722 | write32(mmio + CPU_VGACNTRL, 0x0000298e | VGA_DISP_DISABLE); |
| 723 | write32(mmio + 0x0007019c, 0x00000000); |
| 724 | write32(mmio + 0x0007119c, 0x00000000); |
| 725 | write32(mmio + 0x000fc008, 0x2c010000); |
| 726 | write32(mmio + 0x000fc020, 0x2c010000); |
| 727 | write32(mmio + 0x000fc038, 0x2c010000); |
| 728 | write32(mmio + 0x000fc050, 0x2c010000); |
| 729 | write32(mmio + 0x000fc408, 0x2c010000); |
| 730 | write32(mmio + 0x000fc420, 0x2c010000); |
| 731 | write32(mmio + 0x000fc438, 0x2c010000); |
| 732 | write32(mmio + 0x000fc450, 0x2c010000); |
| 733 | vga_gr_write(0x18, 0); |
| 734 | write32(mmio + 0x00042004, 0x02000000); |
| 735 | write32(mmio + 0x000fd034, 0x8421ffe0); |
| 736 | |
| 737 | /* Setup GTT. */ |
| 738 | for (i = 0; i < 0x2000; i++) |
| 739 | { |
| 740 | outl((i << 2) | 1, piobase); |
| 741 | outl(physbase + (i << 12) + 1, piobase + 4); |
| 742 | } |
| 743 | |
| 744 | vga_misc_write(0x67); |
| 745 | |
| 746 | const u8 cr[] = { 0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f, |
| 747 | 0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00, |
| 748 | 0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3, |
| 749 | 0xff |
| 750 | }; |
| 751 | vga_cr_write(0x11, 0); |
| 752 | |
| 753 | for (i = 0; i <= 0x18; i++) |
| 754 | vga_cr_write(i, cr[i]); |
| 755 | |
| 756 | power_port(mmio); |
| 757 | |
| 758 | intel_gmbus_read_edid(mmio + PCH_GMBUS0, 3, 0x50, edid_data, 128); |
| 759 | decode_edid(edid_data, |
| 760 | sizeof(edid_data), &edid); |
| 761 | |
| 762 | /* Disable screen memory to prevent garbage from appearing. */ |
| 763 | vga_sr_write(1, vga_sr_read(1) | 0x20); |
| 764 | |
| 765 | hactive = edid.x_resolution; |
| 766 | vactive = edid.y_resolution; |
| 767 | right_border = edid.hborder; |
| 768 | bottom_border = edid.vborder; |
| 769 | hpolarity = (edid.phsync == '-'); |
| 770 | vpolarity = (edid.pvsync == '-'); |
| 771 | vsync = edid.vspw; |
| 772 | hsync = edid.hspw; |
| 773 | vblank = edid.vbl; |
| 774 | hblank = edid.hbl; |
| 775 | hfront_porch = edid.hso; |
| 776 | vfront_porch = edid.vso; |
| 777 | |
| 778 | target_frequency = info->gpu_lvds_dual_channel ? edid.pixel_clock |
| 779 | : (2 * edid.pixel_clock); |
| 780 | #if !IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) |
| 781 | vga_textmode_init(); |
| 782 | #else |
| 783 | vga_sr_write(1, 1); |
| 784 | vga_sr_write(0x2, 0xf); |
| 785 | vga_sr_write(0x3, 0x0); |
| 786 | vga_sr_write(0x4, 0xe); |
| 787 | vga_gr_write(0, 0x0); |
| 788 | vga_gr_write(1, 0x0); |
| 789 | vga_gr_write(2, 0x0); |
| 790 | vga_gr_write(3, 0x0); |
| 791 | vga_gr_write(4, 0x0); |
| 792 | vga_gr_write(5, 0x0); |
| 793 | vga_gr_write(6, 0x5); |
| 794 | vga_gr_write(7, 0xf); |
| 795 | vga_gr_write(0x10, 0x1); |
| 796 | vga_gr_write(0x11, 0); |
| 797 | |
| 798 | |
| 799 | edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63; |
| 800 | |
| 801 | write32(mmio + DSPCNTR(0), DISPPLANE_BGRX888); |
| 802 | write32(mmio + DSPADDR(0), 0); |
| 803 | write32(mmio + DSPSTRIDE(0), edid.bytes_per_line); |
| 804 | write32(mmio + DSPSURF(0), 0); |
| 805 | for (i = 0; i < 0x100; i++) |
| 806 | write32(mmio + LGC_PALETTE(0) + 4 * i, i * 0x010101); |
| 807 | #endif |
| 808 | |
| 809 | /* Find suitable divisors. */ |
| 810 | for (candp1 = 1; candp1 <= 8; candp1++) { |
| 811 | for (candn = 5; candn <= 10; candn++) { |
| 812 | u32 cur_frequency; |
| 813 | u32 m; /* 77 - 131. */ |
| 814 | u32 denom; /* 35 - 560. */ |
| 815 | u32 current_delta; |
| 816 | |
| 817 | denom = candn * candp1 * 7; |
| 818 | /* Doesnt overflow for up to |
| 819 | 5000000 kHz = 5 GHz. */ |
| 820 | m = (target_frequency * denom + 60000) / 120000; |
| 821 | |
| 822 | if (m < 77 || m > 131) |
| 823 | continue; |
| 824 | |
| 825 | cur_frequency = (120000 * m) / denom; |
| 826 | if (target_frequency > cur_frequency) |
| 827 | current_delta = target_frequency - cur_frequency; |
| 828 | else |
| 829 | current_delta = cur_frequency - target_frequency; |
| 830 | |
| 831 | |
| 832 | if (best_delta > current_delta) { |
| 833 | best_delta = current_delta; |
| 834 | pixel_n = candn; |
| 835 | pixel_p1 = candp1; |
| 836 | pixel_m2 = ((m + 3) % 5) + 7; |
| 837 | pixel_m1 = (m - pixel_m2) / 5; |
| 838 | } |
| 839 | } |
| 840 | } |
| 841 | |
| 842 | if (best_delta == 0xffffffff) { |
| 843 | printk (BIOS_ERR, "Couldn't find GFX clock divisors\n"); |
| 844 | return; |
| 845 | } |
| 846 | |
| 847 | link_m1 = ((uint64_t)link_n1 * edid.pixel_clock) / link_frequency; |
| 848 | data_m1 = ((uint64_t)data_n1 * 18 * edid.pixel_clock) |
| 849 | / (link_frequency * 8 * (info->gpu_lvds_num_lanes ? : 4)); |
| 850 | |
| 851 | printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n", |
| 852 | hactive, vactive); |
| 853 | printk(BIOS_DEBUG, "Borders %d x %d\n", |
| 854 | right_border, bottom_border); |
| 855 | printk(BIOS_DEBUG, "Blank %d x %d\n", |
| 856 | hblank, vblank); |
| 857 | printk(BIOS_DEBUG, "Sync %d x %d\n", |
| 858 | hsync, vsync); |
| 859 | printk(BIOS_DEBUG, "Front porch %d x %d\n", |
| 860 | hfront_porch, vfront_porch); |
| 861 | printk(BIOS_DEBUG, (info->gpu_use_spread_spectrum_clock |
| 862 | ? "Spread spectrum clock\n" : "DREF clock\n")); |
| 863 | printk(BIOS_DEBUG, |
| 864 | info->gpu_lvds_dual_channel ? "Dual channel\n" : "Single channel\n"); |
| 865 | printk(BIOS_DEBUG, "Polarities %d, %d\n", |
| 866 | hpolarity, vpolarity); |
| 867 | printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n", |
| 868 | data_m1, data_n1); |
| 869 | printk(BIOS_DEBUG, "Link frequency %d kHz\n", |
| 870 | link_frequency); |
| 871 | printk(BIOS_DEBUG, "Link M1=%d, N1=%d\n", |
| 872 | link_m1, link_n1); |
| 873 | printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n", |
| 874 | pixel_n, pixel_m1, pixel_m2, pixel_p1); |
| 875 | printk(BIOS_DEBUG, "Pixel clock %d kHz\n", |
| 876 | 120000 * (5 * pixel_m1 + pixel_m2) / pixel_n |
| 877 | / (pixel_p1 * 7)); |
| 878 | |
| 879 | write32(mmio + PCH_LVDS, |
| 880 | (hpolarity << 20) | (vpolarity << 21) |
| 881 | | (info->gpu_lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL |
| 882 | | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) |
| 883 | | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL |
| 884 | | LVDS_DETECTED); |
| 885 | write32(mmio + BLC_PWM_CPU_CTL2, (1 << 31)); |
| 886 | write32(mmio + PCH_DREF_CONTROL, (info->gpu_use_spread_spectrum_clock |
| 887 | ? 0x1002 : 0x400)); |
| 888 | mdelay(1); |
| 889 | write32(mmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS |
| 890 | | (read32(mmio + PCH_PP_CONTROL) & ~PANEL_UNLOCK_MASK)); |
| 891 | write32(mmio + _PCH_FP0(0), |
| 892 | ((pixel_n - 2) << 16) |
| 893 | | ((pixel_m1 - 2) << 8) | pixel_m2); |
| 894 | write32(mmio + _PCH_DPLL(0), |
| 895 | DPLL_VCO_ENABLE | DPLLB_MODE_LVDS |
| 896 | | (info->gpu_lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 |
| 897 | : DPLLB_LVDS_P2_CLOCK_DIV_14) |
| 898 | | (0x10000 << (pixel_p1 - 1)) |
| 899 | | ((info->gpu_use_spread_spectrum_clock ? 3 : 0) << 13) |
| 900 | | (0x1 << (pixel_p1 - 1))); |
| 901 | mdelay(1); |
| 902 | write32(mmio + _PCH_DPLL(0), |
| 903 | DPLL_VCO_ENABLE | DPLLB_MODE_LVDS |
| 904 | | (info->gpu_lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 |
| 905 | : DPLLB_LVDS_P2_CLOCK_DIV_14) |
| 906 | | (0x10000 << (pixel_p1 - 1)) |
| 907 | | ((info->gpu_use_spread_spectrum_clock ? 3 : 0) << 13) |
| 908 | | (0x1 << (pixel_p1 - 1))); |
| 909 | /* Re-lock the registers. */ |
| 910 | write32(mmio + PCH_PP_CONTROL, |
| 911 | (read32(mmio + PCH_PP_CONTROL) & ~PANEL_UNLOCK_MASK)); |
| 912 | |
| 913 | write32(mmio + PCH_LVDS, |
| 914 | (hpolarity << 20) | (vpolarity << 21) |
| 915 | | (info->gpu_lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL |
| 916 | | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) |
| 917 | | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL |
| 918 | | LVDS_DETECTED); |
| 919 | |
| 920 | write32(mmio + HTOTAL(0), |
| 921 | ((hactive + right_border + hblank - 1) << 16) |
| 922 | | (hactive - 1)); |
| 923 | write32(mmio + HBLANK(0), |
| 924 | ((hactive + right_border + hblank - 1) << 16) |
| 925 | | (hactive + right_border - 1)); |
| 926 | write32(mmio + HSYNC(0), |
| 927 | ((hactive + right_border + hfront_porch + hsync - 1) << 16) |
| 928 | | (hactive + right_border + hfront_porch - 1)); |
| 929 | |
| 930 | write32(mmio + VTOTAL(0), ((vactive + bottom_border + vblank - 1) << 16) |
| 931 | | (vactive - 1)); |
| 932 | write32(mmio + VBLANK(0), ((vactive + bottom_border + vblank - 1) << 16) |
| 933 | | (vactive + bottom_border - 1)); |
| 934 | write32(mmio + VSYNC(0), |
| 935 | (vactive + bottom_border + vfront_porch + vsync - 1) |
| 936 | | (vactive + bottom_border + vfront_porch - 1)); |
| 937 | |
| 938 | write32(mmio + PIPECONF(0), PIPECONF_DISABLE); |
| 939 | |
| 940 | write32(mmio + PF_WIN_POS(0), 0); |
| 941 | #if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) |
| 942 | write32(mmio + PIPESRC(0), ((hactive - 1) << 16) | (vactive - 1)); |
| 943 | write32(mmio + PF_CTL(0),0); |
| 944 | write32(mmio + PF_WIN_SZ(0), 0); |
| 945 | #else |
| 946 | write32(mmio + PIPESRC(0), (639 << 16) | 399); |
| 947 | write32(mmio + PF_CTL(0),PF_ENABLE | PF_FILTER_MED_3x3); |
| 948 | write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); |
| 949 | #endif |
| 950 | |
| 951 | mdelay(1); |
| 952 | |
| 953 | write32(mmio + PIPE_DATA_M1(0), 0x7e000000 | data_m1); |
| 954 | write32(mmio + PIPE_DATA_N1(0), data_n1); |
| 955 | write32(mmio + PIPE_LINK_M1(0), link_m1); |
| 956 | write32(mmio + PIPE_LINK_N1(0), link_n1); |
| 957 | |
| 958 | write32(mmio + 0x000f000c, 0x00002040); |
| 959 | mdelay(1); |
| 960 | write32(mmio + 0x000f000c, 0x00002050); |
| 961 | write32(mmio + 0x00060100, 0x00044000); |
| 962 | mdelay(1); |
| 963 | write32(mmio + PIPECONF(0), PIPECONF_BPP_6); |
| 964 | write32(mmio + 0x000f0008, 0x00000040); |
| 965 | write32(mmio + 0x000f000c, 0x00022050); |
| 966 | write32(mmio + PIPECONF(0), PIPECONF_BPP_6 | PIPECONF_DITHER_EN); |
| 967 | write32(mmio + PIPECONF(0), PIPECONF_ENABLE | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); |
| 968 | |
| 969 | #if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) |
| 970 | write32(mmio + CPU_VGACNTRL, 0x20298e | VGA_DISP_DISABLE); |
| 971 | #else |
| 972 | write32(mmio + CPU_VGACNTRL, 0x20298e); |
| 973 | #endif |
| 974 | train_link(mmio); |
| 975 | |
| 976 | #if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) |
| 977 | write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); |
| 978 | mdelay(1); |
| 979 | #endif |
| 980 | |
| 981 | write32(mmio + TRANS_HTOTAL(0), |
| 982 | ((hactive + right_border + hblank - 1) << 16) |
| 983 | | (hactive - 1)); |
| 984 | write32(mmio + TRANS_HBLANK(0), |
| 985 | ((hactive + right_border + hblank - 1) << 16) |
| 986 | | (hactive + right_border - 1)); |
| 987 | write32(mmio + TRANS_HSYNC(0), |
| 988 | ((hactive + right_border + hfront_porch + hsync - 1) << 16) |
| 989 | | (hactive + right_border + hfront_porch - 1)); |
| 990 | |
| 991 | write32(mmio + TRANS_VTOTAL(0), |
| 992 | ((vactive + bottom_border + vblank - 1) << 16) |
| 993 | | (vactive - 1)); |
| 994 | write32(mmio + TRANS_VBLANK(0), |
| 995 | ((vactive + bottom_border + vblank - 1) << 16) |
| 996 | | (vactive + bottom_border - 1)); |
| 997 | write32(mmio + TRANS_VSYNC(0), |
| 998 | (vactive + bottom_border + vfront_porch + vsync - 1) |
| 999 | | (vactive + bottom_border + vfront_porch - 1)); |
| 1000 | |
| 1001 | write32(mmio + 0x00060100, 0xb01c4000); |
| 1002 | write32(mmio + 0x000f000c, 0xb01a2050); |
| 1003 | mdelay(1); |
| 1004 | write32(mmio + TRANSCONF(0), TRANS_ENABLE | TRANS_6BPC |
| 1005 | #if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) |
| 1006 | | TRANS_STATE_MASK |
| 1007 | #endif |
| 1008 | ); |
| 1009 | write32(mmio + PCH_LVDS, |
| 1010 | LVDS_PORT_ENABLE |
| 1011 | | (hpolarity << 20) | (vpolarity << 21) |
| 1012 | | (info->gpu_lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL |
| 1013 | | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) |
| 1014 | | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL |
| 1015 | | LVDS_DETECTED); |
| 1016 | |
| 1017 | write32(mmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS | PANEL_POWER_OFF); |
| 1018 | write32(mmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS | PANEL_POWER_RESET); |
| 1019 | mdelay(1); |
| 1020 | write32(mmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS |
| 1021 | | PANEL_POWER_ON | PANEL_POWER_RESET); |
| 1022 | |
| 1023 | printk (BIOS_DEBUG, "waiting for panel powerup\n"); |
| 1024 | while (1) { |
| 1025 | u32 reg32; |
| 1026 | reg32 = read32(mmio + PCH_PP_STATUS); |
| 1027 | if (((reg32 >> 28) & 3) == 0) |
| 1028 | break; |
| 1029 | } |
| 1030 | printk (BIOS_DEBUG, "panel powered up\n"); |
| 1031 | |
| 1032 | write32(mmio + PCH_PP_CONTROL, PANEL_POWER_ON | PANEL_POWER_RESET); |
| 1033 | |
| 1034 | /* Enable screen memory. */ |
| 1035 | vga_sr_write(1, vga_sr_read(1) & ~0x20); |
| 1036 | |
| 1037 | /* Clear interrupts. */ |
| 1038 | write32(mmio + DEIIR, 0xffffffff); |
| 1039 | write32(mmio + SDEIIR, 0xffffffff); |
| 1040 | |
| 1041 | #if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) |
| 1042 | memset ((void *) lfb, 0, edid.x_resolution * edid.y_resolution * 4); |
| 1043 | set_vbe_mode_info_valid(&edid, lfb); |
| 1044 | #endif |
| 1045 | } |
| 1046 | |
| 1047 | #endif |
| 1048 | |
| 1049 | |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1050 | static void gma_func0_init(struct device *dev) |
| 1051 | { |
| 1052 | u32 reg32; |
| 1053 | |
| 1054 | /* IGD needs to be Bus Master */ |
| 1055 | reg32 = pci_read_config32(dev, PCI_COMMAND); |
| 1056 | reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; |
| 1057 | pci_write_config32(dev, PCI_COMMAND, reg32); |
| 1058 | |
| 1059 | /* Init graphics power management */ |
| 1060 | gma_pm_init_pre_vbios(dev); |
| 1061 | |
| 1062 | #if !CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT |
| 1063 | /* PCI Init, will run VBIOS */ |
| 1064 | pci_dev_init(dev); |
| 1065 | #else |
Vladimir Serbinenko | 1315730 | 2014-02-19 22:18:08 +0100 | [diff] [blame] | 1066 | u32 physbase; |
| 1067 | struct northbridge_intel_nehalem_config *conf = dev->chip_info; |
| 1068 | struct resource *lfb_res; |
| 1069 | struct resource *pio_res; |
| 1070 | |
| 1071 | lfb_res = find_resource(dev, PCI_BASE_ADDRESS_2); |
| 1072 | pio_res = find_resource(dev, PCI_BASE_ADDRESS_4); |
| 1073 | |
| 1074 | physbase = pci_read_config32(dev, 0x5c) & ~0xf; |
| 1075 | |
| 1076 | if (gtt_res && gtt_res->base && physbase && pio_res && pio_res->base |
| 1077 | && lfb_res && lfb_res->base) { |
| 1078 | printk(BIOS_SPEW, "Initializing VGA without OPROM. MMIO 0x%llx\n", |
| 1079 | gtt_res->base); |
| 1080 | intel_gma_init(conf, gtt_res->base, physbase, pio_res->base, |
| 1081 | lfb_res->base); |
| 1082 | } |
Vladimir Serbinenko | 503e4fe | 2014-01-03 04:27:39 +0100 | [diff] [blame] | 1083 | #endif |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1084 | |
| 1085 | /* Linux relies on VBT for panel info. */ |
| 1086 | if (read16(0xc0000) != 0xaa55) { |
| 1087 | optionrom_header_t *oh = (void *)0xc0000; |
| 1088 | optionrom_pcir_t *pcir; |
| 1089 | int sz; |
| 1090 | |
| 1091 | memset(oh->reserved, 0, 8192); |
| 1092 | |
| 1093 | sz = (0x80 + sizeof(fake_vbt) + 511) / 512; |
| 1094 | oh->signature = 0xaa55; |
| 1095 | oh->size = sz; |
| 1096 | oh->pcir_offset = 0x40; |
| 1097 | oh->vbt_offset = 0x80; |
| 1098 | |
| 1099 | pcir = (void *)0xc0040; |
| 1100 | pcir->signature = 0x52494350; // PCIR |
| 1101 | pcir->vendor = dev->vendor; |
| 1102 | pcir->device = dev->device; |
| 1103 | pcir->length = sizeof(*pcir); |
| 1104 | pcir->revision = dev->class; |
| 1105 | pcir->classcode[0] = dev->class >> 8; |
| 1106 | pcir->classcode[1] = dev->class >> 16; |
| 1107 | pcir->classcode[2] = dev->class >> 24; |
| 1108 | pcir->imagelength = sz; |
| 1109 | pcir->indicator = 0x80; |
| 1110 | |
| 1111 | memcpy((void *)0xc0080, fake_vbt, sizeof(fake_vbt)); |
| 1112 | } |
| 1113 | |
| 1114 | |
| 1115 | /* Post VBIOS init */ |
| 1116 | gma_pm_init_post_vbios(dev); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1117 | } |
| 1118 | |
| 1119 | static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device) |
| 1120 | { |
| 1121 | if (!vendor || !device) { |
| 1122 | pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, |
| 1123 | pci_read_config32(dev, PCI_VENDOR_ID)); |
| 1124 | } else { |
| 1125 | pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, |
| 1126 | ((device & 0xffff) << 16) | (vendor & |
| 1127 | 0xffff)); |
| 1128 | } |
| 1129 | } |
| 1130 | |
| 1131 | static void gma_read_resources(struct device *dev) |
| 1132 | { |
| 1133 | pci_dev_read_resources(dev); |
| 1134 | |
| 1135 | struct resource *res; |
| 1136 | |
| 1137 | /* Set the graphics memory to write combining. */ |
| 1138 | res = find_resource(dev, PCI_BASE_ADDRESS_2); |
| 1139 | if (res == NULL) { |
| 1140 | printk(BIOS_DEBUG, "gma: memory resource not found.\n"); |
| 1141 | return; |
| 1142 | } |
| 1143 | res->flags |= IORESOURCE_RESERVE | IORESOURCE_FIXED | IORESOURCE_ASSIGNED; |
| 1144 | pci_write_config32(dev, PCI_BASE_ADDRESS_2, |
| 1145 | 0xd0000001); |
| 1146 | pci_write_config32(dev, PCI_BASE_ADDRESS_2 + 4, |
| 1147 | 0); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1148 | res->base = (resource_t) 0xd0000000; |
| 1149 | res->size = (resource_t) 0x10000000; |
| 1150 | } |
| 1151 | |
| 1152 | static struct pci_operations gma_pci_ops = { |
| 1153 | .set_subsystem = gma_set_subsystem, |
| 1154 | }; |
| 1155 | |
| 1156 | static struct device_operations gma_func0_ops = { |
| 1157 | .read_resources = gma_read_resources, |
| 1158 | .set_resources = pci_dev_set_resources, |
| 1159 | .enable_resources = pci_dev_enable_resources, |
| 1160 | .init = gma_func0_init, |
| 1161 | .scan_bus = 0, |
| 1162 | .enable = 0, |
| 1163 | .ops_pci = &gma_pci_ops, |
| 1164 | }; |
| 1165 | |
| 1166 | static const unsigned short pci_device_ids[] = |
| 1167 | { 0x0046, 0x0102, 0x0106, 0x010a, 0x0112, |
| 1168 | 0x0116, 0x0122, 0x0126, 0x0156, |
| 1169 | 0x0166, |
| 1170 | 0 |
| 1171 | }; |
| 1172 | |
| 1173 | static const struct pci_driver gma __pci_driver = { |
| 1174 | .ops = &gma_func0_ops, |
| 1175 | .vendor = PCI_VENDOR_ID_INTEL, |
| 1176 | .devices = pci_device_ids, |
| 1177 | }; |