Anton Kochkov | 7c634ae | 2011-06-20 23:14:22 +0400 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of msrtool. |
| 3 | * |
| 4 | * Copyright (C) 2011 Anton Kochkov <anton.kochkov@gmail.com> |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License version 2 as |
| 8 | * published by the Free Software Foundation. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | */ |
| 19 | |
| 20 | #include "msrtool.h" |
| 21 | |
| 22 | int intel_pentium3_early_probe(const struct targetdef *target) { |
| 23 | struct cpuid_t *id = cpuid(); |
Anton Kochkov | ffbbecc | 2012-07-04 07:31:37 +0400 | [diff] [blame] | 24 | return ((0x6 == id->family) && ( |
| 25 | (0x7 == id->model) || |
| 26 | (0x8 == id->model) |
| 27 | )); |
Anton Kochkov | 7c634ae | 2011-06-20 23:14:22 +0400 | [diff] [blame] | 28 | } |
| 29 | |
| 30 | const struct msrdef intel_pentium3_early_msrs[] = { |
| 31 | {0x0, MSRTYPE_RDWR, MSR2(0,0), "IA32_P5_MC_ADDR", "", { |
| 32 | { BITS_EOT } |
| 33 | }}, |
| 34 | {0x1, MSRTYPE_RDWR, MSR2(0,0), "IA32_P5_MC_TYPE", "", { |
| 35 | { BITS_EOT } |
| 36 | }}, |
| 37 | {0x10, MSRTYPE_RDWR, MSR2(0,0), "IA32_TIME_STAMP_COUNTER", "", { |
| 38 | { BITS_EOT } |
| 39 | }}, |
| 40 | {0x17, MSRTYPE_RDWR, MSR2(0,0), "IA32_PLATFORM_ID", "", { |
| 41 | { BITS_EOT } |
| 42 | }}, |
| 43 | {0x1b, MSRTYPE_RDWR, MSR2(0,0), "IA32_APIC_BASE", "", { |
| 44 | { BITS_EOT } |
| 45 | }}, |
| 46 | {0x2a, MSRTYPE_RDWR, MSR2(0,0), "EBL_CR_POWERON", "", { |
| 47 | { BITS_EOT } |
| 48 | }}, |
| 49 | {0x33, MSRTYPE_RDWR, MSR2(0,0), "TEST_CTL", "", { |
| 50 | { BITS_EOT } |
| 51 | }}, |
| 52 | {0x88, MSRTYPE_RDWR, MSR2(0,0), "BBL_CR_D0", "", { |
| 53 | { BITS_EOT } |
| 54 | }}, |
| 55 | {0x89, MSRTYPE_RDWR, MSR2(0,0), "BBL_CR_D1", "", { |
| 56 | { BITS_EOT } |
| 57 | }}, |
| 58 | {0x8a, MSRTYPE_RDWR, MSR2(0,0), "BBL_CR_D2", "", { |
| 59 | { BITS_EOT } |
| 60 | }}, |
| 61 | {0x8b, MSRTYPE_RDWR, MSR2(0,0), "IA32_BIOS_SIGN_ID", "", { |
| 62 | { BITS_EOT } |
| 63 | }}, |
| 64 | {0xc1, MSRTYPE_RDWR, MSR2(0,0), "PERFCTR0", "", { |
| 65 | { BITS_EOT } |
| 66 | }}, |
| 67 | {0xc2, MSRTYPE_RDWR, MSR2(0,0), "PERFCTR1", "", { |
| 68 | { BITS_EOT } |
| 69 | }}, |
| 70 | {0xfe, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRRCAP", "", { |
| 71 | { BITS_EOT } |
| 72 | }}, |
| 73 | {0x116, MSRTYPE_RDWR, MSR2(0,0), "BBL_CR_ADDR", "", { |
| 74 | { BITS_EOT } |
| 75 | }}, |
| 76 | {0x118, MSRTYPE_RDWR, MSR2(0,0), "BBL_CR_DECC", "", { |
| 77 | { BITS_EOT } |
| 78 | }}, |
| 79 | {0x119, MSRTYPE_RDWR, MSR2(0,0), "BBL_CR_CTL", "", { |
| 80 | { BITS_EOT } |
| 81 | }}, |
| 82 | {0x11b, MSRTYPE_RDWR, MSR2(0,0), "BBL_CR_BUSY", "", { |
| 83 | { BITS_EOT } |
| 84 | }}, |
| 85 | {0x11e, MSRTYPE_RDWR, MSR2(0,0), "BBL_CR_CTL3", "", { |
| 86 | { BITS_EOT } |
| 87 | }}, |
| 88 | {0x174, MSRTYPE_RDWR, MSR2(0,0), "IA32_SYSENTER_CS", "", { |
| 89 | { BITS_EOT } |
| 90 | }}, |
| 91 | {0x175, MSRTYPE_RDWR, MSR2(0,0), "IA32_SYSENTER_ESP", "", { |
| 92 | { BITS_EOT } |
| 93 | }}, |
| 94 | {0x176, MSRTYPE_RDWR, MSR2(0,0), "IA32_SYSENTER_EIP", "", { |
| 95 | { BITS_EOT } |
| 96 | }}, |
| 97 | {0x179, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCG_CAP", "", { |
| 98 | { BITS_EOT } |
| 99 | }}, |
| 100 | {0x17a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCG_STATUS", "", { |
| 101 | { BITS_EOT } |
| 102 | }}, |
| 103 | {0x17b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCG_CTL", "", { |
| 104 | { BITS_EOT } |
| 105 | }}, |
| 106 | {0x186, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_EVNTSEL0", "", { |
| 107 | { BITS_EOT } |
| 108 | }}, |
| 109 | {0x187, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_EVNTSEL1", "", { |
| 110 | { BITS_EOT } |
| 111 | }}, |
| 112 | {0x1d9, MSRTYPE_RDWR, MSR2(0,0), "IA32_DEBUGCTL", "", { |
| 113 | { BITS_EOT } |
| 114 | }}, |
| 115 | {0x1db, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCHFROMIP", "", { |
| 116 | { BITS_EOT } |
| 117 | }}, |
| 118 | {0x1dc, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCHTOIP", "", { |
| 119 | { BITS_EOT } |
| 120 | }}, |
| 121 | {0x1dd, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTINTFROMIP", "", { |
| 122 | { BITS_EOT } |
| 123 | }}, |
| 124 | {0x1de, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTINTTOIP", "", { |
| 125 | { BITS_EOT } |
| 126 | }}, |
| 127 | {0x1e0, MSRTYPE_RDWR, MSR2(0,0), "MSR_ROB_CR_BKUPTMPDR6", "", { |
| 128 | { BITS_EOT } |
| 129 | }}, |
| 130 | {0x200, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE0", "", { |
| 131 | { BITS_EOT } |
| 132 | }}, |
| 133 | {0x201, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK0", "", { |
| 134 | { BITS_EOT } |
| 135 | }}, |
| 136 | {0x202, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE1", "", { |
| 137 | { BITS_EOT } |
| 138 | }}, |
| 139 | {0x203, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK1", "", { |
| 140 | { BITS_EOT } |
| 141 | }}, |
| 142 | {0x204, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE2", "", { |
| 143 | { BITS_EOT } |
| 144 | }}, |
| 145 | {0x205, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK2", "", { |
| 146 | { BITS_EOT } |
| 147 | }}, |
| 148 | {0x206, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE3", "", { |
| 149 | { BITS_EOT } |
| 150 | }}, |
| 151 | {0x207, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK3", "", { |
| 152 | { BITS_EOT } |
| 153 | }}, |
| 154 | {0x208, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE4", "", { |
| 155 | { BITS_EOT } |
| 156 | }}, |
| 157 | {0x209, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK4", "", { |
| 158 | { BITS_EOT } |
| 159 | }}, |
| 160 | {0x20a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE5", "", { |
| 161 | { BITS_EOT } |
| 162 | }}, |
| 163 | {0x20b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK5", "", { |
| 164 | { BITS_EOT } |
| 165 | }}, |
| 166 | {0x20c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE6", "", { |
| 167 | { BITS_EOT } |
| 168 | }}, |
| 169 | {0x20d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK6", "", { |
| 170 | { BITS_EOT } |
| 171 | }}, |
| 172 | {0x20e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE7", "", { |
| 173 | { BITS_EOT } |
| 174 | }}, |
| 175 | {0x20f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK7", "", { |
| 176 | { BITS_EOT } |
| 177 | }}, |
| 178 | {0x250, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX64K_00000", "", { |
| 179 | { BITS_EOT } |
| 180 | }}, |
| 181 | {0x258, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX16K_80000", "", { |
| 182 | { BITS_EOT } |
| 183 | }}, |
| 184 | {0x259, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX16K_A0000", "", { |
| 185 | { BITS_EOT } |
| 186 | }}, |
| 187 | {0x268, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_C0000", "", { |
| 188 | { BITS_EOT } |
| 189 | }}, |
| 190 | {0x269, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_C8000", "", { |
| 191 | { BITS_EOT } |
| 192 | }}, |
| 193 | {0x26a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_D0000", "", { |
| 194 | { BITS_EOT } |
| 195 | }}, |
| 196 | {0x26b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_D8000", "", { |
| 197 | { BITS_EOT } |
| 198 | }}, |
| 199 | {0x26c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_E0000", "", { |
| 200 | { BITS_EOT } |
| 201 | }}, |
| 202 | {0x26d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_E8000", "", { |
| 203 | { BITS_EOT } |
| 204 | }}, |
| 205 | {0x26e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_F0000", "", { |
| 206 | { BITS_EOT } |
| 207 | }}, |
| 208 | {0x26f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_F8000", "", { |
| 209 | { BITS_EOT } |
| 210 | }}, |
| 211 | {0x2ff, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_DEF_TYPE", "", { |
| 212 | { BITS_EOT } |
| 213 | }}, |
| 214 | {0x400, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_CTL", "", { |
| 215 | { BITS_EOT } |
| 216 | }}, |
| 217 | {0x401, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_STATUS", "", { |
| 218 | { BITS_EOT } |
| 219 | }}, |
| 220 | {0x402, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_ADDR", "", { |
| 221 | { BITS_EOT } |
| 222 | }}, |
| 223 | {0x404, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC1_CTL", "", { |
| 224 | { BITS_EOT } |
| 225 | }}, |
| 226 | {0x405, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC1_STATUS", "", { |
| 227 | { BITS_EOT } |
| 228 | }}, |
| 229 | {0x406, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC1_ADDR", "", { |
| 230 | { BITS_EOT } |
| 231 | }}, |
| 232 | {0x408, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_CTL", "", { |
| 233 | { BITS_EOT } |
| 234 | }}, |
| 235 | {0x409, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_STATUS", "", { |
| 236 | { BITS_EOT } |
| 237 | }}, |
| 238 | {0x40a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_ADDR", "", { |
| 239 | { BITS_EOT } |
| 240 | }}, |
| 241 | {0x40c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_CTL", "", { |
| 242 | { BITS_EOT } |
| 243 | }}, |
| 244 | {0x40d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_STATUS", "", { |
| 245 | { BITS_EOT } |
| 246 | }}, |
| 247 | {0x40e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_ADDR", "", { |
| 248 | { BITS_EOT } |
| 249 | }}, |
| 250 | {0x410, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_CTL", "", { |
| 251 | { BITS_EOT } |
| 252 | }}, |
| 253 | {0x411, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_STATUS", "", { |
| 254 | { BITS_EOT } |
| 255 | }}, |
| 256 | {0x412, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_ADDR", "", { |
| 257 | { BITS_EOT } |
| 258 | }}, |
| 259 | { MSR_EOT } |
| 260 | }; |