Hannah Williams | 01bc897 | 2016-02-04 20:13:34 -0800 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2013 Google Inc. |
| 5 | * Copyright (C) 2015-2016 Intel Corp. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License, or (at your option) |
| 10 | * any later version. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | */ |
| 17 | |
Alexandru Gagniuc | a633980 | 2016-04-05 12:40:24 -0700 | [diff] [blame] | 18 | #define __SIMPLE_DEVICE__ |
| 19 | |
Hannah Williams | 01bc897 | 2016-02-04 20:13:34 -0800 | [diff] [blame] | 20 | #include <arch/io.h> |
| 21 | #include <console/console.h> |
| 22 | #include <rules.h> |
| 23 | #include <device/pci_def.h> |
| 24 | #include <soc/iomap.h> |
Alexandru Gagniuc | a633980 | 2016-04-05 12:40:24 -0700 | [diff] [blame] | 25 | #include <soc/pci_devs.h> |
Hannah Williams | 01bc897 | 2016-02-04 20:13:34 -0800 | [diff] [blame] | 26 | #include <soc/pm.h> |
| 27 | #include <device/device.h> |
| 28 | #include <device/pci.h> |
Aaron Durbin | bef75e7 | 2016-05-26 11:00:44 -0500 | [diff] [blame] | 29 | #include <vendorcode/google/chromeos/vboot_common.h> |
Hannah Williams | 01bc897 | 2016-02-04 20:13:34 -0800 | [diff] [blame] | 30 | |
Alexandru Gagniuc | a633980 | 2016-04-05 12:40:24 -0700 | [diff] [blame] | 31 | static uintptr_t read_pmc_mmio_bar(void) |
| 32 | { |
| 33 | uint32_t bar = pci_read_config32(PMC_DEV, PCI_BASE_ADDRESS_0); |
| 34 | return bar & ~PCI_BASE_ADDRESS_MEM_ATTR_MASK; |
| 35 | } |
Hannah Williams | 01bc897 | 2016-02-04 20:13:34 -0800 | [diff] [blame] | 36 | |
| 37 | static void print_num_status_bits(int num_bits, uint32_t status, |
| 38 | const char * const bit_names[]) |
| 39 | { |
| 40 | int i; |
| 41 | |
| 42 | if (!status) |
| 43 | return; |
| 44 | |
| 45 | for (i = num_bits - 1; i >= 0; i--) { |
| 46 | if (status & (1 << i)) { |
| 47 | if (bit_names[i]) |
| 48 | printk(BIOS_DEBUG, "%s ", bit_names[i]); |
| 49 | else |
| 50 | printk(BIOS_DEBUG, "BIT%d ", i); |
| 51 | } |
| 52 | } |
| 53 | } |
| 54 | |
| 55 | static uint32_t print_smi_status(uint32_t smi_sts) |
| 56 | { |
| 57 | static const char * const smi_sts_bits[] = { |
Aaron Durbin | 7929dd0 | 2016-06-10 18:01:45 -0500 | [diff] [blame] | 58 | [BIOS_SMI_STS] = "BIOS", |
| 59 | [LEGACY_USB_SMI_STS] = "LEGACY USB", |
| 60 | [SLP_SMI_STS] = "SLP_SMI", |
| 61 | [APM_SMI_STS] = "APM", |
| 62 | [SWSMI_TMR_SMI_STS] = "SWSMI_TMR", |
Aaron Durbin | a554b71 | 2016-06-10 18:04:21 -0500 | [diff] [blame] | 63 | [FAKE_PM1_SMI_STS] = "PM1", |
Aaron Durbin | 7929dd0 | 2016-06-10 18:01:45 -0500 | [diff] [blame] | 64 | [GPIO_SMI_STS]= "GPIO_SMI", |
| 65 | [GPIO_UNLOCK_SMI_STS]= "GPIO_UNLOCK_SSMI", |
| 66 | [MC_SMI_STS] = "MCSMI", |
| 67 | [TCO_SMI_STS] = "TCO", |
| 68 | [PERIODIC_SMI_STS] = "PERIODIC", |
| 69 | [SERIRQ_SMI_STS] = "SERIRQ", |
| 70 | [SMBUS_SMI_STS] = "SMBUS_SMI", |
| 71 | [XHCI_SMI_STS] = "XHCI", |
| 72 | [HSMBUS_SMI_STS] = "HOST_SMBUS", |
| 73 | [SCS_SMI_STS] = "SCS", |
| 74 | [PCIE_SMI_STS] = "PCI_EXP_SMI", |
| 75 | [SCC2_SMI_STS] = "SCC2", |
| 76 | [SPI_SSMI_STS] = "SPI_SSMI", |
| 77 | [SPI_SMI_STS] = "SPI", |
| 78 | [PMC_OCP_SMI_STS] = "OCP_CSE", |
Hannah Williams | 01bc897 | 2016-02-04 20:13:34 -0800 | [diff] [blame] | 79 | }; |
| 80 | |
| 81 | if (!smi_sts) |
| 82 | return 0; |
| 83 | |
| 84 | printk(BIOS_DEBUG, "SMI_STS: "); |
| 85 | print_num_status_bits(ARRAY_SIZE(smi_sts_bits), smi_sts, smi_sts_bits); |
| 86 | printk(BIOS_DEBUG, "\n"); |
| 87 | |
| 88 | return smi_sts; |
| 89 | } |
| 90 | |
| 91 | static uint32_t reset_smi_status(void) |
| 92 | { |
| 93 | uint32_t smi_sts = inl(ACPI_PMIO_BASE + SMI_STS); |
| 94 | outl(smi_sts, ACPI_PMIO_BASE + SMI_STS); |
| 95 | return smi_sts; |
| 96 | } |
| 97 | |
| 98 | uint32_t clear_smi_status(void) |
| 99 | { |
Aaron Durbin | a554b71 | 2016-06-10 18:04:21 -0500 | [diff] [blame] | 100 | uint32_t sts = reset_smi_status(); |
| 101 | |
| 102 | /* |
| 103 | * Check for power button status if nothing else is indicating an SMI |
| 104 | * and SMIs aren't turned into SCIs. Apparently, there is no PM1 status |
| 105 | * bit in the SMI status register. That makes things difficult for |
| 106 | * determining if the power button caused an SMI. |
| 107 | */ |
| 108 | if (sts == 0 && !(inl(ACPI_PMIO_BASE + PM1_CNT) & SCI_EN)) { |
| 109 | uint16_t pm1_sts = inw(ACPI_PMIO_BASE + PM1_STS); |
| 110 | |
| 111 | /* Fake PM1 status bit if power button pressed. */ |
| 112 | if (pm1_sts & PWRBTN_STS) |
| 113 | sts |= (1 << FAKE_PM1_SMI_STS); |
| 114 | } |
| 115 | |
| 116 | return print_smi_status(sts); |
Hannah Williams | 01bc897 | 2016-02-04 20:13:34 -0800 | [diff] [blame] | 117 | } |
| 118 | |
| 119 | uint32_t get_smi_en(void) |
| 120 | { |
| 121 | return inl(ACPI_PMIO_BASE + SMI_EN); |
| 122 | } |
| 123 | |
| 124 | void enable_smi(uint32_t mask) |
| 125 | { |
| 126 | uint32_t smi_en = inl(ACPI_PMIO_BASE + SMI_EN); |
| 127 | smi_en |= mask; |
| 128 | outl(smi_en, ACPI_PMIO_BASE + SMI_EN); |
| 129 | } |
| 130 | |
| 131 | void disable_smi(uint32_t mask) |
| 132 | { |
| 133 | uint32_t smi_en = inl(ACPI_PMIO_BASE + SMI_EN); |
| 134 | smi_en &= ~mask; |
| 135 | outl(smi_en, ACPI_PMIO_BASE + SMI_EN); |
| 136 | } |
| 137 | |
| 138 | void enable_pm1_control(uint32_t mask) |
| 139 | { |
| 140 | uint32_t pm1_cnt = inl(ACPI_PMIO_BASE + PM1_CNT); |
| 141 | pm1_cnt |= mask; |
| 142 | outl(pm1_cnt, ACPI_PMIO_BASE + PM1_CNT); |
| 143 | } |
| 144 | |
| 145 | void disable_pm1_control(uint32_t mask) |
| 146 | { |
| 147 | uint32_t pm1_cnt = inl(ACPI_PMIO_BASE + PM1_CNT); |
| 148 | pm1_cnt &= ~mask; |
| 149 | outl(pm1_cnt, ACPI_PMIO_BASE + PM1_CNT); |
| 150 | } |
| 151 | |
| 152 | static uint16_t reset_pm1_status(void) |
| 153 | { |
| 154 | uint16_t pm1_sts = inw(ACPI_PMIO_BASE + PM1_STS); |
| 155 | outw(pm1_sts, ACPI_PMIO_BASE + PM1_STS); |
| 156 | return pm1_sts; |
| 157 | } |
| 158 | |
| 159 | static uint16_t print_pm1_status(uint16_t pm1_sts) |
| 160 | { |
| 161 | static const char * const pm1_sts_bits[] = { |
| 162 | [0] = "TMROF", |
| 163 | [5] = "GBL", |
| 164 | [8] = "PWRBTN", |
| 165 | [10] = "RTC", |
| 166 | [11] = "PRBTNOR", |
| 167 | [13] = "USB", |
| 168 | [14] = "PCIEXPWAK", |
| 169 | [15] = "WAK", |
| 170 | }; |
| 171 | |
| 172 | if (!pm1_sts) |
| 173 | return 0; |
| 174 | |
| 175 | printk(BIOS_SPEW, "PM1_STS: "); |
| 176 | print_num_status_bits(ARRAY_SIZE(pm1_sts_bits), pm1_sts, pm1_sts_bits); |
| 177 | printk(BIOS_SPEW, "\n"); |
| 178 | |
| 179 | return pm1_sts; |
| 180 | } |
| 181 | |
| 182 | uint16_t clear_pm1_status(void) |
| 183 | { |
| 184 | return print_pm1_status(reset_pm1_status()); |
| 185 | } |
| 186 | |
| 187 | void enable_pm1(uint16_t events) |
| 188 | { |
| 189 | outw(events, ACPI_PMIO_BASE + PM1_EN); |
| 190 | } |
| 191 | |
| 192 | static uint32_t print_tco_status(uint32_t tco_sts) |
| 193 | { |
| 194 | static const char * const tco_sts_bits[] = { |
| 195 | [3] = "TIMEOUT", |
| 196 | [17] = "SECOND_TO", |
| 197 | }; |
| 198 | |
| 199 | if (!tco_sts) |
| 200 | return 0; |
| 201 | |
| 202 | printk(BIOS_DEBUG, "TCO_STS: "); |
| 203 | print_num_status_bits(ARRAY_SIZE(tco_sts_bits), tco_sts, tco_sts_bits); |
| 204 | printk(BIOS_DEBUG, "\n"); |
| 205 | |
| 206 | return tco_sts; |
| 207 | } |
| 208 | |
| 209 | static uint32_t reset_tco_status(void) |
| 210 | { |
| 211 | uint32_t tco_sts = inl(ACPI_PMIO_BASE + TCO_STS); |
| 212 | uint32_t tco_en = inl(ACPI_PMIO_BASE + TCO1_CNT); |
| 213 | |
| 214 | outl(tco_sts, ACPI_PMIO_BASE + TCO_STS); |
| 215 | return tco_sts & tco_en; |
| 216 | } |
| 217 | |
| 218 | uint32_t clear_tco_status(void) |
| 219 | { |
| 220 | return print_tco_status(reset_tco_status()); |
| 221 | } |
| 222 | |
| 223 | void enable_gpe(uint32_t mask) |
| 224 | { |
| 225 | uint32_t gpe0a_en = inl(ACPI_PMIO_BASE + GPE0_EN(0)); |
| 226 | gpe0a_en |= mask; |
| 227 | outl(gpe0a_en, ACPI_PMIO_BASE + GPE0_EN(0)); |
| 228 | } |
| 229 | |
| 230 | void disable_gpe(uint32_t mask) |
| 231 | { |
| 232 | uint32_t gpe0a_en = inl(ACPI_PMIO_BASE + GPE0_EN(0)); |
| 233 | gpe0a_en &= ~mask; |
| 234 | outl(gpe0a_en, ACPI_PMIO_BASE + GPE0_EN(0)); |
| 235 | } |
| 236 | |
| 237 | void disable_all_gpe(void) |
| 238 | { |
| 239 | disable_gpe(~0); |
| 240 | } |
| 241 | |
| 242 | |
| 243 | static uint32_t reset_gpe_status(void) |
| 244 | { |
| 245 | uint32_t gpe_sts = inl(ACPI_PMIO_BASE + GPE0_STS(0)); |
| 246 | outl(gpe_sts, ACPI_PMIO_BASE + GPE0_STS(0)); |
| 247 | return gpe_sts; |
| 248 | } |
| 249 | |
| 250 | static uint32_t print_gpe_sts(uint32_t gpe_sts) |
| 251 | { |
| 252 | static const char * const gpe_sts_bits[] = { |
| 253 | [0] = "PCIE_SCI", |
| 254 | [2] = "SWGPE", |
| 255 | [3] = "PCIE_WAKE0", |
| 256 | [4] = "PUNIT", |
| 257 | [6] = "PCIE_WAKE1", |
| 258 | [7] = "PCIE_WAKE2", |
| 259 | [8] = "PCIE_WAKE3", |
| 260 | [9] = "PCI_EXP", |
| 261 | [10] = "BATLOW", |
| 262 | [11] = "CSE_PME", |
| 263 | [12] = "XDCI_PME", |
| 264 | [13] = "XHCI_PME", |
| 265 | [14] = "AVS_PME", |
| 266 | [15] = "GPIO_TIER1_SCI", |
| 267 | [16] = "SMB_WAK", |
| 268 | [17] = "SATA_PME", |
| 269 | }; |
| 270 | |
| 271 | if (!gpe_sts) |
| 272 | return gpe_sts; |
| 273 | |
| 274 | printk(BIOS_DEBUG, "GPE0a_STS: "); |
| 275 | print_num_status_bits(ARRAY_SIZE(gpe_sts_bits), gpe_sts, gpe_sts_bits); |
| 276 | printk(BIOS_DEBUG, "\n"); |
| 277 | |
| 278 | return gpe_sts; |
| 279 | } |
| 280 | |
| 281 | uint32_t clear_gpe_status(void) |
| 282 | { |
| 283 | return print_gpe_sts(reset_gpe_status()); |
| 284 | } |
| 285 | |
| 286 | void clear_pmc_status(void) |
| 287 | { |
| 288 | uint32_t prsts; |
| 289 | uint32_t gen_pmcon1; |
Alexandru Gagniuc | a633980 | 2016-04-05 12:40:24 -0700 | [diff] [blame] | 290 | uintptr_t pmc_bar0 = read_pmc_mmio_bar(); |
Hannah Williams | 01bc897 | 2016-02-04 20:13:34 -0800 | [diff] [blame] | 291 | |
Alexandru Gagniuc | a633980 | 2016-04-05 12:40:24 -0700 | [diff] [blame] | 292 | prsts = read32((void *)(pmc_bar0 + PRSTS)); |
| 293 | gen_pmcon1 = read32((void *)(pmc_bar0 + GEN_PMCON1)); |
Hannah Williams | 01bc897 | 2016-02-04 20:13:34 -0800 | [diff] [blame] | 294 | |
| 295 | /* Clear the status bits. The RPS field is cleared on a 0 write. */ |
Alexandru Gagniuc | a633980 | 2016-04-05 12:40:24 -0700 | [diff] [blame] | 296 | write32((void *)(pmc_bar0 + GEN_PMCON1), gen_pmcon1 & ~RPS); |
| 297 | write32((void *)(pmc_bar0 + PRSTS), prsts); |
Hannah Williams | 01bc897 | 2016-02-04 20:13:34 -0800 | [diff] [blame] | 298 | } |
| 299 | |
| 300 | |
| 301 | /* Return 0, 3, or 5 to indicate the previous sleep state. */ |
| 302 | int chipset_prev_sleep_state(struct chipset_power_state *ps) |
| 303 | { |
| 304 | /* Default to S0. */ |
| 305 | int prev_sleep_state = SLEEP_STATE_S0; |
| 306 | |
| 307 | if (ps->pm1_sts & WAK_STS) { |
| 308 | switch ((ps->pm1_cnt & SLP_TYP) >> SLP_TYP_SHIFT) { |
| 309 | #if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) |
| 310 | case SLP_TYP_S3: |
| 311 | prev_sleep_state = SLEEP_STATE_S3; |
| 312 | break; |
| 313 | #endif |
| 314 | case SLP_TYP_S5: |
| 315 | prev_sleep_state = SLEEP_STATE_S5; |
| 316 | break; |
| 317 | } |
| 318 | } |
| 319 | return prev_sleep_state; |
| 320 | } |
| 321 | |
| 322 | /* returns prev_sleep_state */ |
| 323 | int fill_power_state(struct chipset_power_state *ps) |
| 324 | { |
| 325 | int i; |
Alexandru Gagniuc | a633980 | 2016-04-05 12:40:24 -0700 | [diff] [blame] | 326 | uintptr_t pmc_bar0 = read_pmc_mmio_bar(); |
| 327 | |
Hannah Williams | 01bc897 | 2016-02-04 20:13:34 -0800 | [diff] [blame] | 328 | ps->pm1_sts = inw(ACPI_PMIO_BASE + PM1_STS); |
| 329 | ps->pm1_en = inw(ACPI_PMIO_BASE + PM1_EN); |
| 330 | ps->pm1_cnt = inl(ACPI_PMIO_BASE + PM1_CNT); |
| 331 | ps->tco_sts = inl(ACPI_PMIO_BASE + TCO_STS); |
Alexandru Gagniuc | a633980 | 2016-04-05 12:40:24 -0700 | [diff] [blame] | 332 | ps->prsts = read32((void *)(pmc_bar0 + PRSTS)); |
| 333 | ps->gen_pmcon1 =read32((void *)(pmc_bar0 + GEN_PMCON1)); |
| 334 | ps->gen_pmcon2 = read32((void *)(pmc_bar0 + GEN_PMCON2)); |
| 335 | ps->gen_pmcon3 = read32((void *)(pmc_bar0 + GEN_PMCON3)); |
Hannah Williams | 01bc897 | 2016-02-04 20:13:34 -0800 | [diff] [blame] | 336 | |
| 337 | ps->prev_sleep_state = chipset_prev_sleep_state(ps); |
| 338 | |
| 339 | printk(BIOS_DEBUG, "pm1_sts: %04x pm1_en: %04x pm1_cnt: %08x\n", |
| 340 | ps->pm1_sts, ps->pm1_en, ps->pm1_cnt); |
| 341 | printk(BIOS_DEBUG, "prsts: %08x tco_sts: %08x\n", |
| 342 | ps->prsts, ps->tco_sts); |
| 343 | printk(BIOS_DEBUG, |
| 344 | "gen_pmcon1: %08x gen_pmcon2: %08x gen_pmcon3: %08x\n", |
| 345 | ps->gen_pmcon1, ps->gen_pmcon2, ps->gen_pmcon3); |
| 346 | printk(BIOS_DEBUG, "smi_en: %08x smi_sts: %08x\n", |
| 347 | inl(ACPI_PMIO_BASE + SMI_EN), inl(ACPI_PMIO_BASE + SMI_STS)); |
| 348 | for (i=0; i < GPE0_REG_MAX; i++) { |
| 349 | ps->gpe0_sts[i] = inl(ACPI_PMIO_BASE + GPE0_STS(i)); |
| 350 | ps->gpe0_en[i] = inl(ACPI_PMIO_BASE + GPE0_EN(i)); |
| 351 | printk(BIOS_DEBUG, "gpe0_sts[%d]: %08x gpe0_en[%d]: %08x\n", |
| 352 | i, ps->gpe0_sts[i], i, ps->gpe0_en[i]); |
| 353 | } |
| 354 | printk(BIOS_DEBUG, "prev_sleep_state %d\n", ps->prev_sleep_state); |
| 355 | return ps->prev_sleep_state; |
| 356 | } |
Aaron Durbin | bef75e7 | 2016-05-26 11:00:44 -0500 | [diff] [blame] | 357 | |
| 358 | int vboot_platform_is_resuming(void) |
| 359 | { |
| 360 | int typ; |
| 361 | |
| 362 | if (!(inw(ACPI_PMIO_BASE + PM1_STS) & WAK_STS)) |
| 363 | return 0; |
| 364 | |
| 365 | typ = (inl(ACPI_PMIO_BASE + PM1_CNT) & SLP_TYP) >> SLP_TYP_SHIFT; |
| 366 | return typ == SLP_TYP_S3; |
| 367 | } |
Andrey Petrov | 0f593c2 | 2016-06-17 15:30:13 -0700 | [diff] [blame] | 368 | |
| 369 | /* |
| 370 | * If possible, lock 0xcf9. Once the register is locked, it can't be changed. |
| 371 | * This lock is reset on cold boot, hard reset, soft reset and Sx. |
| 372 | */ |
| 373 | void global_reset_lock(void) |
| 374 | { |
| 375 | uintptr_t etr = read_pmc_mmio_bar() + ETR; |
| 376 | uint32_t reg; |
| 377 | |
| 378 | reg = read32((void *)etr); |
| 379 | if (reg & CF9_LOCK) |
| 380 | return; |
| 381 | reg |= CF9_LOCK; |
| 382 | write32((void *)etr, reg); |
| 383 | } |
| 384 | |
| 385 | /* |
| 386 | * Enable or disable global reset. If global reset is enabled, hard reset and |
| 387 | * soft reset will trigger global reset, where both host and TXE are reset. |
| 388 | * This is cleared on cold boot, hard reset, soft reset and Sx. |
| 389 | */ |
| 390 | void global_reset_enable(bool enable) |
| 391 | { |
| 392 | uintptr_t etr = read_pmc_mmio_bar() + ETR; |
| 393 | uint32_t reg; |
| 394 | |
| 395 | reg = read32((void *)etr); |
| 396 | reg = enable ? reg | CF9_GLB_RST : reg & ~CF9_GLB_RST; |
| 397 | write32((void *)etr, reg); |
| 398 | } |