blob: fd4eb34ef923f7883334f2c9a9f0c1ba96327f52 [file] [log] [blame]
Stefan Reinauer00a889c2008-10-29 04:48:44 +00001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2007-2008 coresystems GmbH
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; version 2 of
9 * the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
19 * MA 02110-1301 USA
20 */
21
22 __asm__ volatile (
23
24 "movb $0x30, %al\noutb %al, $0x80\n"
25
26 /* Disable Cache */
27 "movl %cr0, %eax\n"
28 "orl $(1 << 30), %eax\n"
29 "movl %eax, %cr0\n"
30
31 "movb $0x31, %al\noutb %al, $0x80\n"
32
33 /* Disable MTRR */
34 "movl $MTRRdefType_MSR, %ecx\n"
35 "rdmsr\n"
36 "andl $(~(1 << 11)), %eax\n"
37 "wrmsr\n"
38
39 "movb $0x32, %al\noutb %al, $0x80\n"
40
41 "invd\n"
42#if 0
43 "xorl %eax, %eax\n"
44 "xorl %edx, %edx\n"
45 "movl $MTRRphysBase_MSR(0), %ecx\n"
46 "wrmsr\n"
47 "movl $MTRRphysMask_MSR(0), %ecx\n"
48 "wrmsr\n"
49 "movl $MTRRphysBase_MSR(1), %ecx\n"
50 "wrmsr\n"
51 "movl $MTRRphysMask_MSR(1), %ecx\n"
52 "wrmsr\n"
53#endif
54
55 "movb $0x33, %al\noutb %al, $0x80\n"
56#ifdef CLEAR_FIRST_1M_RAM
57 "movb $0x34, %al\noutb %al, $0x80\n"
58 /* Enable Write Combining and Speculative Reads for the first 1MB */
59 "movl $MTRRphysBase_MSR(0), %ecx\n"
60 "movl $(0x00000000 | MTRR_TYPE_WRCOMB), %eax\n"
61 "xorl %edx, %edx\n"
62 "wrmsr\n"
63 "movl $MTRRphysMask_MSR(0), %ecx\n"
64 "movl $(~(1024*1024 -1) | (1 << 11)), %eax\n"
65 "movl $0x0000000f, %edx\n" // 36bit address space
66 "wrmsr\n"
67 "movb $0x35, %al\noutb %al, $0x80\n"
68#endif
69
70 /* Enable Cache */
71 "movl %cr0, %eax\n"
72 "andl $~( (1 << 30) | (1 << 29) ), %eax\n"
73 "movl %eax, %cr0\n"
74
75 "movb $0x36, %al\noutb %al, $0x80\n"
76#ifdef CLEAR_FIRST_1M_RAM
77
78 /* Clear first 1MB of RAM */
79 "movl $0x00000000, %edi\n"
80 "cld\n"
81 "xorl %eax, %eax\n"
82 "movl $((1024*1024) / 4), %ecx\n"
83 "rep stosl\n"
84
85 "movb $0x37, %al\noutb %al, $0x80\n"
86#endif
87
88 /* Disable Cache */
89 "movl %cr0, %eax\n"
90 "orl $(1 << 30), %eax\n"
91 "movl %eax, %cr0\n"
92
93 "movb $0x38, %al\noutb %al, $0x80\n"
94
95 /* Enable Write Back and Speculative Reads for the first 1MB */
96 "movl $MTRRphysBase_MSR(0), %ecx\n"
97 "movl $(0x00000000 | MTRR_TYPE_WRBACK), %eax\n"
98 "xorl %edx, %edx\n"
99 "wrmsr\n"
100 "movl $MTRRphysMask_MSR(0), %ecx\n"
101 "movl $(~(1024*1024 -1) | (1 << 11)), %eax\n"
102 "movl $0x0000000f, %edx\n" // 36bit address space
103 "wrmsr\n"
104
105 "movb $0x39, %al\noutb %al, $0x80\n"
106
107 /* And Enable Cache again after setting MTRRs */
108 "movl %cr0, %eax\n"
109 "andl $~( (1 << 30) | (1 << 29) ), %eax\n"
110 "movl %eax, %cr0\n"
111
112 "movb $0x3a, %al\noutb %al, $0x80\n"
113
114 /* Enable MTRR */
115 "movl $MTRRdefType_MSR, %ecx\n"
116 "rdmsr\n"
117 "orl $(1 << 11), %eax\n"
118 "wrmsr\n"
119
120 "movb $0x3b, %al\noutb %al, $0x80\n"
121
122 /* Invalidate the cache again */
123 "invd\n"
124 "movb $0x3c, %al\noutb %al, $0x80\n"
125 );