Martin Roth | b28f466 | 2018-05-26 17:58:47 -0600 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License as published by |
| 6 | * the Free Software Foundation; version 2 of the License. |
| 7 | * |
| 8 | * This program is distributed in the hope that it will be useful, |
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 11 | * GNU General Public License for more details. |
| 12 | */ |
| 13 | |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 14 | #include <device/pci_ops.h> |
Patrick Rudolph | 1af8923 | 2018-11-11 12:50:51 +0100 | [diff] [blame] | 15 | #include <bootblock_common.h> |
| 16 | #include <southbridge/intel/i82801ix/i82801ix.h> |
Patrick Rudolph | fbdeb4a | 2019-02-14 19:47:03 +0100 | [diff] [blame] | 17 | #include <console/console.h> |
Kyösti Mälkki | b9646a2 | 2013-07-03 08:06:32 +0300 | [diff] [blame] | 18 | |
| 19 | /* Just define these here, there is no gm35.h file to include. */ |
| 20 | #define D0F0_PCIEXBAR_LO 0x60 |
| 21 | #define D0F0_PCIEXBAR_HI 0x64 |
| 22 | |
| 23 | static void bootblock_northbridge_init(void) |
| 24 | { |
| 25 | uint32_t reg; |
| 26 | |
| 27 | /* |
| 28 | * The "io" variant of the config access is explicitly used to |
Kyösti Mälkki | 6f66f41 | 2016-12-01 22:08:18 +0200 | [diff] [blame] | 29 | * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT is set to |
Kyösti Mälkki | b9646a2 | 2013-07-03 08:06:32 +0300 | [diff] [blame] | 30 | * to true. That way all subsequent non-explicit config accesses use |
| 31 | * MCFG. This code also assumes that bootblock_northbridge_init() is |
| 32 | * the first thing called in the non-asm boot block code. The final |
| 33 | * assumption is that no assembly code is using the |
Kyösti Mälkki | 6f66f41 | 2016-12-01 22:08:18 +0200 | [diff] [blame] | 34 | * CONFIG_MMCONF_SUPPORT option to do PCI config acceses. |
Kyösti Mälkki | b9646a2 | 2013-07-03 08:06:32 +0300 | [diff] [blame] | 35 | * |
| 36 | * The PCIEXBAR is assumed to live in the memory mapped IO space under |
| 37 | * 4GiB. |
| 38 | */ |
| 39 | reg = 0; |
| 40 | pci_io_write_config32(PCI_DEV(0,0,0), D0F0_PCIEXBAR_HI, reg); |
| 41 | reg = CONFIG_MMCONF_BASE_ADDRESS | 1; /* 256MiB - 0-255 buses. */ |
| 42 | pci_io_write_config32(PCI_DEV(0,0,0), D0F0_PCIEXBAR_LO, reg); |
Patrick Rudolph | fbdeb4a | 2019-02-14 19:47:03 +0100 | [diff] [blame] | 43 | |
| 44 | /* MCFG is now active. If it's not qemu was started for machine PC */ |
| 45 | if (CONFIG(BOOTBLOCK_CONSOLE) && |
| 46 | (pci_read_config32(PCI_DEV(0, 0, 0), D0F0_PCIEXBAR_LO) != |
| 47 | (CONFIG_MMCONF_BASE_ADDRESS | 1))) |
| 48 | die("You must run qemu for machine Q35 (-M q35)"); |
Kyösti Mälkki | b9646a2 | 2013-07-03 08:06:32 +0300 | [diff] [blame] | 49 | } |
| 50 | |
Patrick Rudolph | 1af8923 | 2018-11-11 12:50:51 +0100 | [diff] [blame] | 51 | static void enable_spi_prefetch(void) |
| 52 | { |
| 53 | u8 reg8; |
| 54 | pci_devfn_t dev; |
| 55 | |
| 56 | dev = PCI_DEV(0, 0x1f, 0); |
| 57 | |
| 58 | reg8 = pci_read_config8(dev, 0xdc); |
| 59 | reg8 &= ~(3 << 2); |
| 60 | reg8 |= (2 << 2); /* Prefetching and Caching Enabled */ |
| 61 | pci_write_config8(dev, 0xdc, reg8); |
| 62 | } |
| 63 | |
| 64 | static void bootblock_southbridge_init(void) |
| 65 | { |
| 66 | enable_spi_prefetch(); |
| 67 | |
| 68 | /* Enable RCBA */ |
Peter Lemenkov | 7b42811 | 2018-10-23 11:12:46 +0200 | [diff] [blame] | 69 | pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, |
Patrick Rudolph | 1af8923 | 2018-11-11 12:50:51 +0100 | [diff] [blame] | 70 | (uintptr_t)DEFAULT_RCBA | 1); |
| 71 | } |
| 72 | |
| 73 | void bootblock_soc_init(void) |
Kyösti Mälkki | b9646a2 | 2013-07-03 08:06:32 +0300 | [diff] [blame] | 74 | { |
| 75 | bootblock_northbridge_init(); |
| 76 | bootblock_southbridge_init(); |
| 77 | } |