Lijian Zhao | 2f764f7 | 2017-07-14 11:09:10 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2016-2017 Intel Corporation. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | */ |
| 15 | |
| 16 | #include <chip.h> |
| 17 | #include <console/console.h> |
Pratik Prajapati | 201fa8f | 2017-08-16 11:42:40 -0700 | [diff] [blame] | 18 | #include <device/device.h> |
Lijian Zhao | 2f764f7 | 2017-07-14 11:09:10 -0700 | [diff] [blame] | 19 | #include <device/pci.h> |
| 20 | #include <fsp/api.h> |
Lijian Zhao | 2f764f7 | 2017-07-14 11:09:10 -0700 | [diff] [blame] | 21 | #include <fsp/util.h> |
| 22 | #include <romstage_handoff.h> |
Abhay kumar | fcf8820 | 2017-09-20 15:17:42 -0700 | [diff] [blame] | 23 | #include <soc/intel/common/vbt.h> |
Pratik Prajapati | 9027e1b | 2017-08-23 17:37:43 -0700 | [diff] [blame] | 24 | #include <soc/pci_devs.h> |
Lijian Zhao | 2f764f7 | 2017-07-14 11:09:10 -0700 | [diff] [blame] | 25 | #include <soc/ramstage.h> |
| 26 | #include <string.h> |
| 27 | |
Lijian Zhao | 2b074d9 | 2017-08-17 14:25:24 -0700 | [diff] [blame] | 28 | #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) |
Aaron Durbin | aa090cb | 2017-09-13 16:01:52 -0600 | [diff] [blame] | 29 | static const char *soc_acpi_name(const struct device *dev) |
Lijian Zhao | 2b074d9 | 2017-08-17 14:25:24 -0700 | [diff] [blame] | 30 | { |
| 31 | if (dev->path.type == DEVICE_PATH_DOMAIN) |
| 32 | return "PCI0"; |
| 33 | |
| 34 | if (dev->path.type != DEVICE_PATH_PCI) |
| 35 | return NULL; |
| 36 | |
| 37 | switch (dev->path.pci.devfn) { |
| 38 | case SA_DEVFN_ROOT: return "MCHC"; |
| 39 | case SA_DEVFN_IGD: return "GFX0"; |
| 40 | case PCH_DEVFN_ISH: return "ISHB"; |
| 41 | case PCH_DEVFN_XHCI: return "XHCI"; |
| 42 | case PCH_DEVFN_USBOTG: return "XDCI"; |
| 43 | case PCH_DEVFN_THERMAL: return "THRM"; |
| 44 | case PCH_DEVFN_I2C0: return "I2C0"; |
| 45 | case PCH_DEVFN_I2C1: return "I2C1"; |
| 46 | case PCH_DEVFN_I2C2: return "I2C2"; |
| 47 | case PCH_DEVFN_I2C3: return "I2C3"; |
| 48 | case PCH_DEVFN_CSE: return "CSE1"; |
| 49 | case PCH_DEVFN_CSE_2: return "CSE2"; |
| 50 | case PCH_DEVFN_CSE_IDER: return "CSED"; |
| 51 | case PCH_DEVFN_CSE_KT: return "CSKT"; |
| 52 | case PCH_DEVFN_CSE_3: return "CSE3"; |
| 53 | case PCH_DEVFN_SATA: return "SATA"; |
| 54 | case PCH_DEVFN_UART2: return "UAR2"; |
| 55 | case PCH_DEVFN_I2C4: return "I2C4"; |
| 56 | case PCH_DEVFN_I2C5: return "I2C5"; |
| 57 | case PCH_DEVFN_PCIE1: return "RP01"; |
| 58 | case PCH_DEVFN_PCIE2: return "RP02"; |
| 59 | case PCH_DEVFN_PCIE3: return "RP03"; |
| 60 | case PCH_DEVFN_PCIE4: return "RP04"; |
| 61 | case PCH_DEVFN_PCIE5: return "RP05"; |
| 62 | case PCH_DEVFN_PCIE6: return "RP06"; |
| 63 | case PCH_DEVFN_PCIE7: return "RP07"; |
| 64 | case PCH_DEVFN_PCIE8: return "RP08"; |
| 65 | case PCH_DEVFN_PCIE9: return "RP09"; |
| 66 | case PCH_DEVFN_PCIE10: return "RP10"; |
| 67 | case PCH_DEVFN_PCIE11: return "RP11"; |
| 68 | case PCH_DEVFN_PCIE12: return "RP12"; |
| 69 | case PCH_DEVFN_UART0: return "UAR0"; |
| 70 | case PCH_DEVFN_UART1: return "UAR1"; |
| 71 | case PCH_DEVFN_GSPI0: return "SPI0"; |
| 72 | case PCH_DEVFN_GSPI1: return "SPI1"; |
| 73 | case PCH_DEVFN_GSPI2: return "SPI2"; |
| 74 | case PCH_DEVFN_EMMC: return "EMMC"; |
| 75 | case PCH_DEVFN_SDCARD: return "SDXC"; |
| 76 | case PCH_DEVFN_LPC: return "LPCB"; |
| 77 | case PCH_DEVFN_P2SB: return "P2SB"; |
| 78 | case PCH_DEVFN_PMC: return "PMC_"; |
| 79 | case PCH_DEVFN_HDA: return "HDAS"; |
| 80 | case PCH_DEVFN_SMBUS: return "SBUS"; |
| 81 | case PCH_DEVFN_SPI: return "FSPI"; |
| 82 | case PCH_DEVFN_GBE: return "IGBE"; |
| 83 | case PCH_DEVFN_TRACEHUB:return "THUB"; |
| 84 | } |
| 85 | |
| 86 | return NULL; |
| 87 | } |
| 88 | #endif |
| 89 | |
Lijian Zhao | 0823183 | 2017-09-05 18:16:21 -0700 | [diff] [blame] | 90 | static void parse_devicetree(FSP_S_CONFIG *params) |
| 91 | { |
| 92 | struct device *dev = SA_DEV_ROOT; |
| 93 | if (!dev) { |
| 94 | printk(BIOS_ERR, "Could not find root device\n"); |
| 95 | return; |
| 96 | } |
| 97 | |
| 98 | const config_t *config = dev->chip_info; |
| 99 | const int SerialIoDev[] = { |
| 100 | PCH_DEVFN_I2C0, |
| 101 | PCH_DEVFN_I2C1, |
| 102 | PCH_DEVFN_I2C2, |
| 103 | PCH_DEVFN_I2C3, |
| 104 | PCH_DEVFN_I2C4, |
| 105 | PCH_DEVFN_I2C5, |
| 106 | PCH_DEVFN_GSPI0, |
| 107 | PCH_DEVFN_GSPI1, |
| 108 | PCH_DEVFN_GSPI2, |
| 109 | PCH_DEVFN_UART0, |
| 110 | PCH_DEVFN_UART1, |
| 111 | PCH_DEVFN_UART2 |
| 112 | }; |
| 113 | |
| 114 | for (int i = 0; i < ARRAY_SIZE(SerialIoDev); i++) { |
| 115 | dev = dev_find_slot(0, SerialIoDev[i]); |
| 116 | if (!dev->enabled) { |
| 117 | params->SerialIoDevMode[i] = PchSerialIoDisabled; |
| 118 | continue; |
| 119 | } |
| 120 | params->SerialIoDevMode[i] = PchSerialIoPci; |
| 121 | if (config->SerialIoDevMode[i] == PchSerialIoAcpi || |
| 122 | config->SerialIoDevMode[i] == PchSerialIoHidden) |
| 123 | params->SerialIoDevMode[i] = config->SerialIoDevMode[i]; |
| 124 | } |
| 125 | } |
| 126 | |
Lijian Zhao | 2f764f7 | 2017-07-14 11:09:10 -0700 | [diff] [blame] | 127 | void soc_init_pre_device(void *chip_info) |
| 128 | { |
| 129 | /* Perform silicon specific init. */ |
| 130 | fsp_silicon_init(romstage_handoff_is_resume()); |
| 131 | } |
| 132 | |
Pratik Prajapati | 201fa8f | 2017-08-16 11:42:40 -0700 | [diff] [blame] | 133 | static void pci_domain_set_resources(device_t dev) |
| 134 | { |
| 135 | assign_resources(dev->link_list); |
| 136 | } |
| 137 | |
| 138 | static struct device_operations pci_domain_ops = { |
| 139 | .read_resources = &pci_domain_read_resources, |
| 140 | .set_resources = &pci_domain_set_resources, |
| 141 | .scan_bus = &pci_domain_scan_bus, |
| 142 | .ops_pci_bus = &pci_bus_default_ops, |
Lijian Zhao | 2b074d9 | 2017-08-17 14:25:24 -0700 | [diff] [blame] | 143 | #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) |
| 144 | .acpi_name = &soc_acpi_name, |
| 145 | #endif |
Pratik Prajapati | 201fa8f | 2017-08-16 11:42:40 -0700 | [diff] [blame] | 146 | }; |
| 147 | |
| 148 | static struct device_operations cpu_bus_ops = { |
| 149 | .read_resources = DEVICE_NOOP, |
| 150 | .set_resources = DEVICE_NOOP, |
| 151 | .enable_resources = DEVICE_NOOP, |
| 152 | .init = DEVICE_NOOP, |
| 153 | }; |
| 154 | |
| 155 | static void soc_enable(device_t dev) |
| 156 | { |
| 157 | /* Set the operations if it is a special bus type */ |
| 158 | if (dev->path.type == DEVICE_PATH_DOMAIN) |
| 159 | dev->ops = &pci_domain_ops; |
| 160 | else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) |
| 161 | dev->ops = &cpu_bus_ops; |
| 162 | } |
| 163 | |
Lijian Zhao | 2f764f7 | 2017-07-14 11:09:10 -0700 | [diff] [blame] | 164 | struct chip_operations soc_intel_cannonlake_ops = { |
| 165 | CHIP_NAME("Intel Cannonlake") |
Pratik Prajapati | 201fa8f | 2017-08-16 11:42:40 -0700 | [diff] [blame] | 166 | .enable_dev = &soc_enable, |
Lijian Zhao | 2f764f7 | 2017-07-14 11:09:10 -0700 | [diff] [blame] | 167 | .init = &soc_init_pre_device, |
| 168 | }; |
| 169 | |
| 170 | /* UPD parameters to be initialized before SiliconInit */ |
| 171 | void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) |
| 172 | { |
| 173 | int i; |
| 174 | FSP_S_CONFIG *params = &supd->FspsConfig; |
Pratik Prajapati | 9027e1b | 2017-08-23 17:37:43 -0700 | [diff] [blame] | 175 | const struct device *dev = SA_DEV_ROOT; |
| 176 | const config_t *config = dev->chip_info; |
Lijian Zhao | 2f764f7 | 2017-07-14 11:09:10 -0700 | [diff] [blame] | 177 | |
Lijian Zhao | 0823183 | 2017-09-05 18:16:21 -0700 | [diff] [blame] | 178 | /* Parse device tree and enable/disable devices */ |
| 179 | parse_devicetree(params); |
| 180 | |
Abhay kumar | fcf8820 | 2017-09-20 15:17:42 -0700 | [diff] [blame] | 181 | /* Load VBT before devicetree-specific config. */ |
Patrick Georgi | 2257959 | 2017-10-06 17:36:09 +0200 | [diff] [blame] | 182 | params->GraphicsConfigPtr = (uintptr_t)vbt_get(); |
Abhay kumar | fcf8820 | 2017-09-20 15:17:42 -0700 | [diff] [blame] | 183 | |
Lijian Zhao | 2f764f7 | 2017-07-14 11:09:10 -0700 | [diff] [blame] | 184 | /* Set USB OC pin to 0 first */ |
| 185 | for (i = 0; i < ARRAY_SIZE(params->Usb2OverCurrentPin); i++) { |
| 186 | params->Usb2OverCurrentPin[i] = 0; |
| 187 | } |
| 188 | |
| 189 | for (i = 0; i < ARRAY_SIZE(params->Usb3OverCurrentPin); i++) { |
| 190 | params->Usb3OverCurrentPin[i] = 0; |
| 191 | } |
| 192 | |
| 193 | mainboard_silicon_init_params(params); |
Pratik Prajapati | 9027e1b | 2017-08-23 17:37:43 -0700 | [diff] [blame] | 194 | |
| 195 | /* SATA */ |
| 196 | params->SataEnable = config->SataEnable; |
| 197 | params->SataMode = config->SataMode; |
| 198 | params->SataSalpSupport = config->SataSalpSupport; |
| 199 | memcpy(params->SataPortsEnable, config->SataPortsEnable, |
| 200 | sizeof(params->SataPortsEnable)); |
| 201 | memcpy(params->SataPortsDevSlp, config->SataPortsDevSlp, |
| 202 | sizeof(params->SataPortsDevSlp)); |
| 203 | |
| 204 | /* Lan */ |
| 205 | params->PchLanEnable = config->PchLanEnable; |
| 206 | |
| 207 | /* Audio */ |
| 208 | params->PchHdaDspEnable = config->PchHdaDspEnable; |
| 209 | params->PchHdaAudioLinkHda = config->PchHdaAudioLinkHda; |
| 210 | |
| 211 | /* USB */ |
| 212 | for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) { |
| 213 | params->PortUsb20Enable[i] = |
| 214 | config->usb2_ports[i].enable; |
| 215 | params->Usb2OverCurrentPin[i] = |
| 216 | config->usb2_ports[i].ocpin; |
| 217 | params->Usb2AfePetxiset[i] = |
| 218 | config->usb2_ports[i].pre_emp_bias; |
| 219 | params->Usb2AfeTxiset[i] = |
| 220 | config->usb2_ports[i].tx_bias; |
| 221 | params->Usb2AfePredeemp[i] = |
| 222 | config->usb2_ports[i].tx_emp_enable; |
| 223 | params->Usb2AfePehalfbit[i] = |
| 224 | config->usb2_ports[i].pre_emp_bit; |
| 225 | } |
| 226 | |
| 227 | for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) { |
| 228 | params->PortUsb30Enable[i] = config->usb3_ports[i].enable; |
| 229 | params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin; |
| 230 | if (config->usb3_ports[i].tx_de_emp) { |
| 231 | params->Usb3HsioTxDeEmphEnable[i] = 1; |
| 232 | params->Usb3HsioTxDeEmph[i] = |
| 233 | config->usb3_ports[i].tx_de_emp; |
| 234 | } |
| 235 | if (config->usb3_ports[i].tx_downscale_amp) { |
| 236 | params->Usb3HsioTxDownscaleAmpEnable[i] = 1; |
| 237 | params->Usb3HsioTxDownscaleAmp[i] = |
| 238 | config->usb3_ports[i].tx_downscale_amp; |
| 239 | } |
| 240 | } |
| 241 | |
| 242 | params->XdciEnable = config->XdciEnable; |
| 243 | |
| 244 | /* eMMC and SD */ |
| 245 | params->ScsEmmcEnabled = config->ScsEmmcEnabled; |
| 246 | params->ScsEmmcHs400Enabled = config->ScsEmmcHs400Enabled; |
| 247 | params->ScsSdCardEnabled = config->ScsSdCardEnabled; |
| 248 | params->ScsUfsEnabled = config->ScsUfsEnabled; |
| 249 | |
| 250 | params->Heci3Enabled = config->Heci3Enabled; |
| 251 | params->Device4Enable = config->Device4Enable; |
| 252 | params->SkipMpInit = config->FspSkipMpInit; |
| 253 | |
| 254 | /* VrConfig Settings for 5 domains |
| 255 | * 0 = System Agent, 1 = IA Core, 2 = Ring, |
| 256 | * 3 = GT unsliced, 4 = GT sliced */ |
| 257 | for (i = 0; i < ARRAY_SIZE(config->domain_vr_config); i++) |
| 258 | fill_vr_domain_config(params, i, &config->domain_vr_config[i]); |
Lijian Zhao | 2f764f7 | 2017-07-14 11:09:10 -0700 | [diff] [blame] | 259 | } |
| 260 | |
| 261 | /* Mainboard GPIO Configuration */ |
| 262 | __attribute__((weak)) void mainboard_silicon_init_params(FSP_S_CONFIG *params) |
| 263 | { |
| 264 | printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); |
| 265 | } |