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Furquan Shaikh26a87472014-06-11 14:48:37 -07001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2014 Google Inc
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; version 2 of
9 * the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
Furquan Shaikh26a87472014-06-11 14:48:37 -070016 * lib_helpers.h: All library function prototypes and macros are defined in this
17 * file.
18 */
19
Furquan Shaikh2157ba72014-08-31 12:21:37 -070020#ifndef __ARCH_LIB_HELPERS_H__
21#define __ARCH_LIB_HELPERS_H__
22
Furquan Shaikh26a87472014-06-11 14:48:37 -070023#define EL0 0
24#define EL1 1
25#define EL2 2
26#define EL3 3
27
28#define CURRENT_EL_MASK 0x3
29#define CURRENT_EL_SHIFT 2
30
Furquan Shaikh0b606732014-09-12 19:12:27 -070031#define SPSR_USE_L 0
32#define SPSR_USE_H 1
33#define SPSR_L_H_MASK 1
34#define SPSR_M_SHIFT 4
35#define SPSR_ERET_32 (1 << SPSR_M_SHIFT)
36#define SPSR_ERET_64 (0 << SPSR_M_SHIFT)
Julius Wernerda3a1462015-05-13 11:19:33 -070037#define SPSR_FIQ (1 << 6)
38#define SPSR_IRQ (1 << 7)
39#define SPSR_SERROR (1 << 8)
40#define SPSR_DEBUG (1 << 9)
41#define SPSR_EXCEPTION_MASK (SPSR_FIQ | SPSR_IRQ | SPSR_SERROR | SPSR_DEBUG)
Furquan Shaikh0b606732014-09-12 19:12:27 -070042
Aaron Durbinf228e8d2014-09-15 14:19:21 -050043#define SCR_NS_SHIFT 0
44#define SCR_NS_MASK (1 << SCR_NS_SHIFT)
45#define SCR_NS_ENABLE (1 << SCR_NS_SHIFT)
46#define SCR_NS_DISABLE (0 << SCR_NS_SHIFT)
47#define SCR_NS SCR_NS_ENABLE
Furquan Shaikh0b606732014-09-12 19:12:27 -070048#define SCR_RES1 (0x3 << 4)
Aaron Durbinf228e8d2014-09-15 14:19:21 -050049#define SCR_IRQ_SHIFT 2
50#define SCR_IRQ_MASK (1 << SCR_IRQ_SHIFT)
51#define SCR_IRQ_ENABLE (1 << SCR_IRQ_SHIFT)
52#define SCR_IRQ_DISABLE (0 << SCR_IRQ_SHIFT)
53#define SCR_FIQ_SHIFT 2
54#define SCR_FIQ_MASK (1 << SCR_FIQ_SHIFT)
55#define SCR_FIQ_ENABLE (1 << SCR_FIQ_SHIFT)
56#define SCR_FIQ_DISABLE (0 << SCR_FIQ_SHIFT)
57#define SCR_EA_SHIFT 3
58#define SCR_EA_MASK (1 << SCR_EA_SHIFT)
59#define SCR_EA_ENABLE (1 << SCR_EA_SHIFT)
60#define SCR_EA_DISABLE (0 << SCR_EA_SHIFT)
Julius Werner7dcf9d52015-10-16 13:10:02 -070061#define SCR_SMD_SHIFT 7
62#define SCR_SMD_MASK (1 << SCR_SMD_SHIFT)
63#define SCR_SMD_DISABLE (1 << SCR_SMD_SHIFT)
64#define SCR_SMD_ENABLE (0 << SCR_SMD_SHIFT)
Furquan Shaikh0b606732014-09-12 19:12:27 -070065#define SCR_HVC_SHIFT 8
Aaron Durbinf228e8d2014-09-15 14:19:21 -050066#define SCR_HVC_MASK (1 << SCR_HVC_SHIFT)
Furquan Shaikh0b606732014-09-12 19:12:27 -070067#define SCR_HVC_DISABLE (0 << SCR_HVC_SHIFT)
68#define SCR_HVC_ENABLE (1 << SCR_HVC_SHIFT)
Aaron Durbinf228e8d2014-09-15 14:19:21 -050069#define SCR_SIF_SHIFT 9
70#define SCR_SIF_MASK (1 << SCR_SIF_SHIFT)
71#define SCR_SIF_ENABLE (1 << SCR_SIF_SHIFT)
72#define SCR_SIF_DISABLE (0 << SCR_SIF_SHIFT)
Furquan Shaikh0b606732014-09-12 19:12:27 -070073#define SCR_RW_SHIFT 10
Aaron Durbinf228e8d2014-09-15 14:19:21 -050074#define SCR_RW_MASK (1 << SCR_RW_SHIFT)
Furquan Shaikh0b606732014-09-12 19:12:27 -070075#define SCR_LOWER_AARCH64 (1 << SCR_RW_SHIFT)
76#define SCR_LOWER_AARCH32 (0 << SCR_RW_SHIFT)
Aaron Durbinf228e8d2014-09-15 14:19:21 -050077#define SCR_ST_SHIFT 11
78#define SCR_ST_MASK (1 << SCR_ST_SHIFT)
79#define SCR_ST_ENABLE (1 << SCR_ST_SHIFT)
80#define SCR_ST_DISABLE (0 << SCR_ST_SHIFT)
81#define SCR_TWI_SHIFT 12
82#define SCR_TWI_MASK (1 << SCR_TWI_SHIFT)
83#define SCR_TWI_ENABLE (1 << SCR_TWI_SHIFT)
84#define SCR_TWI_DISABLE (0 << SCR_TWI_SHIFT)
85#define SCR_TWE_SHIFT 13
86#define SCR_TWE_MASK (1 << SCR_TWE_SHIFT)
87#define SCR_TWE_ENABLE (1 << SCR_TWE_SHIFT)
88#define SCR_TWE_DISABLE (0 << SCR_TWE_SHIFT)
Furquan Shaikh0b606732014-09-12 19:12:27 -070089
90#define HCR_RW_SHIFT 31
91#define HCR_LOWER_AARCH64 (1 << HCR_RW_SHIFT)
92#define HCR_LOWER_AARCH32 (0 << HCR_RW_SHIFT)
93
94#define SCTLR_MMU_ENABLE 1
95#define SCTLR_MMU_DISABLE 0
96#define SCTLR_ACE_SHIFT 1
97#define SCTLR_ACE_ENABLE (1 << SCTLR_ACE_SHIFT)
98#define SCTLR_ACE_DISABLE (0 << SCTLR_ACE_SHIFT)
99#define SCTLR_CACHE_SHIFT 2
100#define SCTLR_CACHE_ENABLE (1 << SCTLR_CACHE_SHIFT)
101#define SCTLR_CACHE_DISABLE (0 << SCTLR_CACHE_SHIFT)
102#define SCTLR_SAE_SHIFT 3
103#define SCTLR_SAE_ENABLE (1 << SCTLR_SAE_SHIFT)
104#define SCTLR_SAE_DISABLE (0 << SCTLR_SAE_SHIFT)
105#define SCTLR_RES1 ((0x3 << 4) | (0x1 << 11) | (0x1 << 16) | \
106 (0x1 << 18) | (0x3 << 22) | (0x3 << 28))
107#define SCTLR_ICE_SHIFT 12
108#define SCTLR_ICE_ENABLE (1 << SCTLR_ICE_SHIFT)
109#define SCTLR_ICE_DISABLE (0 << SCTLR_ICE_SHIFT)
110#define SCTLR_WXN_SHIFT 19
111#define SCTLR_WXN_ENABLE (1 << SCTLR_WXN_SHIFT)
112#define SCTLR_WXN_DISABLE (0 << SCTLR_WXN_SHIFT)
113#define SCTLR_ENDIAN_SHIFT 25
114#define SCTLR_LITTLE_END (0 << SCTLR_ENDIAN_SHIFT)
115#define SCTLR_BIG_END (1 << SCTLR_ENDIAN_SHIFT)
116
Yen Lin900059a2015-03-24 11:15:10 -0700117#define CPTR_EL3_TCPAC_SHIFT (31)
118#define CPTR_EL3_TTA_SHIFT (20)
119#define CPTR_EL3_TFP_SHIFT (10)
120#define CPTR_EL3_TCPAC_DISABLE (0 << CPTR_EL3_TCPAC_SHIFT)
121#define CPTR_EL3_TCPAC_ENABLE (1 << CPTR_EL3_TCPAC_SHIFT)
122#define CPTR_EL3_TTA_DISABLE (0 << CPTR_EL3_TTA_SHIFT)
123#define CPTR_EL3_TTA_ENABLE (1 << CPTR_EL3_TTA_SHIFT)
124#define CPTR_EL3_TFP_DISABLE (0 << CPTR_EL3_TFP_SHIFT)
125#define CPTR_EL3_TFP_ENABLE (1 << CPTR_EL3_TFP_SHIFT)
126
127#define CPACR_TTA_SHIFT (28)
128#define CPACR_TTA_ENABLE (1 << CPACR_TTA_SHIFT)
129#define CPACR_TTA_DISABLE (0 << CPACR_TTA_SHIFT)
130#define CPACR_FPEN_SHIFT (20)
131/*
132 * ARMv8-A spec: Values 0b00 and 0b10 both seem to enable traps from el0 and el1
133 * for fp reg access.
134 */
135#define CPACR_TRAP_FP_EL0_EL1 (0 << CPACR_FPEN_SHIFT)
136#define CPACR_TRAP_FP_EL0 (1 << CPACR_FPEN_SHIFT)
137#define CPACR_TRAP_FP_DISABLE (3 << CPACR_FPEN_SHIFT)
138
Furquan Shaikh2157ba72014-08-31 12:21:37 -0700139#ifdef __ASSEMBLY__
140
141/* Macro to switch to label based on current el */
142.macro switch_el xreg label1 label2 label3
143 mrs \xreg, CurrentEL
144 /* Currently at EL1 */
145 cmp \xreg, #(EL1 << CURRENT_EL_SHIFT)
146 b.eq \label1
147 /* Currently at EL2 */
148 cmp \xreg, #(EL2 << CURRENT_EL_SHIFT)
149 b.eq \label2
150 /* Currently at EL3 */
151 cmp \xreg, #(EL3 << CURRENT_EL_SHIFT)
152 b.eq \label3
153.endm
154
155/* Macro to read sysreg at current EL
156 xreg - reg in which read value needs to be stored
157 sysreg - system reg that is to be read
158*/
159.macro read_current xreg sysreg
160 switch_el \xreg, 101f, 102f, 103f
161101:
162 mrs \xreg, \sysreg\()_el1
163 b 104f
164102:
165 mrs \xreg, \sysreg\()_el2
166 b 104f
167103:
168 mrs \xreg, \sysreg\()_el3
169 b 104f
170104:
171.endm
172
173/* Macro to write sysreg at current EL
174 xreg - reg from which value needs to be written
175 sysreg - system reg that is to be written
176 temp - temp reg that can be used to read current EL
177*/
178.macro write_current sysreg xreg temp
179 switch_el \temp, 101f, 102f, 103f
180101:
181 msr \sysreg\()_el1, \xreg
182 b 104f
183102:
184 msr \sysreg\()_el2, \xreg
185 b 104f
186103:
187 msr \sysreg\()_el3, \xreg
188 b 104f
189104:
190.endm
191
192/* Macro to read sysreg at current EL - 1
193 xreg - reg in which read value needs to be stored
194 sysreg - system reg that is to be read
195*/
196.macro read_lower xreg sysreg
197 switch_el \xreg, 101f, 102f, 103f
198101:
199 b 104f
200102:
201 mrs \xreg, \sysreg\()_el1
202 b 104f
203103:
204 mrs \xreg, \sysreg\()_el2
205 b 104f
206104:
207.endm
208
209/* Macro to write sysreg at current EL - 1
210 xreg - reg from which value needs to be written
211 sysreg - system reg that is to be written
212 temp - temp reg that can be used to read current EL
213*/
214.macro write_lower sysreg xreg temp
215 switch_el \temp, 101f, 102f, 103f
216101:
217 b 104f
218102:
219 msr \sysreg\()_el1, \xreg
220 b 104f
221103:
222 msr \sysreg\()_el2, \xreg
223 b 104f
224104:
225.endm
226
Furquan Shaikhff6d4fa2014-11-21 15:35:17 -0800227/* Macro to read from a register at EL3 only if we are currently at that
228 level. This is required to ensure that we do not attempt to read registers
229 from a level lower than el3. e.g. SCR is available for read only at EL3.
230 IMPORTANT: if EL != EL3, macro silently doesn't perform the read.
231*/
232.macro read_el3 xreg sysreg
233 switch_el \xreg, 402f, 402f, 401f
234401:
235 mrs \xreg, \sysreg\()_el3
236402:
237.endm
238
239/* Macro to write to a register at EL3 only if we are currently at that
240 level. This is required to ensure that we do not attempt to write to
241 registers from a level lower than el3. e.g. SCR is available to write only at
242 EL3.
243 IMPORTANT: if EL != EL3, macro silently doesn't perform the write.
244*/
245.macro write_el3 sysreg xreg temp
246 switch_el \temp, 402f, 402f, 401f
247401:
248 msr \sysreg\()_el3, \xreg
249402:
250.endm
251
Joseph Lod8a50172015-04-17 15:31:59 +0800252/* Macro to read from an el1 register */
253.macro read_el1 xreg sysreg
254 mrs \xreg, \sysreg\()_el1
255.endm
256
257/* Macro to write to an el1 register */
258.macro write_el1 sysreg xreg temp
259 msr \sysreg\()_el1, \xreg
260.endm
261
Jimmy Huang6e415232015-04-01 18:27:12 +0800262/* Macro to read from an el0 register */
263.macro read_el0 xreg sysreg
264 mrs \xreg, \sysreg\()_el0
265.endm
266
267/* Macro to write to an el0 register */
268.macro write_el0 sysreg xreg temp
269 msr \sysreg\()_el0, \xreg
270.endm
271
Furquan Shaikhb17f5802014-11-24 15:12:12 -0800272/* Macro to invalidate all stage 1 TLB entries for current EL */
273.macro tlbiall_current temp
274 switch_el \temp, 401f, 402f, 403f
275401:
276 tlbi alle1
277 b 404f
278402:
279 tlbi alle2
280 b 404f
281403:
282 tlbi alle3
283 b 404f
284404:
285.endm
286
Furquan Shaikh2157ba72014-08-31 12:21:37 -0700287#else
288
Furquan Shaikhe1b87a12014-09-07 18:23:18 -0700289#include <stdint.h>
290
Furquan Shaikh26a87472014-06-11 14:48:37 -0700291#define DAIF_DBG_BIT (1<<3)
292#define DAIF_ABT_BIT (1<<2)
293#define DAIF_IRQ_BIT (1<<1)
294#define DAIF_FIQ_BIT (1<<0)
295
Furquan Shaikhe1b87a12014-09-07 18:23:18 -0700296#define SWITCH_CASE_READ(func, var, type, el) do { \
297 type var = -1; \
298 switch(el) { \
299 case EL1: \
300 var = func##_el1(); \
301 break; \
302 case EL2: \
303 var = func##_el2(); \
304 break; \
305 case EL3: \
306 var = func##_el3(); \
307 break; \
308 } \
309 return var; \
Furquan Shaikh26a87472014-06-11 14:48:37 -0700310 } while(0)
311
Furquan Shaikhe1b87a12014-09-07 18:23:18 -0700312#define SWITCH_CASE_WRITE(func, var, el) do { \
313 switch(el) { \
314 case EL1: \
315 func##_el1(var); \
316 break; \
317 case EL2: \
318 func##_el2(var); \
319 break; \
320 case EL3: \
321 func##_el3(var); \
322 break; \
323 } \
Furquan Shaikh26a87472014-06-11 14:48:37 -0700324 } while(0)
325
Furquan Shaikhe1b87a12014-09-07 18:23:18 -0700326#define SWITCH_CASE_TLBI(func, el) do { \
327 switch(el) { \
328 case EL1: \
Furquan Shaikh26a87472014-06-11 14:48:37 -0700329 func##_el1(); \
330 break; \
Furquan Shaikhe1b87a12014-09-07 18:23:18 -0700331 case EL2: \
Furquan Shaikh26a87472014-06-11 14:48:37 -0700332 func##_el2(); \
333 break; \
Furquan Shaikhe1b87a12014-09-07 18:23:18 -0700334 case EL3: \
Furquan Shaikh26a87472014-06-11 14:48:37 -0700335 func##_el3(); \
336 break; \
337 } \
338 } while(0)
339
340/* PSTATE and special purpose register access functions */
341uint32_t raw_read_current_el(void);
342uint32_t get_current_el(void);
343uint32_t raw_read_daif(void);
344void raw_write_daif(uint32_t daif);
345void enable_debug_exceptions(void);
346void enable_serror_exceptions(void);
347void enable_irq(void);
348void enable_fiq(void);
349void disable_debug_exceptions(void);
350void disable_serror_exceptions(void);
351void disable_irq(void);
352void disable_fiq(void);
353uint64_t raw_read_dlr_el0(void);
354void raw_write_dlr_el0(uint64_t dlr_el0);
355uint64_t raw_read_dspsr_el0(void);
356void raw_write_dspsr_el0(uint64_t dspsr_el0);
357uint64_t raw_read_elr_el1(void);
358void raw_write_elr_el1(uint64_t elr_el1);
359uint64_t raw_read_elr_el2(void);
360void raw_write_elr_el2(uint64_t elr_el2);
361uint64_t raw_read_elr_el3(void);
362void raw_write_elr_el3(uint64_t elr_el3);
363uint64_t raw_read_elr_current(void);
364void raw_write_elr_current(uint64_t elr);
Furquan Shaikhe1b87a12014-09-07 18:23:18 -0700365uint64_t raw_read_elr(uint32_t el);
366void raw_write_elr(uint64_t elr, uint32_t el);
Furquan Shaikh26a87472014-06-11 14:48:37 -0700367uint32_t raw_read_fpcr(void);
368void raw_write_fpcr(uint32_t fpcr);
369uint32_t raw_read_fpsr(void);
370void raw_write_fpsr(uint32_t fpsr);
371uint32_t raw_read_nzcv(void);
372void raw_write_nzcv(uint32_t nzcv);
373uint64_t raw_read_sp_el0(void);
374void raw_write_sp_el0(uint64_t sp_el0);
375uint64_t raw_read_sp_el1(void);
376void raw_write_sp_el1(uint64_t sp_el1);
377uint64_t raw_read_sp_el2(void);
378void raw_write_sp_el2(uint64_t sp_el2);
379uint32_t raw_read_spsel(void);
380void raw_write_spsel(uint32_t spsel);
381uint64_t raw_read_sp_el3(void);
382void raw_write_sp_el3(uint64_t sp_el3);
Furquan Shaikh33dbfd42014-09-07 18:27:16 -0700383uint64_t raw_read_sp_elx(uint32_t el);
384void raw_write_sp_elx(uint64_t sp_elx, uint32_t el);
Furquan Shaikh26a87472014-06-11 14:48:37 -0700385uint32_t raw_read_spsr_abt(void);
386void raw_write_spsr_abt(uint32_t spsr_abt);
387uint32_t raw_read_spsr_el1(void);
388void raw_write_spsr_el1(uint32_t spsr_el1);
389uint32_t raw_read_spsr_el2(void);
390void raw_write_spsr_el2(uint32_t spsr_el2);
391uint32_t raw_read_spsr_el3(void);
392void raw_write_spsr_el3(uint32_t spsr_el3);
393uint32_t raw_read_spsr_current(void);
394void raw_write_spsr_current(uint32_t spsr);
Furquan Shaikhe1b87a12014-09-07 18:23:18 -0700395uint32_t raw_read_spsr(uint32_t el);
396void raw_write_spsr(uint32_t spsr, uint32_t el);
Furquan Shaikh26a87472014-06-11 14:48:37 -0700397uint32_t raw_read_spsr_fiq(void);
398void raw_write_spsr_fiq(uint32_t spsr_fiq);
399uint32_t raw_read_spsr_irq(void);
400void raw_write_spsr_irq(uint32_t spsr_irq);
401uint32_t raw_read_spsr_und(void);
402void raw_write_spsr_und(uint32_t spsr_und);
403
404/* System control register access */
405uint32_t raw_read_actlr_el1(void);
406void raw_write_actlr_el1(uint32_t actlr_el1);
407uint32_t raw_read_actlr_el2(void);
408void raw_write_actlr_el2(uint32_t actlr_el2);
409uint32_t raw_read_actlr_el3(void);
410void raw_write_actlr_el3(uint32_t actlr_el3);
411uint32_t raw_read_actlr_current(void);
412void raw_write_actlr_current(uint32_t actlr);
Furquan Shaikhe1b87a12014-09-07 18:23:18 -0700413uint32_t raw_read_actlr(uint32_t el);
414void raw_write_actlr(uint32_t actlr, uint32_t el);
Furquan Shaikh26a87472014-06-11 14:48:37 -0700415uint32_t raw_read_afsr0_el1(void);
416void raw_write_afsr0_el1(uint32_t afsr0_el1);
417uint32_t raw_read_afsr0_el2(void);
418void raw_write_afsr0_el2(uint32_t afsr0_el2);
419uint32_t raw_read_afsr0_el3(void);
420void raw_write_afsr0_el3(uint32_t afsr0_el3);
421uint32_t raw_read_afsr0_current(void);
422void raw_write_afsr0_current(uint32_t afsr0);
Furquan Shaikhe1b87a12014-09-07 18:23:18 -0700423uint32_t raw_read_afsr0(uint32_t el);
424void raw_write_afsr0(uint32_t afsr0, uint32_t el);
Furquan Shaikh26a87472014-06-11 14:48:37 -0700425uint32_t raw_read_afsr1_el1(void);
426void raw_write_afsr1_el1(uint32_t afsr1_el1);
427uint32_t raw_read_afsr1_el2(void);
428void raw_write_afsr1_el2(uint32_t afsr1_el2);
429uint32_t raw_read_afsr1_el3(void);
430void raw_write_afsr1_el3(uint32_t afsr1_el3);
431uint32_t raw_read_afsr1_current(void);
432void raw_write_afsr1_current(uint32_t afsr1);
Furquan Shaikhe1b87a12014-09-07 18:23:18 -0700433uint32_t raw_read_afsr1(uint32_t el);
434void raw_write_afsr1(uint32_t afsr1, uint32_t el);
Furquan Shaikh26a87472014-06-11 14:48:37 -0700435uint32_t raw_read_aidr_el1(void);
436uint64_t raw_read_amair_el1(void);
437void raw_write_amair_el1(uint64_t amair_el1);
438uint64_t raw_read_amair_el2(void);
439void raw_write_amair_el2(uint64_t amair_el2);
440uint64_t raw_read_amair_el3(void);
441void raw_write_amair_el3(uint64_t amair_el3);
442uint64_t raw_read_amair_current(void);
443void raw_write_amair_current(uint64_t amair);
Furquan Shaikhe1b87a12014-09-07 18:23:18 -0700444uint64_t raw_read_amair(uint32_t el);
445void raw_write_amair(uint64_t amair, uint32_t el);
Furquan Shaikh26a87472014-06-11 14:48:37 -0700446uint32_t raw_read_ccsidr_el1(void);
447uint32_t raw_read_clidr_el1(void);
448uint32_t raw_read_cpacr_el1(void);
449void raw_write_cpacr_el1(uint32_t cpacr_el1);
450uint32_t raw_read_cptr_el2(void);
451void raw_write_cptr_el2(uint32_t cptr_el2);
452uint32_t raw_read_cptr_el3(void);
453void raw_write_cptr_el3(uint32_t cptr_el3);
454uint32_t raw_read_cptr_current(void);
455void raw_write_cptr_current(uint32_t cptr);
456uint32_t raw_read_csselr_el1(void);
457void raw_write_csselr_el1(uint32_t csselr_el1);
458uint32_t raw_read_ctr_el0(void);
459uint32_t raw_read_esr_el1(void);
460void raw_write_esr_el1(uint32_t esr_el1);
461uint32_t raw_read_esr_el2(void);
462void raw_write_esr_el2(uint32_t esr_el2);
463uint32_t raw_read_esr_el3(void);
464void raw_write_esr_el3(uint32_t esr_el3);
465uint32_t raw_read_esr_current(void);
466void raw_write_esr_current(uint32_t esr);
Furquan Shaikhe1b87a12014-09-07 18:23:18 -0700467uint32_t raw_read_esr(uint32_t el);
468void raw_write_esr(uint32_t esr, uint32_t el);
Furquan Shaikh26a87472014-06-11 14:48:37 -0700469uint64_t raw_read_far_el1(void);
470void raw_write_far_el1(uint64_t far_el1);
471uint64_t raw_read_far_el2(void);
472void raw_write_far_el2(uint64_t far_el2);
473uint64_t raw_read_far_el3(void);
474void raw_write_far_el3(uint64_t far_el3);
475uint64_t raw_read_far_current(void);
476void raw_write_far_current(uint64_t far);
Furquan Shaikhe1b87a12014-09-07 18:23:18 -0700477uint64_t raw_read_far(uint32_t el);
478void raw_write_far(uint64_t far, uint32_t el);
Furquan Shaikh26a87472014-06-11 14:48:37 -0700479uint64_t raw_read_hcr_el2(void);
480void raw_write_hcr_el2(uint64_t hcr_el2);
481uint64_t raw_read_aa64pfr0_el1(void);
482uint64_t raw_read_mair_el1(void);
483void raw_write_mair_el1(uint64_t mair_el1);
484uint64_t raw_read_mair_el2(void);
485void raw_write_mair_el2(uint64_t mair_el2);
486uint64_t raw_read_mair_el3(void);
487void raw_write_mair_el3(uint64_t mair_el3);
488uint64_t raw_read_mair_current(void);
489void raw_write_mair_current(uint64_t mair);
Furquan Shaikhe1b87a12014-09-07 18:23:18 -0700490uint64_t raw_read_mair(uint32_t el);
491void raw_write_mair(uint64_t mair, uint32_t el);
Aaron Durbinc913a9c2014-09-03 13:19:46 -0500492uint32_t raw_read_midr_el1(void);
Furquan Shaikh26a87472014-06-11 14:48:37 -0700493uint64_t raw_read_mpidr_el1(void);
494uint32_t raw_read_rmr_el1(void);
495void raw_write_rmr_el1(uint32_t rmr_el1);
496uint32_t raw_read_rmr_el2(void);
497void raw_write_rmr_el2(uint32_t rmr_el2);
498uint32_t raw_read_rmr_el3(void);
499void raw_write_rmr_el3(uint32_t rmr_el3);
500uint32_t raw_read_rmr_current(void);
501void raw_write_rmr_current(uint32_t rmr);
Furquan Shaikhe1b87a12014-09-07 18:23:18 -0700502uint32_t raw_read_rmr(uint32_t el);
503void raw_write_rmr(uint32_t rmr, uint32_t el);
Furquan Shaikh26a87472014-06-11 14:48:37 -0700504uint64_t raw_read_rvbar_el1(void);
505void raw_write_rvbar_el1(uint64_t rvbar_el1);
506uint64_t raw_read_rvbar_el2(void);
507void raw_write_rvbar_el2(uint64_t rvbar_el2);
508uint64_t raw_read_rvbar_el3(void);
509void raw_write_rvbar_el3(uint64_t rvbar_el3);
510uint64_t raw_read_rvbar_current(void);
511void raw_write_rvbar_current(uint64_t rvbar);
Furquan Shaikhe1b87a12014-09-07 18:23:18 -0700512uint64_t raw_read_rvbar(uint32_t el);
513void raw_write_rvbar(uint64_t rvbar, uint32_t el);
Furquan Shaikh26a87472014-06-11 14:48:37 -0700514uint32_t raw_read_scr_el3(void);
515void raw_write_scr_el3(uint32_t scr_el3);
516uint32_t raw_read_sctlr_el1(void);
517void raw_write_sctlr_el1(uint32_t sctlr_el1);
518uint32_t raw_read_sctlr_el2(void);
519void raw_write_sctlr_el2(uint32_t sctlr_el2);
520uint32_t raw_read_sctlr_el3(void);
521void raw_write_sctlr_el3(uint32_t sctlr_el3);
522uint32_t raw_read_sctlr_current(void);
523void raw_write_sctlr_current(uint32_t sctlr);
Furquan Shaikhe1b87a12014-09-07 18:23:18 -0700524uint32_t raw_read_sctlr(uint32_t el);
525void raw_write_sctlr(uint32_t sctlr, uint32_t el);
Furquan Shaikh26a87472014-06-11 14:48:37 -0700526uint64_t raw_read_tcr_el1(void);
527void raw_write_tcr_el1(uint64_t tcr_el1);
528uint32_t raw_read_tcr_el2(void);
529void raw_write_tcr_el2(uint32_t tcr_el2);
530uint32_t raw_read_tcr_el3(void);
531void raw_write_tcr_el3(uint32_t tcr_el3);
Furquan Shaikhb718eab2014-11-21 15:27:05 -0800532uint64_t raw_read_tcr_current(void);
533void raw_write_tcr_current(uint64_t tcr);
534uint64_t raw_read_tcr(uint32_t el);
535void raw_write_tcr(uint64_t tcr, uint32_t el);
Furquan Shaikh26a87472014-06-11 14:48:37 -0700536uint64_t raw_read_ttbr0_el1(void);
537void raw_write_ttbr0_el1(uint64_t ttbr0_el1);
538uint64_t raw_read_ttbr0_el2(void);
539void raw_write_ttbr0_el2(uint64_t ttbr0_el2);
540uint64_t raw_read_ttbr0_el3(void);
541void raw_write_ttbr0_el3(uint64_t ttbr0_el3);
542uint64_t raw_read_ttbr0_current(void);
543void raw_write_ttbr0_current(uint64_t ttbr0);
Furquan Shaikhe1b87a12014-09-07 18:23:18 -0700544uint64_t raw_read_ttbr0(uint32_t el);
545void raw_write_ttbr0(uint64_t ttbr0, uint32_t el);
Furquan Shaikh26a87472014-06-11 14:48:37 -0700546uint64_t raw_read_ttbr1_el1(void);
547void raw_write_ttbr1_el1(uint64_t ttbr1_el1);
548uint64_t raw_read_vbar_el1(void);
549void raw_write_vbar_el1(uint64_t vbar_el1);
550uint64_t raw_read_vbar_el2(void);
551void raw_write_vbar_el2(uint64_t vbar_el2);
552uint64_t raw_read_vbar_el3(void);
553void raw_write_vbar_el3(uint64_t vbar_el3);
554uint64_t raw_read_vbar_current(void);
555void raw_write_vbar_current(uint64_t vbar);
Furquan Shaikhe1b87a12014-09-07 18:23:18 -0700556uint64_t raw_read_vbar(uint32_t el);
557void raw_write_vbar(uint64_t vbar, uint32_t el);
Jimmy Huang6e415232015-04-01 18:27:12 +0800558uint32_t raw_read_cntfrq_el0(void);
559void raw_write_cntfrq_el0(uint32_t cntfrq_el0);
Furquan Shaikh26a87472014-06-11 14:48:37 -0700560
561/* Cache maintenance system instructions */
562void dccisw(uint64_t cisw);
563void dccivac(uint64_t civac);
564void dccsw(uint64_t csw);
565void dccvac(uint64_t cvac);
566void dccvau(uint64_t cvau);
567void dcisw(uint64_t isw);
568void dcivac(uint64_t ivac);
569void dczva(uint64_t zva);
570void iciallu(void);
571void icialluis(void);
572void icivau(uint64_t ivau);
573
574/* TLB maintenance instructions */
575void tlbiall_el1(void);
576void tlbiall_el2(void);
577void tlbiall_el3(void);
578void tlbiall_current(void);
Furquan Shaikhe1b87a12014-09-07 18:23:18 -0700579void tlbiall(uint32_t el);
Furquan Shaikh26a87472014-06-11 14:48:37 -0700580void tlbiallis_el1(void);
581void tlbiallis_el2(void);
582void tlbiallis_el3(void);
583void tlbiallis_current(void);
Furquan Shaikhe1b87a12014-09-07 18:23:18 -0700584void tlbiallis(uint32_t el);
Furquan Shaikh26a87472014-06-11 14:48:37 -0700585void tlbivaa_el1(uint64_t va);
Furquan Shaikh2157ba72014-08-31 12:21:37 -0700586
587#endif // __ASSEMBLY__
588
Martin Rothfd277d82016-01-11 12:47:30 -0700589#endif /* __ARCH_LIB_HELPERS_H__ */