blob: c860ee0fc8b75eb5320b6dde4b6508e23ce2a3c8 [file] [log] [blame]
Furquan Shaikhadabbe52014-09-04 15:32:17 -07001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright 2014 Google Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 */
29
30#include <assert.h>
31#include <stdlib.h>
32#include <stdint.h>
33#include <string.h>
34
35#include <arch/mmu.h>
36#include <arch/lib_helpers.h>
37#include <arch/cache.h>
38
39/* Maximum number of XLAT Tables available based on ttb buffer size */
40static unsigned int max_tables;
41/* Address of ttb buffer */
42static uint64_t *xlat_addr;
43
44static int free_idx;
45static uint8_t ttb_buffer[TTB_DEFAULT_SIZE] __attribute__((aligned(GRANULE_SIZE)));
46
Julius Werner62336812015-05-18 13:11:12 -070047static const char * const tag_to_string[] = {
48 [TYPE_NORMAL_MEM] = "normal",
49 [TYPE_DEV_MEM] = "device",
50 [TYPE_DMA_MEM] = "uncached",
51};
52
Furquan Shaikhadabbe52014-09-04 15:32:17 -070053/*
54 * The usedmem_ranges is used to describe all the memory ranges that are
55 * actually used by payload i.e. _start -> _end in linker script and the
56 * coreboot tables. This is required for two purposes:
57 * 1) During the pre_sysinfo_scan_mmu_setup, these are the only ranges
58 * initialized in the page table as we do not know the entire memory map.
59 * 2) During the post_sysinfo_scan_mmu_setup, these ranges are used to check if
60 * the DMA buffer is being placed in a sane location and does not overlap any of
61 * the used mem ranges.
62 */
Aaron Durbin9425a542014-10-07 23:36:55 -050063static struct mmu_ranges usedmem_ranges;
Furquan Shaikhadabbe52014-09-04 15:32:17 -070064
Furquan Shaikhadabbe52014-09-04 15:32:17 -070065static void __attribute__((noreturn)) mmu_error(void)
66{
67 halt();
68}
69
Julius Werner62336812015-05-18 13:11:12 -070070/* Func : get_block_attr
Furquan Shaikhadabbe52014-09-04 15:32:17 -070071 * Desc : Get block descriptor attributes based on the value of tag in memrange
72 * region
73 */
74static uint64_t get_block_attr(unsigned long tag)
75{
76 uint64_t attr;
77
78 /* We should be in EL2(which is non-secure only) or EL1(non-secure) */
79 attr = BLOCK_NS;
80
81 /* Assuming whole memory is read-write */
82 attr |= BLOCK_AP_RW;
83
84 attr |= BLOCK_ACCESS;
85
86 switch (tag) {
87
88 case TYPE_NORMAL_MEM:
Furquan Shaikhc7692672015-03-31 22:15:07 -070089 attr |= BLOCK_SH_INNER_SHAREABLE;
Furquan Shaikhadabbe52014-09-04 15:32:17 -070090 attr |= (BLOCK_INDEX_MEM_NORMAL << BLOCK_INDEX_SHIFT);
91 break;
92 case TYPE_DEV_MEM:
93 attr |= BLOCK_INDEX_MEM_DEV_NGNRNE << BLOCK_INDEX_SHIFT;
Jimmy Huangc159a0e2015-09-15 15:29:10 +080094 attr |= BLOCK_XN;
Furquan Shaikhadabbe52014-09-04 15:32:17 -070095 break;
96 case TYPE_DMA_MEM:
97 attr |= BLOCK_INDEX_MEM_NORMAL_NC << BLOCK_INDEX_SHIFT;
98 break;
99 }
100
101 return attr;
102}
103
Julius Werner62336812015-05-18 13:11:12 -0700104/* Func : table_desc_valid
Furquan Shaikhadabbe52014-09-04 15:32:17 -0700105 * Desc : Check if a table entry contains valid desc
106 */
107static uint64_t table_desc_valid(uint64_t desc)
108{
109 return((desc & TABLE_DESC) == TABLE_DESC);
110}
111
Julius Werner62336812015-05-18 13:11:12 -0700112/* Func : setup_new_table
113 * Desc : Get next free table from TTB and set it up to match old parent entry.
Furquan Shaikhadabbe52014-09-04 15:32:17 -0700114 */
Julius Werner62336812015-05-18 13:11:12 -0700115static uint64_t *setup_new_table(uint64_t desc, size_t xlat_size)
Furquan Shaikhadabbe52014-09-04 15:32:17 -0700116{
Julius Werner62336812015-05-18 13:11:12 -0700117 uint64_t *new, *entry;
Furquan Shaikhadabbe52014-09-04 15:32:17 -0700118
Julius Werner62336812015-05-18 13:11:12 -0700119 assert(free_idx < max_tables);
Furquan Shaikhadabbe52014-09-04 15:32:17 -0700120
121 new = (uint64_t*)((unsigned char *)xlat_addr + free_idx * GRANULE_SIZE);
122 free_idx++;
123
Julius Werner62336812015-05-18 13:11:12 -0700124 if (!desc) {
125 memset(new, 0, GRANULE_SIZE);
126 } else {
127 /* Can reuse old parent entry, but may need to adjust type. */
128 if (xlat_size == L3_XLAT_SIZE)
129 desc |= PAGE_DESC;
130
131 for (entry = new; (u8 *)entry < (u8 *)new + GRANULE_SIZE;
132 entry++, desc += xlat_size)
133 *entry = desc;
134 }
Furquan Shaikhadabbe52014-09-04 15:32:17 -0700135
136 return new;
137}
138
Julius Werner62336812015-05-18 13:11:12 -0700139/* Func : get_table_from_desc
Furquan Shaikhadabbe52014-09-04 15:32:17 -0700140 * Desc : Get next level table address from table descriptor
141 */
142static uint64_t *get_table_from_desc(uint64_t desc)
143{
144 uint64_t *ptr = (uint64_t*)(desc & XLAT_TABLE_MASK);
145 return ptr;
146}
147
Julius Werner62336812015-05-18 13:11:12 -0700148/* Func: get_next_level_table
149 * Desc: Check if the table entry is a valid descriptor. If not, initialize new
Furquan Shaikhadabbe52014-09-04 15:32:17 -0700150 * table, update the entry and return the table addr. If valid, return the addr.
151 */
Julius Werner62336812015-05-18 13:11:12 -0700152static uint64_t *get_next_level_table(uint64_t *ptr, size_t xlat_size)
Furquan Shaikhadabbe52014-09-04 15:32:17 -0700153{
154 uint64_t desc = *ptr;
155
156 if (!table_desc_valid(desc)) {
Julius Werner62336812015-05-18 13:11:12 -0700157 uint64_t *new_table = setup_new_table(desc, xlat_size);
Furquan Shaikhadabbe52014-09-04 15:32:17 -0700158 desc = ((uint64_t)new_table) | TABLE_DESC;
159 *ptr = desc;
160 }
161 return get_table_from_desc(desc);
162}
163
Julius Werner62336812015-05-18 13:11:12 -0700164/* Func : init_xlat_table
Furquan Shaikhadabbe52014-09-04 15:32:17 -0700165 * Desc : Given a base address and size, it identifies the indices within
166 * different level XLAT tables which map the given base addr. Similar to table
167 * walk, except that all invalid entries during the walk are updated
168 * accordingly. On success, it returns the size of the block/page addressed by
169 * the final table.
170 */
171static uint64_t init_xlat_table(uint64_t base_addr,
172 uint64_t size,
173 uint64_t tag)
174{
Patrick Rudolph57afc5e2018-03-05 09:53:47 +0100175 uint64_t l0_index = (base_addr & L0_ADDR_MASK) >> L0_ADDR_SHIFT;
Julius Werner62336812015-05-18 13:11:12 -0700176 uint64_t l1_index = (base_addr & L1_ADDR_MASK) >> L1_ADDR_SHIFT;
177 uint64_t l2_index = (base_addr & L2_ADDR_MASK) >> L2_ADDR_SHIFT;
178 uint64_t l3_index = (base_addr & L3_ADDR_MASK) >> L3_ADDR_SHIFT;
Furquan Shaikhadabbe52014-09-04 15:32:17 -0700179 uint64_t *table = xlat_addr;
180 uint64_t desc;
181 uint64_t attr = get_block_attr(tag);
182
Patrick Rudolph57afc5e2018-03-05 09:53:47 +0100183 /* L0 entry stores a table descriptor (doesn't support blocks) */
184 table = get_next_level_table(&table[l0_index], L1_XLAT_SIZE);
185
186 /* L1 table lookup */
187 if ((size >= L1_XLAT_SIZE) &&
188 IS_ALIGNED(base_addr, (1UL << L1_ADDR_SHIFT))) {
Jimmy Huang0fd3e792015-04-13 20:28:38 +0800189 /* If block address is aligned and size is greater than
190 * or equal to size addressed by each L1 entry, we can
191 * directly store a block desc */
192 desc = base_addr | BLOCK_DESC | attr;
193 table[l1_index] = desc;
194 /* L2 lookup is not required */
195 return L1_XLAT_SIZE;
Furquan Shaikhadabbe52014-09-04 15:32:17 -0700196 }
197
Patrick Rudolph57afc5e2018-03-05 09:53:47 +0100198 /* L1 entry stores a table descriptor */
199 table = get_next_level_table(&table[l1_index], L2_XLAT_SIZE);
200
201 /* L2 table lookup */
Jimmy Huang0fd3e792015-04-13 20:28:38 +0800202 if ((size >= L2_XLAT_SIZE) &&
203 IS_ALIGNED(base_addr, (1UL << L2_ADDR_SHIFT))) {
Julius Werner62336812015-05-18 13:11:12 -0700204 /* If block address is aligned and size is greater than
205 * or equal to size addressed by each L2 entry, we can
206 * directly store a block desc */
Furquan Shaikhadabbe52014-09-04 15:32:17 -0700207 desc = base_addr | BLOCK_DESC | attr;
208 table[l2_index] = desc;
209 /* L3 lookup is not required */
210 return L2_XLAT_SIZE;
Furquan Shaikhadabbe52014-09-04 15:32:17 -0700211 }
212
Julius Werner62336812015-05-18 13:11:12 -0700213 /* L2 entry stores a table descriptor */
214 table = get_next_level_table(&table[l2_index], L3_XLAT_SIZE);
215
Furquan Shaikhadabbe52014-09-04 15:32:17 -0700216 /* L3 table lookup */
217 desc = base_addr | PAGE_DESC | attr;
218 table[l3_index] = desc;
219 return L3_XLAT_SIZE;
220}
221
Julius Werner62336812015-05-18 13:11:12 -0700222/* Func : sanity_check
223 * Desc : Check address/size alignment of a table or page.
Furquan Shaikhadabbe52014-09-04 15:32:17 -0700224 */
Julius Werner62336812015-05-18 13:11:12 -0700225static void sanity_check(uint64_t addr, uint64_t size)
Furquan Shaikhadabbe52014-09-04 15:32:17 -0700226{
Julius Werner62336812015-05-18 13:11:12 -0700227 assert(!(addr & GRANULE_SIZE_MASK) &&
228 !(size & GRANULE_SIZE_MASK) &&
Patrick Rudolph57afc5e2018-03-05 09:53:47 +0100229 (addr + size < (1UL << BITS_PER_VA)) &&
Julius Werner62336812015-05-18 13:11:12 -0700230 size >= GRANULE_SIZE);
Furquan Shaikhadabbe52014-09-04 15:32:17 -0700231}
232
Julius Werner62336812015-05-18 13:11:12 -0700233/* Func : mmu_config_range
234 * Desc : This function repeatedly calls init_xlat_table with the base
Furquan Shaikhadabbe52014-09-04 15:32:17 -0700235 * address. Based on size returned from init_xlat_table, base_addr is updated
236 * and subsequent calls are made for initializing the xlat table until the whole
237 * region is initialized.
238 */
Julius Werner62336812015-05-18 13:11:12 -0700239void mmu_config_range(void *start, size_t size, uint64_t tag)
Furquan Shaikhadabbe52014-09-04 15:32:17 -0700240{
Julius Werner62336812015-05-18 13:11:12 -0700241 uint64_t base_addr = (uintptr_t)start;
Furquan Shaikhadabbe52014-09-04 15:32:17 -0700242 uint64_t temp_size = size;
243
Julius Werner62336812015-05-18 13:11:12 -0700244 assert(tag < ARRAY_SIZE(tag_to_string));
245 printf("Libpayload: ARM64 MMU: Mapping address range [%p:%p) as %s\n",
246 start, start + size, tag_to_string[tag]);
247 sanity_check(base_addr, temp_size);
Furquan Shaikhadabbe52014-09-04 15:32:17 -0700248
Julius Werner62336812015-05-18 13:11:12 -0700249 while (temp_size)
250 temp_size -= init_xlat_table(base_addr + (size - temp_size),
251 temp_size, tag);
Furquan Shaikhadabbe52014-09-04 15:32:17 -0700252
Julius Werner62336812015-05-18 13:11:12 -0700253 /* ARMv8 MMUs snoop L1 data cache, no need to flush it. */
254 dsb();
255 tlbiall_current();
256 dsb();
257 isb();
Furquan Shaikhadabbe52014-09-04 15:32:17 -0700258}
259
Julius Werner62336812015-05-18 13:11:12 -0700260/* Func : mmu_init
Furquan Shaikhadabbe52014-09-04 15:32:17 -0700261 * Desc : Initialize mmu based on the mmu_memrange passed. ttb_buffer is used as
262 * the base address for xlat tables. TTB_DEFAULT_SIZE defines the max number of
263 * tables that can be used
huang lin7b9bca02016-03-03 15:29:34 +0800264 * Assuming that memory 0-4GiB is device memory.
Furquan Shaikhadabbe52014-09-04 15:32:17 -0700265 */
266uint64_t mmu_init(struct mmu_ranges *mmu_ranges)
267{
Furquan Shaikhadabbe52014-09-04 15:32:17 -0700268 int i = 0;
269
270 xlat_addr = (uint64_t *)&ttb_buffer;
271
272 memset((void*)xlat_addr, 0, GRANULE_SIZE);
273 max_tables = (TTB_DEFAULT_SIZE >> GRANULE_SIZE_SHIFT);
274 free_idx = 1;
275
276 printf("Libpayload ARM64: TTB_BUFFER: 0x%p Max Tables: %d\n",
277 (void*)xlat_addr, max_tables);
278
huang lin7b9bca02016-03-03 15:29:34 +0800279 /*
280 * To keep things simple we start with mapping the entire base 4GB as
281 * device memory. This accommodates various architectures' default
282 * settings (for instance rk3399 mmio starts at 0xf8000000); it is
283 * fine tuned (e.g. mapping DRAM areas as write-back) later in the
284 * boot process.
285 */
286 mmu_config_range(NULL, 0x100000000, TYPE_DEV_MEM);
Furquan Shaikhadabbe52014-09-04 15:32:17 -0700287
Julius Werner62336812015-05-18 13:11:12 -0700288 for (; i < mmu_ranges->used; i++)
289 mmu_config_range((void *)mmu_ranges->entries[i].base,
290 mmu_ranges->entries[i].size,
291 mmu_ranges->entries[i].type);
Furquan Shaikhadabbe52014-09-04 15:32:17 -0700292
293 printf("Libpayload ARM64: MMU init done\n");
294 return 0;
295}
296
297static uint32_t is_mmu_enabled(void)
298{
299 uint32_t sctlr;
300
301 sctlr = raw_read_sctlr_current();
302
303 return (sctlr & SCTLR_M);
304}
305
306/*
307 * Func: mmu_disable
308 * Desc: Invalidate caches and disable mmu
309 */
310void mmu_disable(void)
311{
HC Yen9dd2cf62015-01-12 18:53:01 +0800312 uint32_t el = get_current_el();
Furquan Shaikhadabbe52014-09-04 15:32:17 -0700313 uint32_t sctlr;
314
HC Yen9dd2cf62015-01-12 18:53:01 +0800315 sctlr = raw_read_sctlr(el);
Furquan Shaikhadabbe52014-09-04 15:32:17 -0700316 sctlr &= ~(SCTLR_C | SCTLR_M | SCTLR_I);
317
318 tlbiall_current();
319 dcache_clean_invalidate_all();
320
321 dsb();
322 isb();
323
HC Yen9dd2cf62015-01-12 18:53:01 +0800324 raw_write_sctlr(sctlr, el);
Furquan Shaikhadabbe52014-09-04 15:32:17 -0700325
326 dcache_clean_invalidate_all();
327 dsb();
328 isb();
329}
330
331/*
332 * Func: mmu_enable
333 * Desc: Initialize MAIR, TCR, TTBR and enable MMU by setting appropriate bits
334 * in SCTLR
335 */
336void mmu_enable(void)
337{
338 uint32_t sctlr;
339
340 /* Initialize MAIR indices */
341 raw_write_mair_current(MAIR_ATTRIBUTES);
342
343 /* Invalidate TLBs */
344 tlbiall_current();
345
346 /* Initialize TCR flags */
347 raw_write_tcr_current(TCR_TOSZ | TCR_IRGN0_NM_WBWAC | TCR_ORGN0_NM_WBWAC |
Patrick Rudolph57afc5e2018-03-05 09:53:47 +0100348 TCR_SH0_IS | TCR_TG0_4KB | TCR_PS_256TB |
Furquan Shaikhadabbe52014-09-04 15:32:17 -0700349 TCR_TBI_USED);
350
351 /* Initialize TTBR */
352 raw_write_ttbr0_current((uintptr_t)xlat_addr);
353
Julius Werner62336812015-05-18 13:11:12 -0700354 /* Ensure system register writes are committed before enabling MMU */
Furquan Shaikhadabbe52014-09-04 15:32:17 -0700355 isb();
356
357 /* Enable MMU */
358 sctlr = raw_read_sctlr_current();
359 sctlr |= SCTLR_C | SCTLR_M | SCTLR_I;
360 raw_write_sctlr_current(sctlr);
361
362 isb();
363
364 if(is_mmu_enabled())
365 printf("ARM64: MMU enable done\n");
366 else
367 printf("ARM64: MMU enable failed\n");
368}
369
370/*
Aaron Durbin9425a542014-10-07 23:36:55 -0500371 * Func: mmu_add_memrange
372 * Desc: Adds a new memory range
373 */
Furquan Shaikh69856232014-10-08 01:04:18 -0700374static struct mmu_memrange *mmu_add_memrange(struct mmu_ranges *r,
375 uint64_t base, uint64_t size,
376 uint64_t type)
Aaron Durbin9425a542014-10-07 23:36:55 -0500377{
378 struct mmu_memrange *curr = NULL;
379 int i = r->used;
380
381 if (i < ARRAY_SIZE(r->entries)) {
382 curr = &r->entries[i];
383 curr->base = base;
384 curr->size = size;
385 curr->type = type;
386
387 r->used = i + 1;
388 }
389
390 return curr;
391}
392
Furquan Shaikh69856232014-10-08 01:04:18 -0700393/* Structure to define properties of new memrange request */
394struct mmu_new_range_prop {
395 /* Type of memrange */
396 uint64_t type;
397 /* Size of the range */
398 uint64_t size;
399 /*
400 * If any restrictions on the max addr limit(This addr is exclusive for
401 * the range), else 0
402 */
403 uint64_t lim_excl;
404 /* If any restrictions on alignment of the range base, else 0 */
405 uint64_t align;
406 /*
407 * Function to test whether selected range is fine.
408 * NULL=any range is fine
409 * Return value 1=valid range, 0=otherwise
410 */
411 int (*is_valid_range)(uint64_t, uint64_t);
412 /* From what type of source range should this range be extracted */
413 uint64_t src_type;
414};
415
Aaron Durbin9425a542014-10-07 23:36:55 -0500416/*
Furquan Shaikh69856232014-10-08 01:04:18 -0700417 * Func: mmu_is_range_free
418 * Desc: We need to ensure that the new range being allocated doesnt overlap
419 * with any used memory range. Basically:
420 * 1. Memory ranges used by the payload (usedmem_ranges)
421 * 2. Any area that falls below _end symbol in linker script (Kernel needs to be
422 * loaded in lower areas of memory, So, the payload linker script can have
423 * kernel memory below _start and _end. Thus, we want to make sure we do not
424 * step in those areas as well.
425 * Returns: 1 on success, 0 on error
426 * ASSUMPTION: All the memory used by payload resides below the program
427 * proper. If there is any memory used above the _end symbol, then it should be
428 * marked as used memory in usedmem_ranges during the presysinfo_scan.
Furquan Shaikhadabbe52014-09-04 15:32:17 -0700429 */
Furquan Shaikh69856232014-10-08 01:04:18 -0700430static int mmu_is_range_free(uint64_t r_base,
431 uint64_t r_end)
432{
433 uint64_t payload_end = (uint64_t)&_end;
434 uint64_t i;
435 struct mmu_memrange *r = &usedmem_ranges.entries[0];
436
437 /* Allocate memranges only above payload */
438 if ((r_base <= payload_end) || (r_end <= payload_end))
439 return 0;
440
441 for (i = 0; i < usedmem_ranges.used; i++) {
442 uint64_t start = r[i].base;
443 uint64_t end = start + r[i].size;
444
Julius Werner41ddd4f2016-08-05 10:37:52 -0700445 if ((start < r_end) && (end > r_base))
Furquan Shaikh69856232014-10-08 01:04:18 -0700446 return 0;
447 }
448
449 return 1;
450}
451
452/*
453 * Func: mmu_get_new_range
454 * Desc: Add a requested new memrange. We take as input set of all memranges and
455 * a structure to define the new memrange properties i.e. its type, size,
456 * max_addr it can grow upto, alignment restrictions, source type to take range
457 * from and finally a function pointer to check if the chosen range is valid.
458 */
459static struct mmu_memrange *mmu_get_new_range(struct mmu_ranges *mmu_ranges,
460 struct mmu_new_range_prop *new)
Furquan Shaikhadabbe52014-09-04 15:32:17 -0700461{
462 int i = 0;
463 struct mmu_memrange *r = &mmu_ranges->entries[0];
464
Furquan Shaikh69856232014-10-08 01:04:18 -0700465 if (new->size == 0) {
466 printf("MMU Error: Invalid range size\n");
467 return NULL;
468 }
469
Furquan Shaikhadabbe52014-09-04 15:32:17 -0700470 for (; i < mmu_ranges->used; i++) {
471
Furquan Shaikh69856232014-10-08 01:04:18 -0700472 if ((r[i].type != new->src_type) ||
473 (r[i].size < new->size) ||
474 (new->lim_excl && (r[i].base >= new->lim_excl)))
Furquan Shaikhadabbe52014-09-04 15:32:17 -0700475 continue;
476
477 uint64_t base_addr;
478 uint64_t range_end_addr = r[i].base + r[i].size;
Furquan Shaikhadabbe52014-09-04 15:32:17 -0700479 uint64_t end_addr = range_end_addr;
480
Furquan Shaikh69856232014-10-08 01:04:18 -0700481 /* Make sure we do not go above max if it is non-zero */
482 if (new->lim_excl && (end_addr >= new->lim_excl))
483 end_addr = new->lim_excl;
Furquan Shaikhadabbe52014-09-04 15:32:17 -0700484
Aaron Durbin9425a542014-10-07 23:36:55 -0500485 while (1) {
Furquan Shaikhadabbe52014-09-04 15:32:17 -0700486 /*
Furquan Shaikh69856232014-10-08 01:04:18 -0700487 * In case of alignment requirement,
488 * if end_addr is aligned, then base_addr will be too.
Furquan Shaikhadabbe52014-09-04 15:32:17 -0700489 */
Furquan Shaikh69856232014-10-08 01:04:18 -0700490 if (new->align)
491 end_addr = ALIGN_DOWN(end_addr, new->align);
Furquan Shaikhadabbe52014-09-04 15:32:17 -0700492
Furquan Shaikh69856232014-10-08 01:04:18 -0700493 base_addr = end_addr - new->size;
Furquan Shaikhadabbe52014-09-04 15:32:17 -0700494
495 if (base_addr < r[i].base)
496 break;
Aaron Durbin9425a542014-10-07 23:36:55 -0500497
Furquan Shaikh69856232014-10-08 01:04:18 -0700498 /*
499 * If the selected range is not used and valid for the
500 * user, move ahead with it
501 */
502 if (mmu_is_range_free(base_addr, end_addr) &&
503 ((new->is_valid_range == NULL) ||
504 new->is_valid_range(base_addr, end_addr)))
Aaron Durbin9425a542014-10-07 23:36:55 -0500505 break;
506
507 /* Drop to the next address. */
508 end_addr -= 1;
509 }
Furquan Shaikhadabbe52014-09-04 15:32:17 -0700510
511 if (base_addr < r[i].base)
512 continue;
513
Furquan Shaikhadabbe52014-09-04 15:32:17 -0700514 if (end_addr != range_end_addr) {
515 /* Add a new memrange since we split up one
516 * range crossing the 4GiB boundary or doing an
517 * ALIGN_DOWN on end_addr.
518 */
519 r[i].size -= (range_end_addr - end_addr);
520 if (mmu_add_memrange(mmu_ranges, end_addr,
521 range_end_addr - end_addr,
Furquan Shaikh69856232014-10-08 01:04:18 -0700522 r[i].type) == NULL)
Furquan Shaikhadabbe52014-09-04 15:32:17 -0700523 mmu_error();
524 }
525
Furquan Shaikh69856232014-10-08 01:04:18 -0700526 if (r[i].size == new->size) {
527 r[i].type = new->type;
528 return &r[i];
529 }
Furquan Shaikhadabbe52014-09-04 15:32:17 -0700530
Furquan Shaikh69856232014-10-08 01:04:18 -0700531 r[i].size -= new->size;
532
533 r = mmu_add_memrange(mmu_ranges, base_addr, new->size,
534 new->type);
Furquan Shaikhadabbe52014-09-04 15:32:17 -0700535
536 if (r == NULL)
537 mmu_error();
538
539 return r;
540 }
541
542 /* Should never reach here if everything went fine */
Furquan Shaikh69856232014-10-08 01:04:18 -0700543 printf("ARM64 ERROR: No region allocated\n");
Furquan Shaikhadabbe52014-09-04 15:32:17 -0700544 return NULL;
545}
546
547/*
Furquan Shaikh69856232014-10-08 01:04:18 -0700548 * Func: mmu_alloc_range
549 * Desc: Call get_new_range to get a new memrange which is unused and mark it as
550 * used to avoid same range being allocated for different purposes.
551 */
552static struct mmu_memrange *mmu_alloc_range(struct mmu_ranges *mmu_ranges,
553 struct mmu_new_range_prop *p)
554{
555 struct mmu_memrange *r = mmu_get_new_range(mmu_ranges, p);
556
557 if (r == NULL)
558 return NULL;
559
560 /*
561 * Mark this memrange as used memory. Important since function
562 * can be called multiple times and we do not want to reuse some
563 * range already allocated.
564 */
565 if (mmu_add_memrange(&usedmem_ranges, r->base, r->size, r->type)
566 == NULL)
567 mmu_error();
568
569 return r;
570}
571
572/*
573 * Func: mmu_add_dma_range
574 * Desc: Add a memrange for dma operations. This is special because we want to
575 * initialize this memory as non-cacheable. We have a constraint that the DMA
576 * buffer should be below 4GiB(32-bit only). So, we lookup a TYPE_NORMAL_MEM
577 * from the lowest available addresses and align it to page size i.e. 64KiB.
578 */
579static struct mmu_memrange *mmu_add_dma_range(struct mmu_ranges *mmu_ranges)
580{
581 struct mmu_new_range_prop prop;
582
583 prop.type = TYPE_DMA_MEM;
584 /* DMA_DEFAULT_SIZE is multiple of GRANULE_SIZE */
585 assert((DMA_DEFAULT_SIZE % GRANULE_SIZE) == 0);
586 prop.size = DMA_DEFAULT_SIZE;
Furquan Shaikhe4a642c2015-01-31 23:24:32 -0800587 prop.lim_excl = (uint64_t)CONFIG_LP_DMA_LIM_EXCL * MiB;
Furquan Shaikh69856232014-10-08 01:04:18 -0700588 prop.align = GRANULE_SIZE;
589 prop.is_valid_range = NULL;
590 prop.src_type = TYPE_NORMAL_MEM;
591
592 return mmu_alloc_range(mmu_ranges, &prop);
593}
594
Jimmy Zhangbe1b4f12014-10-09 18:42:00 -0700595static struct mmu_memrange *_mmu_add_fb_range(
596 uint32_t size,
597 struct mmu_ranges *mmu_ranges)
598{
599 struct mmu_new_range_prop prop;
600
601 prop.type = TYPE_DMA_MEM;
602
603 /* make sure to allocate a size of multiple of GRANULE_SIZE */
604 size = ALIGN_UP(size, GRANULE_SIZE);
605 prop.size = size;
606 prop.lim_excl = MIN_64_BIT_ADDR;
607 prop.align = MB_SIZE;
608 prop.is_valid_range = NULL;
609 prop.src_type = TYPE_NORMAL_MEM;
610
611 return mmu_alloc_range(mmu_ranges, &prop);
612}
613
Furquan Shaikh69856232014-10-08 01:04:18 -0700614/*
Furquan Shaikhadabbe52014-09-04 15:32:17 -0700615 * Func: mmu_extract_ranges
616 * Desc: Assumption is that coreboot tables have memranges in sorted
617 * order. So, if there is an opportunity to combine ranges, we do that as
618 * well. Memranges are initialized for both CB_MEM_RAM and CB_MEM_TABLE as
619 * TYPE_NORMAL_MEM.
620 */
621static void mmu_extract_ranges(struct memrange *cb_ranges,
622 uint64_t ncb,
623 struct mmu_ranges *mmu_ranges)
624{
625 int i = 0;
626 struct mmu_memrange *prev_range = NULL;
627
628 /* Extract memory ranges to be mapped */
629 for (; i < ncb; i++) {
630 switch (cb_ranges[i].type) {
631 case CB_MEM_RAM:
632 case CB_MEM_TABLE:
633 if (prev_range && (prev_range->base + prev_range->size
634 == cb_ranges[i].base)) {
635 prev_range->size += cb_ranges[i].size;
636 } else {
637 prev_range = mmu_add_memrange(mmu_ranges,
638 cb_ranges[i].base,
639 cb_ranges[i].size,
640 TYPE_NORMAL_MEM);
641 if (prev_range == NULL)
642 mmu_error();
643 }
644 break;
645 default:
646 break;
647 }
648 }
649}
650
Jimmy Zhangbe1b4f12014-10-09 18:42:00 -0700651static void mmu_add_fb_range(struct mmu_ranges *mmu_ranges)
652{
653 struct mmu_memrange *fb_range;
Aaron Durbin584e0482014-11-18 11:55:33 -0600654 static struct cb_framebuffer modified_fb;
Jimmy Zhangbe1b4f12014-10-09 18:42:00 -0700655 struct cb_framebuffer *framebuffer = lib_sysinfo.framebuffer;
656 uint32_t fb_size;
657
Patrick Georgi5dc87fe2016-04-28 06:03:57 +0200658 /* Check whether framebuffer is needed */
Jimmy Zhangbe1b4f12014-10-09 18:42:00 -0700659 if (framebuffer == NULL)
660 return;
Patrick Georgi5dc87fe2016-04-28 06:03:57 +0200661
Jimmy Zhangbe1b4f12014-10-09 18:42:00 -0700662 fb_size = framebuffer->bytes_per_line * framebuffer->y_resolution;
663 if (!fb_size)
664 return;
665
Patrick Georgi5dc87fe2016-04-28 06:03:57 +0200666 /* framebuffer address has been set already, so just add it as DMA */
667 if (framebuffer->physical_address) {
668 if (mmu_add_memrange(mmu_ranges,
669 framebuffer->physical_address,
670 fb_size,
671 TYPE_DMA_MEM) == NULL)
672 mmu_error();
673 return;
674 }
675
Jimmy Zhangbe1b4f12014-10-09 18:42:00 -0700676 /* Allocate framebuffer */
677 fb_range = _mmu_add_fb_range(fb_size, mmu_ranges);
678 if (fb_range == NULL)
679 mmu_error();
680
Aaron Durbin584e0482014-11-18 11:55:33 -0600681 /*
682 * Set framebuffer address. However, one needs to use a freshly
683 * allocated framebuffer structure because the one in the coreboot
684 * table is part of a checksum calculation. Therefore, one cannot
685 * modify a field without recomputing the necessary checksum
686 * calcuation.
687 */
688 modified_fb = *framebuffer;
689 modified_fb.physical_address = fb_range->base;
690 lib_sysinfo.framebuffer = &modified_fb;
Jimmy Zhangbe1b4f12014-10-09 18:42:00 -0700691}
692
Furquan Shaikhadabbe52014-09-04 15:32:17 -0700693/*
694 * Func: mmu_init_ranges
695 * Desc: Initialize mmu_memranges based on the memranges obtained from coreboot
696 * tables. Also, initialize dma memrange and xlat_addr for ttb buffer.
697 */
698struct mmu_memrange *mmu_init_ranges_from_sysinfo(struct memrange *cb_ranges,
699 uint64_t ncb,
700 struct mmu_ranges *mmu_ranges)
701{
702 struct mmu_memrange *dma_range;
703
Aaron Durbin9425a542014-10-07 23:36:55 -0500704 /* Initialize mmu_ranges to contain no entries. */
705 mmu_ranges->used = 0;
706
Furquan Shaikhadabbe52014-09-04 15:32:17 -0700707 /* Extract ranges from memrange in lib_sysinfo */
708 mmu_extract_ranges(cb_ranges, ncb, mmu_ranges);
709
710 /* Get a range for dma */
711 dma_range = mmu_add_dma_range(mmu_ranges);
712
Jimmy Zhangbe1b4f12014-10-09 18:42:00 -0700713 /* Get a range for framebuffer */
714 mmu_add_fb_range(mmu_ranges);
715
Furquan Shaikhadabbe52014-09-04 15:32:17 -0700716 if (dma_range == NULL)
717 mmu_error();
718
719 return dma_range;
720}
721
722/*
Furquan Shaikhadabbe52014-09-04 15:32:17 -0700723 * Func: mmu_presysinfo_memory_used
724 * Desc: Initializes all the memory used for presysinfo page table
725 * initialization and enabling of MMU. All these ranges are stored in
726 * usedmem_ranges. usedmem_ranges plays an important role in selecting the dma
727 * buffer as well since we check the dma buffer range against the used memory
728 * ranges to prevent any overstepping.
729 */
730void mmu_presysinfo_memory_used(uint64_t base, uint64_t size)
731{
732 uint64_t range_base;
733
734 range_base = ALIGN_DOWN(base, GRANULE_SIZE);
735
736 size += (base - range_base);
737 size = ALIGN_UP(size, GRANULE_SIZE);
738
739 mmu_add_memrange(&usedmem_ranges, range_base, size, TYPE_NORMAL_MEM);
740}
741
742void mmu_presysinfo_enable(void)
743{
744 mmu_init(&usedmem_ranges);
745 mmu_enable();
746}