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Vladimir Serbinenkob1ccccc2014-02-19 22:20:14 +01001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2007-2009 coresystems GmbH
5 * Copyright (C) 2011 Sven Schnelle <svens@stackframe.org>
6 * Copyright (C) 2013 Vladimir Serbinenko <phcoder@gmail.com>
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; version 2 of
11 * the License.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
Vladimir Serbinenkob1ccccc2014-02-19 22:20:14 +010017 */
18
19/* __PRE_RAM__ means: use "unsigned" for device, not a struct. */
20
21#include <stdint.h>
Vladimir Serbinenkob1ccccc2014-02-19 22:20:14 +010022#include <arch/io.h>
Kyösti Mälkkif1b58b72019-03-01 13:43:02 +020023#include <device/pci_ops.h>
Vladimir Serbinenkob1ccccc2014-02-19 22:20:14 +010024#include <device/pci_def.h>
Vladimir Serbinenkob1ccccc2014-02-19 22:20:14 +010025#include <cpu/x86/lapic.h>
Kyösti Mälkki1b7609c2016-06-25 11:40:00 +030026#include <romstage_handoff.h>
Vladimir Serbinenkob1ccccc2014-02-19 22:20:14 +010027#include <console/console.h>
28#include <cpu/x86/bist.h>
Kyösti Mälkki8431fcb2016-06-17 10:00:28 +030029#include <cpu/intel/romstage.h>
Vladimir Serbinenkob1ccccc2014-02-19 22:20:14 +010030#include <ec/acpi/ec.h>
Vladimir Serbinenkob1ccccc2014-02-19 22:20:14 +010031#include <timestamp.h>
Kyösti Mälkkibb805e12014-06-16 09:14:49 +030032#include <arch/acpi.h>
Vladimir Serbinenkob1ccccc2014-02-19 22:20:14 +010033
34#include "arch/early_variables.h"
Edward O'Callaghan77757c22015-01-04 21:33:39 +110035#include <southbridge/intel/ibexpeak/pch.h>
36#include <northbridge/intel/nehalem/nehalem.h>
Vladimir Serbinenkob1ccccc2014-02-19 22:20:14 +010037
Edward O'Callaghan77757c22015-01-04 21:33:39 +110038#include <northbridge/intel/nehalem/raminit.h>
39#include <southbridge/intel/ibexpeak/me.h>
Vladimir Serbinenkob1ccccc2014-02-19 22:20:14 +010040
41static void pch_enable_lpc(void)
42{
43 /* Enable EC, PS/2 Keyboard/Mouse */
44 pci_write_config16(PCH_LPC_DEV, LPC_EN,
45 CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN |
46 COMA_LPC_EN);
47
48 pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, (0x68 & ~3) | 0x00040001);
49
50 pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10);
51
52 pci_write_config32(PCH_LPC_DEV, 0xd0, 0x0);
53 pci_write_config32(PCH_LPC_DEV, 0xdc, 0x8);
54
55 pci_write_config8(PCH_LPC_DEV, GEN_PMCON_3,
56 (pci_read_config8(PCH_LPC_DEV, GEN_PMCON_3) & ~2) | 1);
57
58 pci_write_config32(PCH_LPC_DEV, ETR3,
59 pci_read_config32(PCH_LPC_DEV, ETR3) & ~ETR3_CF9GR);
60}
61
62static void rcba_config(void)
63{
Vladimir Serbinenko33b535f2014-10-19 10:13:14 +020064 southbridge_configure_default_intmap();
65
Vladimir Serbinenkob1ccccc2014-02-19 22:20:14 +010066 static const u32 rcba_dump3[] = {
Vladimir Serbinenkob1ccccc2014-02-19 22:20:14 +010067 /* 3310 */ 0x02060100, 0x0000000f, 0x01020000, 0x80000000,
68 /* 3320 */ 0x00000000, 0x04000000, 0x00000000, 0x00000000,
69 /* 3330 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
70 /* 3340 */ 0x000fffff, 0x00000000, 0x00000000, 0x00000000,
71 /* 3350 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
72 /* 3360 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
73 /* 3370 */ 0x00000000, 0x00000000, 0x7f8fdfff, 0x00000000,
74 /* 3380 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
75 /* 3390 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
76 /* 33a0 */ 0x00003900, 0x00000000, 0x00000000, 0x00000000,
77 /* 33b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
78 /* 33c0 */ 0x00010000, 0x00000000, 0x00000000, 0x0001004b,
79 /* 33d0 */ 0x06000008, 0x00010000, 0x00000000, 0x00000000,
80 /* 33e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
81 /* 33f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
82 /* 3400 */ 0x0000001c, 0x00000080, 0x00000000, 0x00000000,
83 /* 3410 */ 0x00000c61, 0x00000000, 0x16fc1fe1, 0xbf4f001f,
84 /* 3420 */ 0x00000000, 0x00060010, 0x0000001d, 0x00000000,
85 /* 3430 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
86 /* 3440 */ 0xdeaddeed, 0x00000000, 0x00000000, 0x00000000,
87 /* 3450 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
88 /* 3460 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
89 /* 3470 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
90 /* 3480 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
91 /* 3490 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
92 /* 34a0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
93 /* 34b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
94 /* 34c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
95 /* 34d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
96 /* 34e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
97 /* 34f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
98 /* 3500 */ 0x20000557, 0x2000055f, 0x2000074b, 0x2000074b,
99 /* 3510 */ 0x20000557, 0x2000014b, 0x2000074b, 0x2000074b,
100 /* 3520 */ 0x2000074b, 0x2000074b, 0x2000055f, 0x2000055f,
101 /* 3530 */ 0x20000557, 0x2000055f, 0x00000000, 0x00000000,
102 /* 3540 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
103 /* 3550 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
104 /* 3560 */ 0x00000001, 0x000026a3, 0x00040002, 0x01000052,
105 /* 3570 */ 0x02000772, 0x16000f8f, 0x1800ff4f, 0x0001d630,
106 /* 3580 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
107 /* 3590 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
108 /* 35a0 */ 0xfc000201, 0x3c000201, 0x00000000, 0x00000000,
109 /* 35b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
110 /* 35c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
111 /* 35d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
112 /* 35e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
113 /* 35f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
114 /* 3600 */ 0x0a001f00, 0x00000000, 0x00000000, 0x00000001,
115 /* 3610 */ 0x00010000, 0x00000000, 0x00000000, 0x00000000,
Vladimir Serbinenkob1ccccc2014-02-19 22:20:14 +0100116 /* 3620 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
117 /* 3630 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
118 /* 3640 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
119 /* 3650 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
120 /* 3660 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
121 /* 3670 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
122 /* 3680 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
123 /* 3690 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
124 /* 36a0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
Peter Lemenkovf19a07b2018-11-06 08:59:39 +0100125 /* 36b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
126 /* 36c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
127 /* 36d0 */ 0x00000000, 0x089c0018, 0x00000000, 0x00000000,
128 /* 36e0 */ 0x11111111, 0x00000000, 0x00000000, 0x00000000,
Vladimir Serbinenkob1ccccc2014-02-19 22:20:14 +0100129 /* 36f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
Peter Lemenkovf19a07b2018-11-06 08:59:39 +0100130 /* 3700 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
131 /* 3710 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
132 /* 3720 */ 0x00000000, 0x4e564d49, 0x00000000, 0x00000000,
Vladimir Serbinenkob1ccccc2014-02-19 22:20:14 +0100133 };
134 unsigned i;
Vladimir Serbinenko33b535f2014-10-19 10:13:14 +0200135
Vladimir Serbinenkob1ccccc2014-02-19 22:20:14 +0100136 for (i = 0; i < sizeof(rcba_dump3) / 4; i++) {
Vladimir Serbinenko33b535f2014-10-19 10:13:14 +0200137 RCBA32(4 * i + 0x3310) = rcba_dump3[i];
138 (void)RCBA32(4 * i + 0x3310);
Vladimir Serbinenkob1ccccc2014-02-19 22:20:14 +0100139 }
140}
141
142static inline void write_acpi32(u32 addr, u32 val)
143{
144 outl(val, DEFAULT_PMBASE | addr);
145}
146
147static inline void write_acpi16(u32 addr, u16 val)
148{
149 outw(val, DEFAULT_PMBASE | addr);
150}
151
152static inline u32 read_acpi32(u32 addr)
153{
154 return inl(DEFAULT_PMBASE | addr);
155}
156
Edward O'Callaghan08079ec2015-01-08 01:57:43 +1100157// unused func - used for RE
158#if 0
Vladimir Serbinenkob1ccccc2014-02-19 22:20:14 +0100159static inline u16 read_acpi16(u32 addr)
160{
161 return inw(DEFAULT_PMBASE | addr);
162}
Edward O'Callaghan08079ec2015-01-08 01:57:43 +1100163#endif
Vladimir Serbinenkob1ccccc2014-02-19 22:20:14 +0100164
Kyösti Mälkki8431fcb2016-06-17 10:00:28 +0300165void mainboard_romstage_entry(unsigned long bist)
Vladimir Serbinenkob1ccccc2014-02-19 22:20:14 +0100166{
167 u32 reg32;
168 int s3resume = 0;
169 const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 };
170
Vladimir Serbinenkob1ccccc2014-02-19 22:20:14 +0100171 /* SERR pin is confused on reset. Clear NMI. */
172 outb(4, 0x61);
173 outb(0, 0x61);
174
Vladimir Serbinenkob1ccccc2014-02-19 22:20:14 +0100175 if (bist == 0)
176 enable_lapic();
177
178 nehalem_early_initialization(NEHALEM_MOBILE);
179
180 pch_enable_lpc();
181
182 /* Enable GPIOs */
183 pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1);
184 pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10);
185 outl (0x796bd9c3, DEFAULT_GPIOBASE);
186 outl (0x86fec7c2, DEFAULT_GPIOBASE + 4);
187 outl (0xe4e8d7fe, DEFAULT_GPIOBASE + 0xc);
188 outl (0, DEFAULT_GPIOBASE + 0x18);
189 outl (0x00004182, DEFAULT_GPIOBASE + 0x2c);
190 outl (0x123360f8, DEFAULT_GPIOBASE + 0x30);
191 outl (0x1f47bfa8, DEFAULT_GPIOBASE + 0x34);
192 outl (0xfffe7fb6, DEFAULT_GPIOBASE + 0x38);
193
194
195 /* This should probably go away. Until now it is required
196 * and mainboard specific
197 */
198 rcba_config();
199
200 console_init();
201
202 /* Halt if there was a built in self test failure */
203 report_bist_failure(bist);
204
205 /* Read PM1_CNT */
206 reg32 = inl(DEFAULT_PMBASE + 0x04);
207 printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32);
208 if (((reg32 >> 10) & 7) == 5) {
209 u8 reg8;
210 reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2);
211 printk(BIOS_DEBUG, "a2: %02x\n", reg8);
212 if (!(reg8 & 0x20)) {
213 outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04);
214 printk(BIOS_DEBUG, "Bad resume from S3 detected.\n");
215 } else {
Kyösti Mälkkibb805e12014-06-16 09:14:49 +0300216 if (acpi_s3_resume_allowed()) {
217 printk(BIOS_DEBUG, "Resume from S3 detected.\n");
218 s3resume = 1;
219 } else {
220 printk(BIOS_DEBUG,
221 "Resume from S3 detected, but disabled.\n");
222 }
Vladimir Serbinenkob1ccccc2014-02-19 22:20:14 +0100223 }
224 }
225
226 /* Enable SMBUS. */
227 enable_smbus();
228
229 write_acpi16(0x2, 0x0);
230 write_acpi32(0x28, 0x0);
231 write_acpi32(0x2c, 0x0);
232 if (!s3resume) {
233 read_acpi32(0x4);
234 read_acpi32(0x20);
235 read_acpi32(0x34);
236 write_acpi16(0x0, 0x900);
237 write_acpi32(0x20, 0xffff7ffe);
238 write_acpi32(0x34, 0x56974);
239 pci_write_config8(PCH_LPC_DEV, GEN_PMCON_3,
240 pci_read_config8(PCH_LPC_DEV, GEN_PMCON_3) | 2);
241 }
242
243 early_thermal_init();
244
245 timestamp_add_now(TS_BEFORE_INITRAM);
246
247 chipset_init(s3resume);
248 raminit(s3resume, spd_addrmap);
249
250 timestamp_add_now(TS_AFTER_INITRAM);
251
252 intel_early_me_status();
253
254 if (s3resume) {
255 /* Clear SLP_TYPE. This will break stage2 but
256 * we care for that when we get there.
257 */
258 reg32 = inl(DEFAULT_PMBASE + 0x04);
259 outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04);
260 }
261
Kyösti Mälkki1b7609c2016-06-25 11:40:00 +0300262 romstage_handoff_init(s3resume);
Vladimir Serbinenkob1ccccc2014-02-19 22:20:14 +0100263}