Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2012 secunet Security Networks AG |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
| 8 | * published by the Free Software Foundation; version 2 of |
| 9 | * the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, |
| 19 | * MA 02110-1301 USA |
| 20 | */ |
| 21 | |
| 22 | #include <stdint.h> |
Kyösti Mälkki | 931c1dc | 2014-06-30 09:40:19 +0300 | [diff] [blame] | 23 | #include <stdlib.h> |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 24 | #include <arch/cpu.h> |
| 25 | #include <arch/io.h> |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 26 | #include <device/pci_def.h> |
| 27 | #include <device/pnp_def.h> |
| 28 | #include <spd.h> |
| 29 | #include <console/console.h> |
| 30 | #include <lib.h> |
| 31 | #include "delay.h" |
| 32 | #include "gm45.h" |
| 33 | |
| 34 | static const gmch_gfx_t gmch_gfx_types[][5] = { |
| 35 | /* MAX_667MHz MAX_533MHz MAX_400MHz MAX_333MHz MAX_800MHz */ |
| 36 | { GMCH_UNKNOWN, GMCH_UNKNOWN, GMCH_UNKNOWN, GMCH_UNKNOWN, GMCH_UNKNOWN }, |
| 37 | { GMCH_GM47, GMCH_GM45, GMCH_UNKNOWN, GMCH_UNKNOWN, GMCH_GM49 }, |
| 38 | { GMCH_GE45, GMCH_GE45, GMCH_GE45, GMCH_GE45, GMCH_GE45 }, |
| 39 | { GMCH_UNKNOWN, GMCH_GL43, GMCH_GL40, GMCH_UNKNOWN, GMCH_UNKNOWN }, |
| 40 | { GMCH_UNKNOWN, GMCH_GS45, GMCH_GS40, GMCH_UNKNOWN, GMCH_UNKNOWN }, |
| 41 | { GMCH_UNKNOWN, GMCH_UNKNOWN, GMCH_UNKNOWN, GMCH_UNKNOWN, GMCH_UNKNOWN }, |
| 42 | { GMCH_UNKNOWN, GMCH_UNKNOWN, GMCH_UNKNOWN, GMCH_UNKNOWN, GMCH_UNKNOWN }, |
| 43 | { GMCH_PM45, GMCH_PM45, GMCH_PM45, GMCH_PM45, GMCH_PM45 }, |
| 44 | }; |
| 45 | |
| 46 | void get_gmch_info(sysinfo_t *sysinfo) |
| 47 | { |
| 48 | sysinfo->stepping = pci_read_config8(PCI_DEV(0, 0, 0), PCI_CLASS_REVISION); |
| 49 | if ((sysinfo->stepping > STEPPING_B3) && |
| 50 | (sysinfo->stepping != STEPPING_CONVERSION_A1)) |
| 51 | die("Unknown stepping.\n"); |
| 52 | if (sysinfo->stepping <= STEPPING_B3) |
| 53 | printk(BIOS_DEBUG, "Stepping %c%d\n", 'A' + sysinfo->stepping / 4, sysinfo->stepping % 4); |
| 54 | else |
| 55 | printk(BIOS_DEBUG, "Conversion stepping A1\n"); |
| 56 | |
| 57 | const u32 eax = cpuid_ext(0x04, 0).eax; |
| 58 | sysinfo->cores = ((eax >> 26) & 0x3f) + 1; |
| 59 | printk(BIOS_SPEW, "%d CPU cores\n", sysinfo->cores); |
| 60 | |
| 61 | u32 capid = pci_read_config16(PCI_DEV(0, 0, 0), D0F0_CAPID0+8); |
| 62 | if (!(capid & (1<<(79-64)))) { |
| 63 | printk(BIOS_SPEW, "iTPM enabled\n"); |
| 64 | } |
| 65 | |
| 66 | capid = pci_read_config32(PCI_DEV(0, 0, 0), D0F0_CAPID0+4); |
| 67 | if (!(capid & (1<<(57-32)))) { |
| 68 | printk(BIOS_SPEW, "ME enabled\n"); |
| 69 | } |
| 70 | |
| 71 | if (!(capid & (1<<(56-32)))) { |
| 72 | printk(BIOS_SPEW, "AMT enabled\n"); |
| 73 | } |
| 74 | |
| 75 | sysinfo->max_ddr2_mhz = (capid & (1<<(53-32)))?667:800; |
| 76 | printk(BIOS_SPEW, "capable of DDR2 of %d MHz or lower\n", sysinfo->max_ddr2_mhz); |
| 77 | |
| 78 | if (!(capid & (1<<(48-32)))) { |
| 79 | printk(BIOS_SPEW, "VT-d enabled\n"); |
| 80 | } |
| 81 | |
| 82 | const u32 gfx_variant = (capid>>(42-32)) & 0x7; |
| 83 | const u32 render_freq = ((capid>>(50-32) & 0x1) << 2) | ((capid>>(35-32)) & 0x3); |
| 84 | if (render_freq <= 4) |
| 85 | sysinfo->gfx_type = gmch_gfx_types[gfx_variant][render_freq]; |
| 86 | else |
| 87 | sysinfo->gfx_type = GMCH_UNKNOWN; |
| 88 | sysinfo->gs45_low_power_mode = 0; |
| 89 | switch (sysinfo->gfx_type) { |
| 90 | case GMCH_GM45: |
| 91 | printk(BIOS_SPEW, "GMCH: GM45\n"); |
| 92 | break; |
| 93 | case GMCH_GM47: |
| 94 | printk(BIOS_SPEW, "GMCH: GM47\n"); |
| 95 | break; |
| 96 | case GMCH_GM49: |
| 97 | printk(BIOS_SPEW, "GMCH: GM49\n"); |
| 98 | break; |
| 99 | case GMCH_GE45: |
| 100 | printk(BIOS_SPEW, "GMCH: GE45\n"); |
| 101 | break; |
| 102 | case GMCH_GL40: |
| 103 | printk(BIOS_SPEW, "GMCH: GL40\n"); |
| 104 | break; |
| 105 | case GMCH_GL43: |
| 106 | printk(BIOS_SPEW, "GMCH: GL43\n"); |
| 107 | break; |
| 108 | case GMCH_GS40: |
| 109 | printk(BIOS_SPEW, "GMCH: GS40\n"); |
| 110 | break; |
| 111 | case GMCH_GS45: |
| 112 | printk(BIOS_SPEW, "GMCH: GS45, using low power mode by default\n"); |
| 113 | sysinfo->gs45_low_power_mode = 1; |
| 114 | break; |
| 115 | case GMCH_PM45: |
| 116 | printk(BIOS_SPEW, "GMCH: PM45\n"); |
| 117 | break; |
| 118 | case GMCH_UNKNOWN: |
| 119 | printk(BIOS_SPEW, "unknown GMCH\n"); |
| 120 | break; |
| 121 | } |
| 122 | |
| 123 | sysinfo->txt_enabled = !(capid & (1 << (37-32))); |
| 124 | if (sysinfo->txt_enabled) { |
| 125 | printk(BIOS_SPEW, "TXT enabled\n"); |
| 126 | } |
| 127 | |
| 128 | switch (render_freq) { |
| 129 | case 4: |
| 130 | sysinfo->max_render_mhz = 800; |
| 131 | break; |
| 132 | case 0: |
| 133 | sysinfo->max_render_mhz = 667; |
| 134 | break; |
| 135 | case 1: |
| 136 | sysinfo->max_render_mhz = 533; |
| 137 | break; |
| 138 | case 2: |
| 139 | sysinfo->max_render_mhz = 400; |
| 140 | break; |
| 141 | case 3: |
| 142 | sysinfo->max_render_mhz = 333; |
| 143 | break; |
| 144 | default: |
| 145 | printk(BIOS_SPEW, "Unknown render frequency\n"); |
| 146 | sysinfo->max_render_mhz = 0; |
| 147 | break; |
| 148 | } |
| 149 | if (sysinfo->max_render_mhz != 0) { |
| 150 | printk(BIOS_SPEW, "Render frequency: %d MHz\n", sysinfo->max_render_mhz); |
| 151 | } |
| 152 | |
| 153 | if (!(capid & (1<<(33-32)))) { |
| 154 | printk(BIOS_SPEW, "IGD enabled\n"); |
| 155 | } |
| 156 | |
| 157 | if (!(capid & (1<<(32-32)))) { |
| 158 | printk(BIOS_SPEW, "PCIe-to-GMCH enabled\n"); |
| 159 | } |
| 160 | |
| 161 | capid = pci_read_config32(PCI_DEV(0, 0, 0), D0F0_CAPID0); |
| 162 | |
| 163 | u32 ddr_cap = capid>>30 & 0x3; |
| 164 | switch (ddr_cap) { |
| 165 | case 0: |
| 166 | sysinfo->max_ddr3_mt = 1067; |
| 167 | break; |
| 168 | case 1: |
| 169 | sysinfo->max_ddr3_mt = 800; |
| 170 | break; |
| 171 | case 2: |
| 172 | case 3: |
| 173 | printk(BIOS_SPEW, "GMCH not DDR3 capable\n"); |
| 174 | sysinfo->max_ddr3_mt = 0; |
| 175 | break; |
| 176 | } |
| 177 | if (sysinfo->max_ddr3_mt != 0) { |
| 178 | printk(BIOS_SPEW, "GMCH supports DDR3 with %d MT or less\n", sysinfo->max_ddr3_mt); |
| 179 | } |
| 180 | |
| 181 | const unsigned max_fsb = (capid >> 28) & 0x3; |
| 182 | switch (max_fsb) { |
| 183 | case 1: |
| 184 | sysinfo->max_fsb_mhz = 1067; |
| 185 | break; |
| 186 | case 2: |
| 187 | sysinfo->max_fsb_mhz = 800; |
| 188 | break; |
| 189 | case 3: |
| 190 | sysinfo->max_fsb_mhz = 667; |
| 191 | break; |
| 192 | default: |
| 193 | die("unknown FSB capability\n"); |
| 194 | break; |
| 195 | } |
| 196 | if (sysinfo->max_fsb_mhz != 0) { |
| 197 | printk(BIOS_SPEW, "GMCH supports FSB with up to %d MHz\n", sysinfo->max_fsb_mhz); |
| 198 | } |
| 199 | sysinfo->max_fsb = max_fsb - 1; |
| 200 | } |
| 201 | |
| 202 | /* |
| 203 | * Detect if the system went through an interrupted RAM init or is incon- |
| 204 | * sistent. If so, initiate a cold reboot. Otherwise mark the system to be |
| 205 | * in RAM init, so this function would detect it on an erreneous reboot. |
| 206 | */ |
| 207 | void enter_raminit_or_reset(void) |
| 208 | { |
| 209 | /* Interrupted RAM init or inconsistent system? */ |
| 210 | u8 reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); |
| 211 | |
| 212 | if (reg8 & (1 << 2)) { /* S4-assertion-width violation */ |
| 213 | /* Ignore S4-assertion-width violation like original BIOS. */ |
| 214 | printk(BIOS_WARNING, |
| 215 | "WARNING: Ignoring S4-assertion-width violation.\n"); |
| 216 | /* Bit2 is R/WC, so it will clear itself below. */ |
| 217 | } |
| 218 | |
| 219 | if (reg8 & (1 << 7)) { /* interrupted RAM init */ |
| 220 | /* Don't enable S4-assertion stretch. Makes trouble on roda/rk9. |
| 221 | reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); |
| 222 | pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8 | 0x08); |
| 223 | */ |
| 224 | |
| 225 | /* Clear bit7. */ |
| 226 | pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8 & ~(1 << 7)); |
| 227 | |
| 228 | printk(BIOS_INFO, "Interrupted RAM init, reset required.\n"); |
| 229 | gm45_early_reset(); |
| 230 | } |
| 231 | /* Mark system to be in RAM init. */ |
| 232 | pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8 | (1 << 7)); |
| 233 | } |
| 234 | |
| 235 | |
| 236 | /* For a detected DIMM, test the value of an SPD byte to |
| 237 | match the expected value after masking some bits. */ |
Vladimir Serbinenko | c4d8948 | 2014-06-05 09:14:48 +0200 | [diff] [blame] | 238 | static int test_dimm(sysinfo_t *const sysinfo, |
| 239 | int dimm, int addr, int bitmask, int expected) |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 240 | { |
Vladimir Serbinenko | c4d8948 | 2014-06-05 09:14:48 +0200 | [diff] [blame] | 241 | return (smbus_read_byte(sysinfo->spd_map[dimm], addr) & bitmask) == expected; |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 242 | } |
| 243 | |
| 244 | /* This function dies if dimm is unsuitable for the chipset. */ |
Vladimir Serbinenko | c4d8948 | 2014-06-05 09:14:48 +0200 | [diff] [blame] | 245 | static void verify_ddr3_dimm(sysinfo_t *const sysinfo, int dimm) |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 246 | { |
Vladimir Serbinenko | c4d8948 | 2014-06-05 09:14:48 +0200 | [diff] [blame] | 247 | if (!test_dimm(sysinfo, dimm, 3, 15, 3)) |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 248 | die("Chipset only supports SO-DIMM\n"); |
| 249 | |
Vladimir Serbinenko | c4d8948 | 2014-06-05 09:14:48 +0200 | [diff] [blame] | 250 | if (!test_dimm(sysinfo, dimm, 8, 0x18, 0)) |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 251 | die("Chipset doesn't support ECC RAM\n"); |
| 252 | |
Vladimir Serbinenko | c4d8948 | 2014-06-05 09:14:48 +0200 | [diff] [blame] | 253 | if (!test_dimm(sysinfo, dimm, 7, 0x38, 0) && |
| 254 | !test_dimm(sysinfo, dimm, 7, 0x38, 8)) |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 255 | die("Chipset wants single or double sided DIMMs\n"); |
| 256 | |
Vladimir Serbinenko | c4d8948 | 2014-06-05 09:14:48 +0200 | [diff] [blame] | 257 | if (!test_dimm(sysinfo, dimm, 7, 7, 1) && |
| 258 | !test_dimm(sysinfo, dimm, 7, 7, 2)) |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 259 | die("Chipset requires x8 or x16 width\n"); |
| 260 | |
Vladimir Serbinenko | c4d8948 | 2014-06-05 09:14:48 +0200 | [diff] [blame] | 261 | if (!test_dimm(sysinfo, dimm, 4, 0x0f, 0) && |
| 262 | !test_dimm(sysinfo, dimm, 4, 0x0f, 1) && |
| 263 | !test_dimm(sysinfo, dimm, 4, 0x0f, 2) && |
| 264 | !test_dimm(sysinfo, dimm, 4, 0x0f, 3)) |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 265 | die("Chipset requires 256Mb, 512Mb, 1Gb or 2Gb chips."); |
| 266 | |
Vladimir Serbinenko | c4d8948 | 2014-06-05 09:14:48 +0200 | [diff] [blame] | 267 | if (!test_dimm(sysinfo, dimm, 4, 0x70, 0)) |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 268 | die("Chipset requires 8 banks on DDR3\n"); |
| 269 | |
| 270 | /* How to check if burst length is 8? |
| 271 | Other values are not supported, are they even possible? */ |
| 272 | |
Vladimir Serbinenko | c4d8948 | 2014-06-05 09:14:48 +0200 | [diff] [blame] | 273 | if (!test_dimm(sysinfo, dimm, 10, 0xff, 1)) |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 274 | die("Code assumes 1/8ns MTB\n"); |
| 275 | |
Vladimir Serbinenko | c4d8948 | 2014-06-05 09:14:48 +0200 | [diff] [blame] | 276 | if (!test_dimm(sysinfo, dimm, 11, 0xff, 8)) |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 277 | die("Code assumes 1/8ns MTB\n"); |
| 278 | |
Vladimir Serbinenko | c4d8948 | 2014-06-05 09:14:48 +0200 | [diff] [blame] | 279 | if (!test_dimm(sysinfo, dimm, 62, 0x9f, 0) && |
| 280 | !test_dimm(sysinfo, dimm, 62, 0x9f, 1) && |
| 281 | !test_dimm(sysinfo, dimm, 62, 0x9f, 2) && |
| 282 | !test_dimm(sysinfo, dimm, 62, 0x9f, 3) && |
| 283 | !test_dimm(sysinfo, dimm, 62, 0x9f, 5)) |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 284 | die("Only raw card types A, B, C, D and F are supported.\n"); |
| 285 | } |
| 286 | |
| 287 | /* For every detected DIMM, test if it's suitable for the chipset. */ |
Vladimir Serbinenko | c4d8948 | 2014-06-05 09:14:48 +0200 | [diff] [blame] | 288 | static void verify_ddr3(sysinfo_t *const sysinfo, int mask) |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 289 | { |
| 290 | int cur = 0; |
| 291 | while (mask) { |
| 292 | if (mask & 1) { |
Vladimir Serbinenko | c4d8948 | 2014-06-05 09:14:48 +0200 | [diff] [blame] | 293 | verify_ddr3_dimm(sysinfo, cur); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 294 | } |
| 295 | mask >>= 1; |
| 296 | cur++; |
| 297 | } |
| 298 | } |
| 299 | |
| 300 | |
| 301 | typedef struct { |
| 302 | int dimm_mask; |
| 303 | struct { |
| 304 | unsigned int rows; |
| 305 | unsigned int cols; |
| 306 | unsigned int chip_capacity; |
| 307 | unsigned int banks; |
| 308 | unsigned int ranks; |
| 309 | unsigned int cas_latencies; |
| 310 | unsigned int tAAmin; |
| 311 | unsigned int tCKmin; |
| 312 | unsigned int width; |
| 313 | unsigned int tRAS; |
| 314 | unsigned int tRP; |
| 315 | unsigned int tRCD; |
| 316 | unsigned int tWR; |
| 317 | unsigned int page_size; |
| 318 | unsigned int raw_card; |
| 319 | } channel[2]; |
| 320 | } spdinfo_t; |
| 321 | /* |
| 322 | * This function collects RAM characteristics from SPD, assuming that RAM |
| 323 | * is generally within chipset's requirements, since verify_ddr3() passed. |
| 324 | */ |
Vladimir Serbinenko | c4d8948 | 2014-06-05 09:14:48 +0200 | [diff] [blame] | 325 | static void collect_ddr3(sysinfo_t *const sysinfo, spdinfo_t *const config) |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 326 | { |
| 327 | int mask = config->dimm_mask; |
| 328 | int cur = 0; |
| 329 | while (mask != 0) { |
Vladimir Serbinenko | c4d8948 | 2014-06-05 09:14:48 +0200 | [diff] [blame] | 330 | /* FIXME: support several dimms on same channel. */ |
| 331 | if ((mask & 1) && sysinfo->spd_map[2 * cur]) { |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 332 | int tmp; |
Vladimir Serbinenko | c4d8948 | 2014-06-05 09:14:48 +0200 | [diff] [blame] | 333 | const int smb_addr = sysinfo->spd_map[2 * cur]; |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 334 | |
| 335 | config->channel[cur].rows = ((smbus_read_byte(smb_addr, 5) >> 3) & 7) + 12; |
| 336 | config->channel[cur].cols = (smbus_read_byte(smb_addr, 5) & 7) + 9; |
| 337 | |
| 338 | config->channel[cur].chip_capacity = smbus_read_byte(smb_addr, 4) & 0xf; |
| 339 | |
| 340 | config->channel[cur].banks = 8; /* GM45 only accepts this for DDR3. |
| 341 | verify_ddr3() fails for other values. */ |
| 342 | config->channel[cur].ranks = ((smbus_read_byte(smb_addr, 7) >> 3) & 7) + 1; |
| 343 | |
| 344 | config->channel[cur].cas_latencies = |
| 345 | ((smbus_read_byte(smb_addr, 15) << 8) | smbus_read_byte(smb_addr, 14)) |
| 346 | << 4; /* so bit x is CAS x */ |
| 347 | config->channel[cur].tAAmin = smbus_read_byte(smb_addr, 16); /* in MTB */ |
| 348 | config->channel[cur].tCKmin = smbus_read_byte(smb_addr, 12); /* in MTB */ |
| 349 | |
| 350 | config->channel[cur].width = smbus_read_byte(smb_addr, 7) & 7; |
| 351 | config->channel[cur].page_size = config->channel[cur].width * |
| 352 | (1 << config->channel[cur].cols); /* in Bytes */ |
| 353 | |
| 354 | tmp = smbus_read_byte(smb_addr, 21); |
| 355 | config->channel[cur].tRAS = smbus_read_byte(smb_addr, 22) | ((tmp & 0xf) << 8); |
| 356 | config->channel[cur].tRP = smbus_read_byte(smb_addr, 20); |
| 357 | config->channel[cur].tRCD = smbus_read_byte(smb_addr, 18); |
| 358 | config->channel[cur].tWR = smbus_read_byte(smb_addr, 17); |
| 359 | |
| 360 | config->channel[cur].raw_card = smbus_read_byte(smb_addr, 62) & 0x1f; |
| 361 | } |
| 362 | cur++; |
Vladimir Serbinenko | c4d8948 | 2014-06-05 09:14:48 +0200 | [diff] [blame] | 363 | mask >>= 2; |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 364 | } |
| 365 | } |
| 366 | |
Edward O'Callaghan | 7116ac8 | 2014-07-08 01:53:24 +1000 | [diff] [blame] | 367 | #define ROUNDUP_DIV(val, by) CEIL_DIV(val, by) |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 368 | #define ROUNDUP_DIV_THIS(val, by) val = ROUNDUP_DIV(val, by) |
| 369 | static fsb_clock_t read_fsb_clock(void) |
| 370 | { |
| 371 | switch (MCHBAR32(CLKCFG_MCHBAR) & CLKCFG_FSBCLK_MASK) { |
| 372 | case 6: |
| 373 | return FSB_CLOCK_1067MHz; |
| 374 | case 2: |
| 375 | return FSB_CLOCK_800MHz; |
| 376 | case 3: |
| 377 | return FSB_CLOCK_667MHz; |
| 378 | default: |
| 379 | die("Unsupported FSB clock.\n"); |
| 380 | } |
| 381 | } |
| 382 | static mem_clock_t clock_index(const unsigned int clock) |
| 383 | { |
| 384 | switch (clock) { |
| 385 | case 533: return MEM_CLOCK_533MHz; |
| 386 | case 400: return MEM_CLOCK_400MHz; |
| 387 | case 333: return MEM_CLOCK_333MHz; |
| 388 | default: die("Unknown clock value.\n"); |
| 389 | } |
| 390 | return -1; /* Won't be reached. */ |
| 391 | } |
| 392 | static void normalize_clock(unsigned int *const clock) |
| 393 | { |
| 394 | if (*clock >= 533) |
| 395 | *clock = 533; |
| 396 | else if (*clock >= 400) |
| 397 | *clock = 400; |
| 398 | else if (*clock >= 333) |
| 399 | *clock = 333; |
| 400 | else |
| 401 | *clock = 0; |
| 402 | } |
| 403 | static void lower_clock(unsigned int *const clock) |
| 404 | { |
| 405 | --*clock; |
| 406 | normalize_clock(clock); |
| 407 | } |
| 408 | static unsigned int find_common_clock_cas(sysinfo_t *const sysinfo, |
| 409 | const spdinfo_t *const spdinfo) |
| 410 | { |
| 411 | /* various constraints must be fulfilled: |
| 412 | CAS * tCK < 20ns == 160MTB |
| 413 | tCK_max >= tCK >= tCK_min |
| 414 | CAS >= roundup(tAA_min/tCK) |
| 415 | CAS supported |
| 416 | Clock(MHz) = 1000 / tCK(ns) |
| 417 | Clock(MHz) = 8000 / tCK(MTB) |
| 418 | AND BTW: Clock(MT) = 2000 / tCK(ns) - intel uses MTs but calls them MHz |
| 419 | */ |
| 420 | int i; |
| 421 | |
| 422 | /* Calculate common cas_latencies mask, tCKmin and tAAmin. */ |
| 423 | unsigned int cas_latencies = (unsigned int)-1; |
| 424 | unsigned int tCKmin = 0, tAAmin = 0; |
| 425 | FOR_EACH_POPULATED_CHANNEL(sysinfo->dimms, i) { |
| 426 | cas_latencies &= spdinfo->channel[i].cas_latencies; |
| 427 | if (spdinfo->channel[i].tCKmin > tCKmin) |
| 428 | tCKmin = spdinfo->channel[i].tCKmin; |
| 429 | if (spdinfo->channel[i].tAAmin > tAAmin) |
| 430 | tAAmin = spdinfo->channel[i].tAAmin; |
| 431 | } |
| 432 | |
| 433 | /* Get actual value of fsb clock. */ |
| 434 | sysinfo->selected_timings.fsb_clock = read_fsb_clock(); |
| 435 | unsigned int fsb_mhz = 0; |
| 436 | switch (sysinfo->selected_timings.fsb_clock) { |
| 437 | case FSB_CLOCK_1067MHz: fsb_mhz = 1067; break; |
| 438 | case FSB_CLOCK_800MHz: fsb_mhz = 800; break; |
| 439 | case FSB_CLOCK_667MHz: fsb_mhz = 667; break; |
| 440 | } |
| 441 | |
| 442 | unsigned int clock = 8000 / tCKmin; |
| 443 | if ((clock > sysinfo->max_ddr3_mt / 2) || (clock > fsb_mhz / 2)) { |
| 444 | int new_clock = min(sysinfo->max_ddr3_mt / 2, fsb_mhz / 2); |
| 445 | printk(BIOS_SPEW, "DIMMs support %d MHz, but chipset only runs at up to %d. Limiting...\n", |
| 446 | clock, new_clock); |
| 447 | clock = new_clock; |
| 448 | } |
| 449 | normalize_clock(&clock); |
| 450 | |
| 451 | /* Find compatible clock / CAS pair. */ |
| 452 | unsigned int tCKproposed; |
| 453 | unsigned int CAS; |
| 454 | while (1) { |
| 455 | if (!clock) |
| 456 | die("Couldn't find compatible clock / CAS settings.\n"); |
| 457 | tCKproposed = 8000 / clock; |
| 458 | CAS = ROUNDUP_DIV(tAAmin, tCKproposed); |
| 459 | printk(BIOS_SPEW, "Trying CAS %u, tCK %u.\n", CAS, tCKproposed); |
| 460 | for (; CAS <= DDR3_MAX_CAS; ++CAS) |
| 461 | if (cas_latencies & (1 << CAS)) |
| 462 | break; |
| 463 | if ((CAS <= DDR3_MAX_CAS) && (CAS * tCKproposed < 160)) { |
| 464 | /* Found good CAS. */ |
| 465 | printk(BIOS_SPEW, "Found compatible clock / CAS pair: %u / %u.\n", clock, CAS); |
| 466 | break; |
| 467 | } |
| 468 | lower_clock(&clock); |
| 469 | } |
| 470 | sysinfo->selected_timings.CAS = CAS; |
| 471 | sysinfo->selected_timings.mem_clock = clock_index(clock); |
| 472 | |
| 473 | return tCKproposed; |
| 474 | } |
| 475 | |
| 476 | static void calculate_derived_timings(sysinfo_t *const sysinfo, |
| 477 | const unsigned int tCLK, |
| 478 | const spdinfo_t *const spdinfo) |
| 479 | { |
| 480 | int i; |
| 481 | |
| 482 | /* Calculate common tRASmin, tRPmin, tRCDmin and tWRmin. */ |
| 483 | unsigned int tRASmin = 0, tRPmin = 0, tRCDmin = 0, tWRmin = 0; |
| 484 | FOR_EACH_POPULATED_CHANNEL(sysinfo->dimms, i) { |
| 485 | if (spdinfo->channel[i].tRAS > tRASmin) |
| 486 | tRASmin = spdinfo->channel[i].tRAS; |
| 487 | if (spdinfo->channel[i].tRP > tRPmin) |
| 488 | tRPmin = spdinfo->channel[i].tRP; |
| 489 | if (spdinfo->channel[i].tRCD > tRCDmin) |
| 490 | tRCDmin = spdinfo->channel[i].tRCD; |
| 491 | if (spdinfo->channel[i].tWR > tWRmin) |
| 492 | tWRmin = spdinfo->channel[i].tWR; |
| 493 | } |
| 494 | ROUNDUP_DIV_THIS(tRASmin, tCLK); |
| 495 | ROUNDUP_DIV_THIS(tRPmin, tCLK); |
| 496 | ROUNDUP_DIV_THIS(tRCDmin, tCLK); |
| 497 | ROUNDUP_DIV_THIS(tWRmin, tCLK); |
| 498 | |
| 499 | /* Lookup tRFC and calculate common tRFCmin. */ |
| 500 | const unsigned int tRFC_from_clock_and_cap[][4] = { |
| 501 | /* CAP_256M CAP_512M CAP_1G CAP_2G */ |
| 502 | /* 533MHz */ { 40, 56, 68, 104 }, |
| 503 | /* 400MHz */ { 30, 42, 51, 78 }, |
| 504 | /* 333MHz */ { 25, 35, 43, 65 }, |
| 505 | }; |
| 506 | unsigned int tRFCmin = 0; |
| 507 | FOR_EACH_POPULATED_CHANNEL(sysinfo->dimms, i) { |
| 508 | const unsigned int tRFC = tRFC_from_clock_and_cap |
| 509 | [sysinfo->selected_timings.mem_clock][spdinfo->channel[i].chip_capacity]; |
| 510 | if (tRFC > tRFCmin) |
| 511 | tRFCmin = tRFC; |
| 512 | } |
| 513 | |
| 514 | /* Calculate common tRD from CAS and FSB and DRAM clocks. */ |
| 515 | unsigned int tRDmin = sysinfo->selected_timings.CAS; |
| 516 | switch (sysinfo->selected_timings.fsb_clock) { |
| 517 | case FSB_CLOCK_667MHz: |
| 518 | tRDmin += 1; |
| 519 | break; |
| 520 | case FSB_CLOCK_800MHz: |
| 521 | tRDmin += 2; |
| 522 | break; |
| 523 | case FSB_CLOCK_1067MHz: |
| 524 | tRDmin += 3; |
| 525 | if (sysinfo->selected_timings.mem_clock == MEM_CLOCK_1067MT) |
| 526 | tRDmin += 1; |
| 527 | break; |
| 528 | } |
| 529 | |
| 530 | /* Calculate common tRRDmin. */ |
| 531 | unsigned int tRRDmin = 0; |
| 532 | FOR_EACH_POPULATED_CHANNEL(sysinfo->dimms, i) { |
| 533 | unsigned int tRRD = 2 + (spdinfo->channel[i].page_size / 1024); |
| 534 | if (sysinfo->selected_timings.mem_clock == MEM_CLOCK_1067MT) |
| 535 | tRRD += (spdinfo->channel[i].page_size / 1024); |
| 536 | if (tRRD > tRRDmin) |
| 537 | tRRDmin = tRRD; |
| 538 | } |
| 539 | |
| 540 | /* Lookup and calculate common tFAWmin. */ |
| 541 | unsigned int tFAW_from_pagesize_and_clock[][3] = { |
| 542 | /* 533MHz 400MHz 333MHz */ |
| 543 | /* 1K */ { 20, 15, 13 }, |
| 544 | /* 2K */ { 27, 20, 17 }, |
| 545 | }; |
| 546 | unsigned int tFAWmin = 0; |
| 547 | FOR_EACH_POPULATED_CHANNEL(sysinfo->dimms, i) { |
| 548 | const unsigned int tFAW = tFAW_from_pagesize_and_clock |
| 549 | [spdinfo->channel[i].page_size / 1024 - 1] |
| 550 | [sysinfo->selected_timings.mem_clock]; |
| 551 | if (tFAW > tFAWmin) |
| 552 | tFAWmin = tFAW; |
| 553 | } |
| 554 | |
| 555 | /* Refresh rate is fixed. */ |
| 556 | unsigned int tWL; |
| 557 | if (sysinfo->selected_timings.mem_clock == MEM_CLOCK_1067MT) { |
| 558 | tWL = 6; |
| 559 | } else { |
| 560 | tWL = 5; |
| 561 | } |
| 562 | |
| 563 | printk(BIOS_SPEW, "Timing values:\n" |
| 564 | " tCLK: %3u\n" |
| 565 | " tRAS: %3u\n" |
| 566 | " tRP: %3u\n" |
| 567 | " tRCD: %3u\n" |
| 568 | " tRFC: %3u\n" |
| 569 | " tWR: %3u\n" |
| 570 | " tRD: %3u\n" |
| 571 | " tRRD: %3u\n" |
| 572 | " tFAW: %3u\n" |
| 573 | " tWL: %3u\n", |
| 574 | tCLK, tRASmin, tRPmin, tRCDmin, tRFCmin, tWRmin, tRDmin, tRRDmin, tFAWmin, tWL); |
| 575 | |
| 576 | sysinfo->selected_timings.tRAS = tRASmin; |
| 577 | sysinfo->selected_timings.tRP = tRPmin; |
| 578 | sysinfo->selected_timings.tRCD = tRCDmin; |
| 579 | sysinfo->selected_timings.tRFC = tRFCmin; |
| 580 | sysinfo->selected_timings.tWR = tWRmin; |
| 581 | sysinfo->selected_timings.tRD = tRDmin; |
| 582 | sysinfo->selected_timings.tRRD = tRRDmin; |
| 583 | sysinfo->selected_timings.tFAW = tFAWmin; |
| 584 | sysinfo->selected_timings.tWL = tWL; |
| 585 | } |
| 586 | |
| 587 | static void collect_dimm_config(sysinfo_t *const sysinfo) |
| 588 | { |
| 589 | int i; |
| 590 | spdinfo_t spdinfo; |
| 591 | |
| 592 | spdinfo.dimm_mask = 0; |
| 593 | sysinfo->spd_type = 0; |
| 594 | |
Vladimir Serbinenko | c4d8948 | 2014-06-05 09:14:48 +0200 | [diff] [blame] | 595 | for (i = 0; i < 4; i++) |
| 596 | if (sysinfo->spd_map[i]) { |
| 597 | const u8 spd = smbus_read_byte(sysinfo->spd_map[i], 2); |
| 598 | printk (BIOS_DEBUG, "%x:%x:%x\n", |
| 599 | i, sysinfo->spd_map[i], |
| 600 | spd); |
| 601 | if ((spd == 7) || (spd == 8) || (spd == 0xb)) { |
| 602 | spdinfo.dimm_mask |= 1 << i; |
| 603 | if (sysinfo->spd_type && sysinfo->spd_type != spd) { |
| 604 | die("Multiple types of DIMM installed in the system, don't do that!\n"); |
| 605 | } |
| 606 | sysinfo->spd_type = spd; |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 607 | } |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 608 | } |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 609 | if (spdinfo.dimm_mask == 0) { |
| 610 | die("Could not find any DIMM.\n"); |
| 611 | } |
| 612 | |
| 613 | /* Normalize spd_type to 1, 2, 3. */ |
| 614 | sysinfo->spd_type = (sysinfo->spd_type & 1) | ((sysinfo->spd_type & 8) >> 2); |
| 615 | printk(BIOS_SPEW, "DDR mask %x, DDR %d\n", spdinfo.dimm_mask, sysinfo->spd_type); |
| 616 | |
| 617 | if (sysinfo->spd_type == DDR2) { |
| 618 | die("DDR2 not supported at this time.\n"); |
| 619 | } else if (sysinfo->spd_type == DDR3) { |
Vladimir Serbinenko | c4d8948 | 2014-06-05 09:14:48 +0200 | [diff] [blame] | 620 | verify_ddr3(sysinfo, spdinfo.dimm_mask); |
| 621 | collect_ddr3(sysinfo, &spdinfo); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 622 | } else { |
| 623 | die("Will never support DDR1.\n"); |
| 624 | } |
| 625 | |
| 626 | for (i = 0; i < 2; i++) { |
| 627 | if ((spdinfo.dimm_mask >> (i*2)) & 1) { |
| 628 | printk(BIOS_SPEW, "Bank %d populated:\n" |
| 629 | " Raw card type: %4c\n" |
| 630 | " Row addr bits: %4u\n" |
| 631 | " Col addr bits: %4u\n" |
| 632 | " byte width: %4u\n" |
| 633 | " page size: %4u\n" |
| 634 | " banks: %4u\n" |
| 635 | " ranks: %4u\n" |
| 636 | " tAAmin: %3u\n" |
| 637 | " tCKmin: %3u\n" |
| 638 | " Max clock: %3u MHz\n" |
| 639 | " CAS: 0x%04x\n", |
| 640 | i, spdinfo.channel[i].raw_card + 'A', |
| 641 | spdinfo.channel[i].rows, spdinfo.channel[i].cols, |
| 642 | spdinfo.channel[i].width, spdinfo.channel[i].page_size, |
| 643 | spdinfo.channel[i].banks, spdinfo.channel[i].ranks, |
| 644 | spdinfo.channel[i].tAAmin, spdinfo.channel[i].tCKmin, |
| 645 | 8000 / spdinfo.channel[i].tCKmin, spdinfo.channel[i].cas_latencies); |
| 646 | } |
| 647 | } |
| 648 | |
| 649 | FOR_EACH_CHANNEL(i) { |
| 650 | sysinfo->dimms[i].card_type = |
| 651 | (spdinfo.dimm_mask & (1 << (i * 2))) ? spdinfo.channel[i].raw_card + 0xa : 0; |
| 652 | } |
| 653 | |
| 654 | /* Find common memory clock and CAS. */ |
| 655 | const unsigned int tCLK = find_common_clock_cas(sysinfo, &spdinfo); |
| 656 | |
| 657 | /* Calculate other timings from clock and CAS. */ |
| 658 | calculate_derived_timings(sysinfo, tCLK, &spdinfo); |
| 659 | |
| 660 | /* Initialize DIMM infos. */ |
| 661 | /* Always prefer interleaved over async channel mode. */ |
| 662 | FOR_EACH_CHANNEL(i) { |
| 663 | IF_CHANNEL_POPULATED(sysinfo->dimms, i) { |
| 664 | sysinfo->dimms[i].banks = spdinfo.channel[i].banks; |
| 665 | sysinfo->dimms[i].ranks = spdinfo.channel[i].ranks; |
| 666 | |
| 667 | /* .width is 1 for x8 or 2 for x16, bus width is 8 bytes. */ |
| 668 | const unsigned int chips_per_rank = 8 / spdinfo.channel[i].width; |
| 669 | |
| 670 | sysinfo->dimms[i].chip_width = spdinfo.channel[i].width; |
| 671 | sysinfo->dimms[i].chip_capacity = spdinfo.channel[i].chip_capacity; |
| 672 | sysinfo->dimms[i].page_size = spdinfo.channel[i].page_size * chips_per_rank; |
| 673 | sysinfo->dimms[i].rank_capacity_mb = |
| 674 | /* offset of chip_capacity is 8 (256M), therefore, add 8 |
| 675 | chip_capacity is in Mbit, we want MByte, therefore, subtract 3 */ |
| 676 | (1 << (spdinfo.channel[i].chip_capacity + 8 - 3)) * chips_per_rank; |
| 677 | } |
| 678 | } |
| 679 | if (CHANNEL_IS_POPULATED(sysinfo->dimms, 0) && |
| 680 | CHANNEL_IS_POPULATED(sysinfo->dimms, 1)) |
| 681 | sysinfo->selected_timings.channel_mode = CHANNEL_MODE_DUAL_INTERLEAVED; |
| 682 | else |
| 683 | sysinfo->selected_timings.channel_mode = CHANNEL_MODE_SINGLE; |
| 684 | } |
| 685 | |
| 686 | static void reset_on_bad_warmboot(void) |
| 687 | { |
| 688 | /* Check self refresh channel status. */ |
| 689 | const u32 reg = MCHBAR32(PMSTS_MCHBAR); |
| 690 | /* Clear status bits. R/WC */ |
| 691 | MCHBAR32(PMSTS_MCHBAR) = reg; |
| 692 | if ((reg & PMSTS_WARM_RESET) && !(reg & PMSTS_BOTH_SELFREFRESH)) { |
| 693 | printk(BIOS_INFO, "DRAM was not in self refresh " |
| 694 | "during warm boot, reset required.\n"); |
| 695 | gm45_early_reset(); |
| 696 | } |
| 697 | } |
| 698 | |
| 699 | static void set_system_memory_frequency(const timings_t *const timings) |
| 700 | { |
| 701 | MCHBAR16(CLKCFG_MCHBAR + 0x60) &= ~(1 << 15); |
| 702 | MCHBAR16(CLKCFG_MCHBAR + 0x48) &= ~(1 << 15); |
| 703 | |
| 704 | /* Calculate wanted frequency setting. */ |
| 705 | const int want_freq = 6 - timings->mem_clock; |
| 706 | |
| 707 | /* Read current memory frequency. */ |
| 708 | const u32 clkcfg = MCHBAR32(CLKCFG_MCHBAR); |
| 709 | int cur_freq = (clkcfg & CLKCFG_MEMCLK_MASK) >> CLKCFG_MEMCLK_SHIFT; |
| 710 | if (0 == cur_freq) { |
| 711 | /* Try memory frequency from scratchpad. */ |
| 712 | printk(BIOS_DEBUG, "Reading current memory frequency from scratchpad.\n"); |
| 713 | cur_freq = (MCHBAR16(SSKPD_MCHBAR) & SSKPD_CLK_MASK) >> SSKPD_CLK_SHIFT; |
| 714 | } |
| 715 | |
| 716 | if (cur_freq != want_freq) { |
| 717 | printk(BIOS_DEBUG, "Changing memory frequency: old %x, new %x.\n", cur_freq, want_freq); |
| 718 | /* When writing new frequency setting, reset, then set update bit. */ |
| 719 | MCHBAR32(CLKCFG_MCHBAR) = (MCHBAR32(CLKCFG_MCHBAR) & ~(CLKCFG_UPDATE | CLKCFG_MEMCLK_MASK)) | |
| 720 | (want_freq << CLKCFG_MEMCLK_SHIFT); |
| 721 | MCHBAR32(CLKCFG_MCHBAR) = (MCHBAR32(CLKCFG_MCHBAR) & ~CLKCFG_MEMCLK_MASK) | |
| 722 | (want_freq << CLKCFG_MEMCLK_SHIFT) | CLKCFG_UPDATE; |
| 723 | /* Reset update bit. */ |
| 724 | MCHBAR32(CLKCFG_MCHBAR) &= ~CLKCFG_UPDATE; |
| 725 | } |
| 726 | |
| 727 | if ((timings->fsb_clock == FSB_CLOCK_1067MHz) && (timings->mem_clock == MEM_CLOCK_667MT)) { |
| 728 | MCHBAR32(CLKCFG_MCHBAR + 0x16) = 0x000030f0; |
| 729 | MCHBAR32(CLKCFG_MCHBAR + 0x64) = 0x000050c1; |
| 730 | |
| 731 | MCHBAR32(CLKCFG_MCHBAR) = (MCHBAR32(CLKCFG_MCHBAR) & ~(1 << 12)) | (1 << 17); |
| 732 | MCHBAR32(CLKCFG_MCHBAR) |= (1 << 17) | (1 << 12); |
| 733 | MCHBAR32(CLKCFG_MCHBAR) &= ~(1 << 12); |
| 734 | |
| 735 | MCHBAR32(CLKCFG_MCHBAR + 0x04) = 0x9bad1f1f; |
| 736 | MCHBAR8(CLKCFG_MCHBAR + 0x08) = 0xf4; |
| 737 | MCHBAR8(CLKCFG_MCHBAR + 0x0a) = 0x43; |
| 738 | MCHBAR8(CLKCFG_MCHBAR + 0x0c) = 0x10; |
| 739 | MCHBAR8(CLKCFG_MCHBAR + 0x0d) = 0x80; |
| 740 | MCHBAR32(CLKCFG_MCHBAR + 0x50) = 0x0b0e151b; |
| 741 | MCHBAR8(CLKCFG_MCHBAR + 0x54) = 0xb4; |
| 742 | MCHBAR8(CLKCFG_MCHBAR + 0x55) = 0x10; |
| 743 | MCHBAR8(CLKCFG_MCHBAR + 0x56) = 0x08; |
| 744 | |
| 745 | MCHBAR32(CLKCFG_MCHBAR) |= (1 << 10); |
| 746 | MCHBAR32(CLKCFG_MCHBAR) |= (1 << 11); |
| 747 | MCHBAR32(CLKCFG_MCHBAR) &= ~(1 << 10); |
| 748 | MCHBAR32(CLKCFG_MCHBAR) &= ~(1 << 11); |
| 749 | } |
| 750 | |
| 751 | MCHBAR32(CLKCFG_MCHBAR + 0x48) |= 0x3f << 24; |
| 752 | } |
| 753 | |
| 754 | int raminit_read_vco_index(void) |
| 755 | { |
| 756 | switch (MCHBAR8(0x0c0f) & 0x7) { |
| 757 | case VCO_2666: |
| 758 | return 0; |
| 759 | case VCO_3200: |
| 760 | return 1; |
| 761 | case VCO_4000: |
| 762 | return 2; |
| 763 | case VCO_5333: |
| 764 | return 3; |
| 765 | default: |
| 766 | die("Unknown VCO frequency.\n"); |
| 767 | return 0; |
| 768 | } |
| 769 | } |
| 770 | static void set_igd_memory_frequencies(const sysinfo_t *const sysinfo) |
| 771 | { |
| 772 | const int gfx_idx = ((sysinfo->gfx_type == GMCH_GS45) && |
| 773 | !sysinfo->gs45_low_power_mode) |
| 774 | ? (GMCH_GS45 + 1) : sysinfo->gfx_type; |
| 775 | |
| 776 | /* Render and sampler frequency values seem to be some kind of factor. */ |
| 777 | const u16 render_freq_from_vco_and_gfxtype[][10] = { |
| 778 | /* GM45 GM47 GM49 GE45 GL40 GL43 GS40 GS45 (perf) */ |
| 779 | /* VCO 2666 */ { 0xd, 0xd, 0xe, 0xd, 0xb, 0xd, 0xb, 0xa, 0xd }, |
| 780 | /* VCO 3200 */ { 0xd, 0xe, 0xf, 0xd, 0xb, 0xd, 0xb, 0x9, 0xd }, |
| 781 | /* VCO 4000 */ { 0xc, 0xd, 0xf, 0xc, 0xa, 0xc, 0xa, 0x9, 0xc }, |
| 782 | /* VCO 5333 */ { 0xb, 0xc, 0xe, 0xb, 0x9, 0xb, 0x9, 0x8, 0xb }, |
| 783 | }; |
| 784 | const u16 sampler_freq_from_vco_and_gfxtype[][10] = { |
| 785 | /* GM45 GM47 GM49 GE45 GL40 GL43 GS40 GS45 (perf) */ |
| 786 | /* VCO 2666 */ { 0xc, 0xc, 0xd, 0xc, 0x9, 0xc, 0x9, 0x8, 0xc }, |
| 787 | /* VCO 3200 */ { 0xc, 0xd, 0xe, 0xc, 0x9, 0xc, 0x9, 0x8, 0xc }, |
| 788 | /* VCO 4000 */ { 0xa, 0xc, 0xd, 0xa, 0x8, 0xa, 0x8, 0x8, 0xa }, |
| 789 | /* VCO 5333 */ { 0xa, 0xa, 0xc, 0xa, 0x7, 0xa, 0x7, 0x6, 0xa }, |
| 790 | }; |
| 791 | const u16 display_clock_select_from_gfxtype[] = { |
| 792 | /* GM45 GM47 GM49 GE45 GL40 GL43 GS40 GS45 (perf) */ |
| 793 | 1, 1, 1, 1, 1, 1, 1, 0, 1 |
| 794 | }; |
| 795 | |
| 796 | if (pci_read_config16(GCFGC_PCIDEV, 0) != 0x8086) { |
| 797 | printk(BIOS_DEBUG, "Skipping IGD memory frequency setting.\n"); |
| 798 | return; |
| 799 | } |
| 800 | |
| 801 | MCHBAR16(0x119e) = 0xa800; |
| 802 | MCHBAR16(0x11c0) = (MCHBAR16(0x11c0) & ~0xff00) | (0x01 << 8); |
| 803 | MCHBAR16(0x119e) = 0xb800; |
| 804 | MCHBAR8(0x0f10) |= 1 << 7; |
| 805 | |
| 806 | /* Read VCO. */ |
| 807 | const int vco_idx = raminit_read_vco_index(); |
| 808 | printk(BIOS_DEBUG, "Setting IGD memory frequencies for VCO #%d.\n", vco_idx); |
| 809 | |
| 810 | const u32 freqcfg = |
| 811 | ((render_freq_from_vco_and_gfxtype[vco_idx][gfx_idx] |
| 812 | << GCFGC_CR_SHIFT) & GCFGC_CR_MASK) | |
| 813 | ((sampler_freq_from_vco_and_gfxtype[vco_idx][gfx_idx] |
| 814 | << GCFGC_CS_SHIFT) & GCFGC_CS_MASK); |
| 815 | |
| 816 | /* Set frequencies, clear update bit. */ |
| 817 | u32 gcfgc = pci_read_config16(GCFGC_PCIDEV, GCFGC_OFFSET); |
| 818 | gcfgc &= ~(GCFGC_CS_MASK | GCFGC_UPDATE | GCFGC_CR_MASK); |
| 819 | gcfgc |= freqcfg; |
| 820 | pci_write_config16(GCFGC_PCIDEV, GCFGC_OFFSET, gcfgc); |
| 821 | |
| 822 | /* Set frequencies, set update bit. */ |
| 823 | gcfgc = pci_read_config16(GCFGC_PCIDEV, GCFGC_OFFSET); |
| 824 | gcfgc &= ~(GCFGC_CS_MASK | GCFGC_CR_MASK); |
| 825 | gcfgc |= freqcfg | GCFGC_UPDATE; |
| 826 | pci_write_config16(GCFGC_PCIDEV, GCFGC_OFFSET, gcfgc); |
| 827 | |
| 828 | /* Clear update bit. */ |
| 829 | pci_write_config16(GCFGC_PCIDEV, GCFGC_OFFSET, |
| 830 | pci_read_config16(GCFGC_PCIDEV, GCFGC_OFFSET) & ~GCFGC_UPDATE); |
| 831 | |
| 832 | /* Set display clock select bit. */ |
| 833 | pci_write_config16(GCFGC_PCIDEV, GCFGC_OFFSET, |
| 834 | (pci_read_config16(GCFGC_PCIDEV, GCFGC_OFFSET) & ~GCFGC_CD_MASK) | |
| 835 | (display_clock_select_from_gfxtype[gfx_idx] << GCFGC_CD_SHIFT)); |
| 836 | } |
| 837 | |
| 838 | static void configure_dram_control_mode(const timings_t *const timings, const dimminfo_t *const dimms) |
| 839 | { |
| 840 | int ch, r; |
| 841 | |
| 842 | FOR_EACH_CHANNEL(ch) { |
| 843 | unsigned int mchbar = CxDRC0_MCHBAR(ch); |
| 844 | u32 cxdrc = MCHBAR32(mchbar); |
| 845 | cxdrc &= ~CxDRC0_RANKEN_MASK; |
| 846 | FOR_EACH_POPULATED_RANK_IN_CHANNEL(dimms, ch, r) |
| 847 | cxdrc |= CxDRC0_RANKEN(r); |
| 848 | cxdrc = (cxdrc & ~CxDRC0_RMS_MASK) | |
| 849 | /* Always 7.8us for DDR3: */ |
| 850 | CxDRC0_RMS_78US; |
| 851 | MCHBAR32(mchbar) = cxdrc; |
| 852 | |
| 853 | mchbar = CxDRC1_MCHBAR(ch); |
| 854 | cxdrc = MCHBAR32(mchbar); |
| 855 | cxdrc |= CxDRC1_NOTPOP_MASK; |
| 856 | FOR_EACH_POPULATED_RANK_IN_CHANNEL(dimms, ch, r) |
| 857 | cxdrc &= ~CxDRC1_NOTPOP(r); |
| 858 | cxdrc |= CxDRC1_MUSTWR; |
| 859 | MCHBAR32(mchbar) = cxdrc; |
| 860 | |
| 861 | mchbar = CxDRC2_MCHBAR(ch); |
| 862 | cxdrc = MCHBAR32(mchbar); |
| 863 | cxdrc |= CxDRC2_NOTPOP_MASK; |
| 864 | FOR_EACH_POPULATED_RANK_IN_CHANNEL(dimms, ch, r) |
| 865 | cxdrc &= ~CxDRC2_NOTPOP(r); |
| 866 | cxdrc |= CxDRC2_MUSTWR; |
| 867 | if (timings->mem_clock == MEM_CLOCK_1067MT) |
| 868 | cxdrc |= CxDRC2_CLK1067MT; |
| 869 | MCHBAR32(mchbar) = cxdrc; |
| 870 | } |
| 871 | } |
| 872 | |
| 873 | static void rcomp_initialization(const stepping_t stepping, const int sff) |
| 874 | { |
| 875 | /* Programm RCOMP codes. */ |
| 876 | if (sff) |
| 877 | die("SFF platform unsupported in RCOMP initialization.\n"); |
| 878 | /* Values are for DDR3. */ |
| 879 | MCHBAR8(0x6ac) &= ~0x0f; |
| 880 | MCHBAR8(0x6b0) = 0x55; |
| 881 | MCHBAR8(0x6ec) &= ~0x0f; |
| 882 | MCHBAR8(0x6f0) = 0x66; |
| 883 | MCHBAR8(0x72c) &= ~0x0f; |
| 884 | MCHBAR8(0x730) = 0x66; |
| 885 | MCHBAR8(0x76c) &= ~0x0f; |
| 886 | MCHBAR8(0x770) = 0x66; |
| 887 | MCHBAR8(0x7ac) &= ~0x0f; |
| 888 | MCHBAR8(0x7b0) = 0x66; |
| 889 | MCHBAR8(0x7ec) &= ~0x0f; |
| 890 | MCHBAR8(0x7f0) = 0x66; |
| 891 | MCHBAR8(0x86c) &= ~0x0f; |
| 892 | MCHBAR8(0x870) = 0x55; |
| 893 | MCHBAR8(0x8ac) &= ~0x0f; |
| 894 | MCHBAR8(0x8b0) = 0x66; |
| 895 | /* ODT multiplier bits. */ |
| 896 | MCHBAR32(0x04d0) = (MCHBAR32(0x04d0) & ~((7 << 3) | (7 << 0))) | (2 << 3) | (2 << 0); |
| 897 | |
| 898 | /* Perform RCOMP calibration for DDR3. */ |
| 899 | raminit_rcomp_calibration(stepping); |
| 900 | |
| 901 | /* Run initial RCOMP. */ |
| 902 | MCHBAR32(0x418) |= 1 << 17; |
| 903 | MCHBAR32(0x40c) &= ~(1 << 23); |
| 904 | MCHBAR32(0x41c) &= ~((1 << 7) | (1 << 3)); |
| 905 | MCHBAR32(0x400) |= 1; |
| 906 | while (MCHBAR32(0x400) & 1) {} |
| 907 | |
| 908 | /* Run second RCOMP. */ |
| 909 | MCHBAR32(0x40c) |= 1 << 19; |
| 910 | MCHBAR32(0x400) |= 1; |
| 911 | while (MCHBAR32(0x400) & 1) {} |
| 912 | |
| 913 | /* Cleanup and start periodic RCOMP. */ |
| 914 | MCHBAR32(0x40c) &= ~(1 << 19); |
| 915 | MCHBAR32(0x40c) |= 1 << 23; |
| 916 | MCHBAR32(0x418) &= ~(1 << 17); |
| 917 | MCHBAR32(0x41c) |= (1 << 7) | (1 << 3); |
| 918 | MCHBAR32(0x400) |= (1 << 1); |
| 919 | } |
| 920 | |
| 921 | static void dram_powerup(const int resume) |
| 922 | { |
| 923 | udelay_from_reset(200); |
| 924 | MCHBAR32(CLKCFG_MCHBAR) = (MCHBAR32(CLKCFG_MCHBAR) & ~(1 << 3)) | (3 << 21); |
| 925 | if (!resume) { |
| 926 | MCHBAR32(0x1434) |= (1 << 10); |
| 927 | ns100delay(2); |
| 928 | } |
| 929 | MCHBAR32(0x1434) |= (1 << 6); |
| 930 | if (!resume) { |
| 931 | ns100delay(1); |
| 932 | MCHBAR32(0x1434) |= (1 << 9); |
| 933 | MCHBAR32(0x1434) &= ~(1 << 10); |
| 934 | udelay(500); |
| 935 | } |
| 936 | } |
| 937 | static void dram_program_timings(const timings_t *const timings) |
| 938 | { |
| 939 | /* Values are for DDR3. */ |
| 940 | const int burst_length = 8; |
| 941 | const int tWTR = 4, tRTP = 1; |
| 942 | int i; |
| 943 | |
| 944 | FOR_EACH_CHANNEL(i) { |
| 945 | u32 reg = MCHBAR32(CxDRT0_MCHBAR(i)); |
| 946 | const int btb_wtp = timings->tWL + burst_length/2 + timings->tWR; |
| 947 | const int btb_wtr = timings->tWL + burst_length/2 + tWTR; |
| 948 | reg = (reg & ~(CxDRT0_BtB_WtP_MASK | CxDRT0_BtB_WtR_MASK)) | |
| 949 | ((btb_wtp << CxDRT0_BtB_WtP_SHIFT) & CxDRT0_BtB_WtP_MASK) | |
| 950 | ((btb_wtr << CxDRT0_BtB_WtR_SHIFT) & CxDRT0_BtB_WtR_MASK); |
| 951 | if (timings->mem_clock != MEM_CLOCK_1067MT) { |
| 952 | reg = (reg & ~(0x7 << 15)) | ((9 - timings->CAS) << 15); |
| 953 | reg = (reg & ~(0xf << 10)) | ((timings->CAS - 3) << 10); |
| 954 | } else { |
| 955 | reg = (reg & ~(0x7 << 15)) | ((10 - timings->CAS) << 15); |
| 956 | reg = (reg & ~(0xf << 10)) | ((timings->CAS - 4) << 10); |
| 957 | } |
| 958 | reg = (reg & ~(0x7 << 5)) | (3 << 5); |
| 959 | reg = (reg & ~(0x7 << 0)) | (1 << 0); |
| 960 | MCHBAR32(CxDRT0_MCHBAR(i)) = reg; |
| 961 | |
| 962 | reg = MCHBAR32(CxDRT1_MCHBAR(i)); |
| 963 | reg = (reg & ~(0x03 << 28)) | ((tRTP & 0x03) << 28); |
| 964 | reg = (reg & ~(0x1f << 21)) | ((timings->tRAS & 0x1f) << 21); |
| 965 | reg = (reg & ~(0x07 << 10)) | (((timings->tRRD - 2) & 0x07) << 10); |
| 966 | reg = (reg & ~(0x07 << 5)) | (((timings->tRCD - 2) & 0x07) << 5); |
| 967 | reg = (reg & ~(0x07 << 0)) | (((timings->tRP - 2) & 0x07) << 0); |
| 968 | MCHBAR32(CxDRT1_MCHBAR(i)) = reg; |
| 969 | |
| 970 | reg = MCHBAR32(CxDRT2_MCHBAR(i)); |
| 971 | reg = (reg & ~(0x1f << 17)) | ((timings->tFAW & 0x1f) << 17); |
| 972 | if (timings->mem_clock != MEM_CLOCK_1067MT) { |
| 973 | reg = (reg & ~(0x7 << 12)) | (0x2 << 12); |
| 974 | reg = (reg & ~(0xf << 6)) | (0x9 << 6); |
| 975 | } else { |
| 976 | reg = (reg & ~(0x7 << 12)) | (0x3 << 12); |
| 977 | reg = (reg & ~(0xf << 6)) | (0xc << 6); |
| 978 | } |
| 979 | reg = (reg & ~(0x1f << 0)) | (0x13 << 0); |
| 980 | MCHBAR32(CxDRT2_MCHBAR(i)) = reg; |
| 981 | |
| 982 | reg = MCHBAR32(CxDRT3_MCHBAR(i)); |
| 983 | reg |= 0x3 << 28; |
| 984 | reg = (reg & ~(0x03 << 26)); |
| 985 | reg = (reg & ~(0x07 << 23)) | (((timings->CAS - 3) & 0x07) << 23); |
| 986 | reg = (reg & ~(0xff << 13)) | ((timings->tRFC & 0xff) << 13); |
| 987 | reg = (reg & ~(0x07 << 0)) | (((timings->tWL - 2) & 0x07) << 0); |
| 988 | MCHBAR32(CxDRT3_MCHBAR(i)) = reg; |
| 989 | |
| 990 | reg = MCHBAR32(CxDRT4_MCHBAR(i)); |
| 991 | static const u8 timings_by_clock[4][3] = { |
| 992 | /* 333MHz 400MHz 533MHz |
| 993 | 667MT 800MT 1067MT */ |
| 994 | { 0x07, 0x0a, 0x0d }, |
| 995 | { 0x3a, 0x46, 0x5d }, |
| 996 | { 0x0c, 0x0e, 0x18 }, |
| 997 | { 0x21, 0x28, 0x35 }, |
| 998 | }; |
| 999 | const int clk_idx = 2 - timings->mem_clock; |
| 1000 | reg = (reg & ~(0x01f << 27)) | (timings_by_clock[0][clk_idx] << 27); |
| 1001 | reg = (reg & ~(0x3ff << 17)) | (timings_by_clock[1][clk_idx] << 17); |
| 1002 | reg = (reg & ~(0x03f << 10)) | (timings_by_clock[2][clk_idx] << 10); |
| 1003 | reg = (reg & ~(0x1ff << 0)) | (timings_by_clock[3][clk_idx] << 0); |
| 1004 | MCHBAR32(CxDRT4_MCHBAR(i)) = reg; |
| 1005 | |
| 1006 | reg = MCHBAR32(CxDRT5_MCHBAR(i)); |
| 1007 | if (timings->mem_clock == MEM_CLOCK_1067MT) |
| 1008 | reg = (reg & ~(0xf << 28)) | (0x8 << 28); |
| 1009 | reg = (reg & ~(0x00f << 22)) | ((burst_length/2 + timings->CAS + 2) << 22); |
| 1010 | reg = (reg & ~(0x3ff << 12)) | (0x190 << 12); |
| 1011 | reg = (reg & ~(0x00f << 4)) | ((timings->CAS - 2) << 4); |
| 1012 | reg = (reg & ~(0x003 << 2)) | (0x001 << 2); |
| 1013 | reg = (reg & ~(0x003 << 0)); |
| 1014 | MCHBAR32(CxDRT5_MCHBAR(i)) = reg; |
| 1015 | |
| 1016 | reg = MCHBAR32(CxDRT6_MCHBAR(i)); |
| 1017 | reg = (reg & ~(0xffff << 16)) | (0x066a << 16); /* always 7.8us refresh rate for DDR3 */ |
| 1018 | reg |= (1 << 2); |
| 1019 | MCHBAR32(CxDRT6_MCHBAR(i)) = reg; |
| 1020 | } |
| 1021 | } |
| 1022 | |
| 1023 | static void dram_program_banks(const dimminfo_t *const dimms) |
| 1024 | { |
| 1025 | int ch, r; |
| 1026 | |
| 1027 | FOR_EACH_CHANNEL(ch) { |
| 1028 | const int tRPALL = dimms[ch].banks == 8; |
| 1029 | |
| 1030 | u32 reg = MCHBAR32(CxDRT1_MCHBAR(ch)) & ~(0x01 << 15); |
| 1031 | IF_CHANNEL_POPULATED(dimms, ch) |
| 1032 | reg |= tRPALL << 15; |
| 1033 | MCHBAR32(CxDRT1_MCHBAR(ch)) = reg; |
| 1034 | |
| 1035 | reg = MCHBAR32(CxDRA_MCHBAR(ch)) & ~CxDRA_BANKS_MASK; |
| 1036 | FOR_EACH_POPULATED_RANK_IN_CHANNEL(dimms, ch, r) { |
| 1037 | reg |= CxDRA_BANKS(r, dimms[ch].banks); |
| 1038 | } |
| 1039 | MCHBAR32(CxDRA_MCHBAR(ch)) = reg; |
| 1040 | } |
| 1041 | } |
| 1042 | |
| 1043 | static void odt_setup(const timings_t *const timings, const int sff) |
| 1044 | { |
| 1045 | /* Values are for DDR3. */ |
| 1046 | int ch; |
| 1047 | |
| 1048 | FOR_EACH_CHANNEL(ch) { |
| 1049 | u32 reg = MCHBAR32(CxODT_HIGH(ch)); |
| 1050 | if (sff && (timings->mem_clock != MEM_CLOCK_1067MT)) |
| 1051 | reg &= ~(0x3 << (61 - 32)); |
| 1052 | else |
| 1053 | reg |= 0x3 << (61 - 32); |
| 1054 | reg = (reg & ~(0x3 << (52 - 32))) | (0x2 << (52 - 32)); |
| 1055 | reg = (reg & ~(0x7 << (48 - 32))) | ((timings->CAS - 3) << (48 - 32)); |
| 1056 | reg = (reg & ~(0xf << (44 - 32))) | (0x7 << (44 - 32)); |
| 1057 | if (timings->mem_clock != MEM_CLOCK_1067MT) { |
| 1058 | reg = (reg & ~(0xf << (40 - 32))) | ((12 - timings->CAS) << (40 - 32)); |
| 1059 | reg = (reg & ~(0xf << (36 - 32))) | (( 2 + timings->CAS) << (36 - 32)); |
| 1060 | } else { |
| 1061 | reg = (reg & ~(0xf << (40 - 32))) | ((13 - timings->CAS) << (40 - 32)); |
| 1062 | reg = (reg & ~(0xf << (36 - 32))) | (( 1 + timings->CAS) << (36 - 32)); |
| 1063 | } |
| 1064 | reg = (reg & ~(0xf << (32 - 32))) | (0x7 << (32 - 32)); |
| 1065 | MCHBAR32(CxODT_HIGH(ch)) = reg; |
| 1066 | |
| 1067 | reg = MCHBAR32(CxODT_LOW(ch)); |
| 1068 | reg = (reg & ~(0x7 << 28)) | (0x2 << 28); |
| 1069 | reg = (reg & ~(0x3 << 22)) | (0x2 << 22); |
| 1070 | reg = (reg & ~(0x7 << 12)) | (0x2 << 12); |
| 1071 | reg = (reg & ~(0x7 << 4)) | (0x2 << 4); |
| 1072 | switch (timings->mem_clock) { |
| 1073 | case MEM_CLOCK_667MT: |
| 1074 | reg = (reg & ~0x7); |
| 1075 | break; |
| 1076 | case MEM_CLOCK_800MT: |
| 1077 | reg = (reg & ~0x7) | 0x2; |
| 1078 | break; |
| 1079 | case MEM_CLOCK_1067MT: |
| 1080 | reg = (reg & ~0x7) | 0x5; |
| 1081 | break; |
| 1082 | } |
| 1083 | MCHBAR32(CxODT_LOW(ch)) = reg; |
| 1084 | } |
| 1085 | } |
| 1086 | |
| 1087 | static void misc_settings(const timings_t *const timings, |
| 1088 | const stepping_t stepping) |
| 1089 | { |
| 1090 | MCHBAR32(0x1260) = (MCHBAR32(0x1260) & ~((1 << 24) | 0x1f)) | timings->tRD; |
| 1091 | MCHBAR32(0x1360) = (MCHBAR32(0x1360) & ~((1 << 24) | 0x1f)) | timings->tRD; |
| 1092 | |
| 1093 | MCHBAR8(0x1268) = (MCHBAR8(0x1268) & ~(0xf)) | timings->tWL; |
| 1094 | MCHBAR8(0x1368) = (MCHBAR8(0x1368) & ~(0xf)) | timings->tWL; |
| 1095 | MCHBAR8(0x12a0) = (MCHBAR8(0x12a0) & ~(0xf)) | 0xa; |
| 1096 | MCHBAR8(0x13a0) = (MCHBAR8(0x13a0) & ~(0xf)) | 0xa; |
| 1097 | |
| 1098 | MCHBAR32(0x218) = (MCHBAR32(0x218) & ~((7 << 29) | (7 << 25) | (3 << 22) | (3 << 10))) | |
| 1099 | (4 << 29) | (3 << 25) | (0 << 22) | (1 << 10); |
| 1100 | MCHBAR32(0x220) = (MCHBAR32(0x220) & ~(7 << 16)) | (1 << 21) | (1 << 16); |
| 1101 | MCHBAR32(0x224) = (MCHBAR32(0x224) & ~(7 << 8)) | (3 << 8); |
| 1102 | if (stepping >= STEPPING_B1) |
| 1103 | MCHBAR8(0x234) |= (1 << 3); |
| 1104 | } |
| 1105 | |
| 1106 | static void clock_crossing_setup(const fsb_clock_t fsb, |
| 1107 | const mem_clock_t ddr3clock, |
| 1108 | const dimminfo_t *const dimms) |
| 1109 | { |
| 1110 | int ch; |
| 1111 | |
| 1112 | static const u32 values_from_fsb_and_mem[][3][4] = { |
| 1113 | /* FSB 1067MHz */{ |
| 1114 | /* DDR3-1067 */ { 0x00000000, 0x00000000, 0x00180006, 0x00810060 }, |
| 1115 | /* DDR3-800 */ { 0x00000000, 0x00000000, 0x0000001c, 0x000300e0 }, |
| 1116 | /* DDR3-667 */ { 0x00000000, 0x00001c00, 0x03c00038, 0x0007e000 }, |
| 1117 | }, |
| 1118 | /* FSB 800MHz */{ |
| 1119 | /* DDR3-1067 */ { 0, 0, 0, 0 }, |
| 1120 | /* DDR3-800 */ { 0x00000000, 0x00000000, 0x0030000c, 0x000300c0 }, |
| 1121 | /* DDR3-667 */ { 0x00000000, 0x00000380, 0x0060001c, 0x00030c00 }, |
| 1122 | }, |
| 1123 | /* FSB 667MHz */{ |
| 1124 | /* DDR3-1067 */ { 0, 0, 0, 0 }, |
| 1125 | /* DDR3-800 */ { 0, 0, 0, 0 }, |
| 1126 | /* DDR3-667 */ { 0x00000000, 0x00000000, 0x0030000c, 0x000300c0 }, |
| 1127 | }, |
| 1128 | }; |
| 1129 | |
| 1130 | const u32 *data = values_from_fsb_and_mem[fsb][ddr3clock]; |
| 1131 | MCHBAR32(0x0208) = data[3]; |
| 1132 | MCHBAR32(0x020c) = data[2]; |
| 1133 | if (((fsb == FSB_CLOCK_1067MHz) || (fsb == FSB_CLOCK_800MHz)) && (ddr3clock == MEM_CLOCK_667MT)) |
| 1134 | MCHBAR32(0x0210) = data[1]; |
| 1135 | |
| 1136 | static const u32 from_fsb_and_mem[][3] = { |
| 1137 | /* DDR3-1067 DDR3-800 DDR3-667 */ |
| 1138 | /* FSB 1067MHz */{ 0x40100401, 0x10040220, 0x08040110, }, |
| 1139 | /* FSB 800MHz */{ 0x00000000, 0x40100401, 0x00080201, }, |
| 1140 | /* FSB 667MHz */{ 0x00000000, 0x00000000, 0x40100401, }, |
| 1141 | }; |
| 1142 | FOR_EACH_CHANNEL(ch) { |
| 1143 | const unsigned int mchbar = 0x1258 + (ch * 0x0100); |
| 1144 | if ((fsb == FSB_CLOCK_1067MHz) && (ddr3clock == MEM_CLOCK_800MT) && CHANNEL_IS_CARDF(dimms, ch)) |
| 1145 | MCHBAR32(mchbar) = 0x08040120; |
| 1146 | else |
| 1147 | MCHBAR32(mchbar) = from_fsb_and_mem[fsb][ddr3clock]; |
| 1148 | MCHBAR32(mchbar + 4) = 0x00000000; |
| 1149 | } |
| 1150 | } |
| 1151 | |
| 1152 | /* Program egress VC1 timings. */ |
| 1153 | static void vc1_program_timings(const fsb_clock_t fsb) |
| 1154 | { |
| 1155 | const u32 timings_by_fsb[][2] = { |
| 1156 | /* FSB 1067MHz */ { 0x1a, 0x01380138 }, |
| 1157 | /* FSB 800MHz */ { 0x14, 0x00f000f0 }, |
| 1158 | /* FSB 667MHz */ { 0x10, 0x00c000c0 }, |
| 1159 | }; |
| 1160 | EPBAR8(0x2c) = timings_by_fsb[fsb][0]; |
| 1161 | EPBAR32(0x38) = timings_by_fsb[fsb][1]; |
| 1162 | EPBAR32(0x3c) = timings_by_fsb[fsb][1]; |
| 1163 | } |
| 1164 | |
| 1165 | /* @prejedec if not zero, set rank size to 128MB and page size to 4KB. */ |
| 1166 | static void program_memory_map(const dimminfo_t *const dimms, const channel_mode_t mode, const int prejedec) |
| 1167 | { |
| 1168 | int ch, r; |
| 1169 | |
| 1170 | /* Program rank boundaries (CxDRBy). */ |
| 1171 | unsigned int base = 0; /* start of next rank in MB */ |
| 1172 | unsigned int total_mb[2] = { 0, 0 }; /* total memory per channel in MB */ |
| 1173 | FOR_EACH_CHANNEL(ch) { |
| 1174 | if (mode == CHANNEL_MODE_DUAL_INTERLEAVED) |
| 1175 | /* In interleaved mode, start every channel from 0. */ |
| 1176 | base = 0; |
| 1177 | for (r = 0; r < RANKS_PER_CHANNEL; r += 2) { |
| 1178 | /* Fixed capacity for pre-jedec config. */ |
| 1179 | const unsigned int rank_capacity_mb = |
| 1180 | prejedec ? 128 : dimms[ch].rank_capacity_mb; |
| 1181 | u32 reg = 0; |
| 1182 | |
| 1183 | /* Program bounds in CxDRBy. */ |
| 1184 | IF_RANK_POPULATED(dimms, ch, r) { |
| 1185 | base += rank_capacity_mb; |
| 1186 | total_mb[ch] += rank_capacity_mb; |
| 1187 | } |
| 1188 | reg |= CxDRBy_BOUND_MB(r, base); |
| 1189 | IF_RANK_POPULATED(dimms, ch, r+1) { |
| 1190 | base += rank_capacity_mb; |
| 1191 | total_mb[ch] += rank_capacity_mb; |
| 1192 | } |
| 1193 | reg |= CxDRBy_BOUND_MB(r+1, base); |
| 1194 | |
| 1195 | MCHBAR32(CxDRBy_MCHBAR(ch, r)) = reg; |
| 1196 | } |
| 1197 | } |
| 1198 | |
| 1199 | /* Program page size (CxDRA). */ |
| 1200 | FOR_EACH_CHANNEL(ch) { |
| 1201 | u32 reg = MCHBAR32(CxDRA_MCHBAR(ch)) & ~CxDRA_PAGESIZE_MASK; |
| 1202 | FOR_EACH_POPULATED_RANK_IN_CHANNEL(dimms, ch, r) { |
| 1203 | /* Fixed page size for pre-jedec config. */ |
| 1204 | const unsigned int page_size = /* dimm page size in bytes */ |
| 1205 | prejedec ? 4096 : dimms[ch].page_size; |
| 1206 | reg |= CxDRA_PAGESIZE(r, log2(page_size)); |
| 1207 | /* deferred to f5_27: reg |= CxDRA_BANKS(r, dimms[ch].banks); */ |
| 1208 | } |
| 1209 | MCHBAR32(CxDRA_MCHBAR(ch)) = reg; |
| 1210 | } |
| 1211 | |
| 1212 | /* Calculate memory mapping, all values in MB. */ |
| 1213 | const unsigned int MMIOstart = 0x0c00; /* 3GB, makes MTRR configuration small. */ |
Vladimir Serbinenko | 9907be4 | 2014-08-12 21:51:28 +0200 | [diff] [blame] | 1214 | const int me_active = pci_read_config8(PCI_DEV(0, 3, 0), PCI_CLASS_REVISION) != 0xff; |
| 1215 | const unsigned int ME_SIZE = prejedec || !me_active ? 0 : 32; |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1216 | const unsigned int usedMEsize = (total_mb[0] != total_mb[1]) ? ME_SIZE : 2 * ME_SIZE; |
| 1217 | const unsigned int claimCapable = |
| 1218 | !(pci_read_config32(PCI_DEV(0, 0, 0), D0F0_CAPID0 + 4) & (1 << (47 - 32))); |
| 1219 | |
| 1220 | const unsigned int TOM = total_mb[0] + total_mb[1]; |
| 1221 | unsigned int TOMminusME = TOM - usedMEsize; |
| 1222 | unsigned int TOLUD = (TOMminusME < MMIOstart) ? TOMminusME : MMIOstart; |
| 1223 | unsigned int TOUUD = TOMminusME; |
| 1224 | unsigned int REMAPbase = 0xffff, REMAPlimit = 0; |
| 1225 | |
| 1226 | if (claimCapable && (TOMminusME >= (MMIOstart + 64))) { |
| 1227 | /* 64MB alignment: We'll lose some MBs here, if ME is on. */ |
| 1228 | TOMminusME &= ~(64 - 1); |
| 1229 | /* 64MB alignment: Loss will be reclaimed. */ |
| 1230 | TOLUD &= ~(64 - 1); |
| 1231 | if (TOMminusME > 4096) { |
| 1232 | REMAPbase = TOMminusME; |
| 1233 | REMAPlimit = REMAPbase + (4096 - TOLUD); |
| 1234 | } else { |
| 1235 | REMAPbase = 4096; |
| 1236 | REMAPlimit = REMAPbase + (TOMminusME - TOLUD); |
| 1237 | } |
| 1238 | TOUUD = REMAPlimit; |
| 1239 | /* REMAPlimit is an inclusive bound, all others exclusive. */ |
| 1240 | REMAPlimit -= 64; |
| 1241 | } |
| 1242 | |
| 1243 | pci_write_config16(PCI_DEV(0, 0, 0), D0F0_TOM, (TOM >> 7) & 0x1ff); |
| 1244 | pci_write_config16(PCI_DEV(0, 0, 0), D0F0_TOLUD, TOLUD << 4); |
| 1245 | pci_write_config16(PCI_DEV(0, 0, 0), D0F0_TOUUD, TOUUD); |
| 1246 | pci_write_config16(PCI_DEV(0, 0, 0), D0F0_REMAPBASE, (REMAPbase >> 6) & 0x03ff); |
| 1247 | pci_write_config16(PCI_DEV(0, 0, 0), D0F0_REMAPLIMIT, (REMAPlimit >> 6) & 0x03ff); |
| 1248 | |
| 1249 | /* Program channel mode. */ |
| 1250 | switch (mode) { |
| 1251 | case CHANNEL_MODE_SINGLE: |
| 1252 | printk(BIOS_DEBUG, "Memory configured in single-channel mode.\n"); |
| 1253 | MCHBAR32(DCC_MCHBAR) &= ~DCC_INTERLEAVED; |
| 1254 | break; |
| 1255 | case CHANNEL_MODE_DUAL_ASYNC: |
| 1256 | printk(BIOS_DEBUG, "Memory configured in dual-channel assymetric mode.\n"); |
| 1257 | MCHBAR32(DCC_MCHBAR) &= ~DCC_INTERLEAVED; |
| 1258 | break; |
| 1259 | case CHANNEL_MODE_DUAL_INTERLEAVED: |
| 1260 | printk(BIOS_DEBUG, "Memory configured in dual-channel interleaved mode.\n"); |
| 1261 | MCHBAR32(DCC_MCHBAR) &= ~(DCC_NO_CHANXOR | (1 << 9)); |
| 1262 | MCHBAR32(DCC_MCHBAR) |= DCC_INTERLEAVED; |
| 1263 | break; |
| 1264 | } |
| 1265 | |
| 1266 | printk(BIOS_SPEW, "Memory map:\n" |
| 1267 | "TOM = %5uMB\n" |
| 1268 | "TOLUD = %5uMB\n" |
| 1269 | "TOUUD = %5uMB\n" |
| 1270 | "REMAP:\t base = %5uMB\n" |
Vladimir Serbinenko | 9907be4 | 2014-08-12 21:51:28 +0200 | [diff] [blame] | 1271 | "\t limit = %5uMB\n" |
| 1272 | "usedMEsize: %dMB\n", |
| 1273 | TOM, TOLUD, TOUUD, REMAPbase, REMAPlimit, usedMEsize); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1274 | } |
| 1275 | static void prejedec_memory_map(const dimminfo_t *const dimms, channel_mode_t mode) |
| 1276 | { |
| 1277 | /* Never use dual-interleaved mode in pre-jedec config. */ |
| 1278 | if (CHANNEL_MODE_DUAL_INTERLEAVED == mode) |
| 1279 | mode = CHANNEL_MODE_DUAL_ASYNC; |
| 1280 | |
| 1281 | program_memory_map(dimms, mode, 1); |
| 1282 | MCHBAR32(DCC_MCHBAR) |= DCC_NO_CHANXOR; |
| 1283 | } |
| 1284 | |
| 1285 | static void ddr3_select_clock_mux(const mem_clock_t ddr3clock, |
| 1286 | const dimminfo_t *const dimms, |
| 1287 | const stepping_t stepping) |
| 1288 | { |
| 1289 | const int clk1067 = (ddr3clock == MEM_CLOCK_1067MT); |
| 1290 | const int cardF[] = { CHANNEL_IS_CARDF(dimms, 0), CHANNEL_IS_CARDF(dimms, 1) }; |
| 1291 | |
| 1292 | int ch; |
| 1293 | |
| 1294 | if (stepping < STEPPING_B1) |
| 1295 | die("Stepping <B1 unsupported in clock-multiplexer selection.\n"); |
| 1296 | |
| 1297 | FOR_EACH_POPULATED_CHANNEL(dimms, ch) { |
| 1298 | int mixed = 0; |
| 1299 | if ((1 == ch) && (!CHANNEL_IS_POPULATED(dimms, 0) || (cardF[0] != cardF[1]))) |
| 1300 | mixed = 4 << 11; |
| 1301 | const unsigned int b = 0x14b0 + (ch * 0x0100); |
| 1302 | MCHBAR32(b+0x1c) = (MCHBAR32(b+0x1c) & ~(7 << 11)) | |
| 1303 | ((( cardF[ch])?1:0) << 11) | mixed; |
| 1304 | MCHBAR32(b+0x18) = (MCHBAR32(b+0x18) & ~(7 << 11)) | mixed; |
| 1305 | MCHBAR32(b+0x14) = (MCHBAR32(b+0x14) & ~(7 << 11)) | |
| 1306 | (((!clk1067 && !cardF[ch])?0:1) << 11) | mixed; |
| 1307 | MCHBAR32(b+0x10) = (MCHBAR32(b+0x10) & ~(7 << 11)) | |
| 1308 | ((( clk1067 && !cardF[ch])?1:0) << 11) | mixed; |
| 1309 | MCHBAR32(b+0x0c) = (MCHBAR32(b+0x0c) & ~(7 << 11)) | |
| 1310 | ((( cardF[ch])?3:2) << 11) | mixed; |
| 1311 | MCHBAR32(b+0x08) = (MCHBAR32(b+0x08) & ~(7 << 11)) | |
| 1312 | (2 << 11) | mixed; |
| 1313 | MCHBAR32(b+0x04) = (MCHBAR32(b+0x04) & ~(7 << 11)) | |
| 1314 | (((!clk1067 && !cardF[ch])?2:3) << 11) | mixed; |
| 1315 | MCHBAR32(b+0x00) = (MCHBAR32(b+0x00) & ~(7 << 11)) | |
| 1316 | ((( clk1067 && !cardF[ch])?3:2) << 11) | mixed; |
| 1317 | } |
| 1318 | } |
| 1319 | static void ddr3_write_io_init(const mem_clock_t ddr3clock, |
| 1320 | const dimminfo_t *const dimms, |
| 1321 | const stepping_t stepping, |
| 1322 | const int sff) |
| 1323 | { |
| 1324 | const int a1step = stepping >= STEPPING_CONVERSION_A1; |
| 1325 | const int cardF[] = { CHANNEL_IS_CARDF(dimms, 0), CHANNEL_IS_CARDF(dimms, 1) }; |
| 1326 | |
| 1327 | int ch; |
| 1328 | |
| 1329 | if (stepping < STEPPING_B1) |
| 1330 | die("Stepping <B1 unsupported in write i/o initialization.\n"); |
| 1331 | if (sff) |
| 1332 | die("SFF platform unsupported in write i/o initialization.\n"); |
| 1333 | |
| 1334 | static const u32 ddr3_667_800_by_stepping_ddr3_and_card[][2][2][4] = { |
| 1335 | { /* Stepping B3 and below */ |
| 1336 | { /* 667 MHz */ |
| 1337 | { 0xa3255008, 0x26888209, 0x26288208, 0x6188040f }, |
| 1338 | { 0x7524240b, 0xa5255608, 0x232b8508, 0x5528040f }, |
| 1339 | }, |
| 1340 | { /* 800 MHz */ |
| 1341 | { 0xa6255308, 0x26888209, 0x212b7508, 0x6188040f }, |
| 1342 | { 0x7524240b, 0xa6255708, 0x132b7508, 0x5528040f }, |
| 1343 | }, |
| 1344 | }, |
| 1345 | { /* Conversion stepping A1 and above */ |
| 1346 | { /* 667 MHz */ |
| 1347 | { 0xc5257208, 0x26888209, 0x26288208, 0x6188040f }, |
| 1348 | { 0x7524240b, 0xc5257608, 0x232b8508, 0x5528040f }, |
| 1349 | }, |
| 1350 | { /* 800 MHz */ |
| 1351 | { 0xb6256308, 0x26888209, 0x212b7508, 0x6188040f }, |
| 1352 | { 0x7524240b, 0xb6256708, 0x132b7508, 0x5528040f }, |
| 1353 | } |
| 1354 | }}; |
| 1355 | |
| 1356 | static const u32 ddr3_1067_by_channel_and_card[][2][4] = { |
| 1357 | { /* Channel A */ |
| 1358 | { 0xb2254708, 0x002b7408, 0x132b8008, 0x7228060f }, |
| 1359 | { 0xb0255008, 0xa4254108, 0x4528b409, 0x9428230f }, |
| 1360 | }, |
| 1361 | { /* Channel B */ |
| 1362 | { 0xa4254208, 0x022b6108, 0x132b8208, 0x9228210f }, |
| 1363 | { 0x6024140b, 0x92244408, 0x252ba409, 0x9328360c }, |
| 1364 | }, |
| 1365 | }; |
| 1366 | |
| 1367 | FOR_EACH_POPULATED_CHANNEL(dimms, ch) { |
| 1368 | if ((1 == ch) && CHANNEL_IS_POPULATED(dimms, 0) && (cardF[0] == cardF[1])) |
| 1369 | /* Only write if second channel population differs. */ |
| 1370 | continue; |
| 1371 | const u32 *const data = (ddr3clock != MEM_CLOCK_1067MT) |
| 1372 | ? ddr3_667_800_by_stepping_ddr3_and_card[a1step][2 - ddr3clock][cardF[ch]] |
| 1373 | : ddr3_1067_by_channel_and_card[ch][cardF[ch]]; |
| 1374 | MCHBAR32(CxWRTy_MCHBAR(ch, 0)) = data[0]; |
| 1375 | MCHBAR32(CxWRTy_MCHBAR(ch, 1)) = data[1]; |
| 1376 | MCHBAR32(CxWRTy_MCHBAR(ch, 2)) = data[2]; |
| 1377 | MCHBAR32(CxWRTy_MCHBAR(ch, 3)) = data[3]; |
| 1378 | } |
| 1379 | |
| 1380 | MCHBAR32(0x1490) = 0x00e70067; |
| 1381 | MCHBAR32(0x1494) = 0x000d8000; |
| 1382 | MCHBAR32(0x1590) = 0x00e70067; |
| 1383 | MCHBAR32(0x1594) = 0x000d8000; |
| 1384 | } |
| 1385 | static void ddr3_read_io_init(const mem_clock_t ddr3clock, |
| 1386 | const dimminfo_t *const dimms, |
| 1387 | const int sff) |
| 1388 | { |
| 1389 | int ch; |
| 1390 | |
| 1391 | FOR_EACH_POPULATED_CHANNEL(dimms, ch) { |
| 1392 | u32 addr, tmp; |
| 1393 | const unsigned int base = 0x14b0 + (ch * 0x0100); |
| 1394 | for (addr = base + 0x1c; addr >= base; addr -= 4) { |
| 1395 | tmp = MCHBAR32(addr); |
| 1396 | tmp &= ~((3 << 25) | (1 << 8) | (7 << 16) | (0xf << 20) | (1 << 27)); |
| 1397 | tmp |= (1 << 27); |
| 1398 | switch (ddr3clock) { |
| 1399 | case MEM_CLOCK_667MT: |
| 1400 | tmp |= (1 << 16) | (4 << 20); |
| 1401 | break; |
| 1402 | case MEM_CLOCK_800MT: |
| 1403 | tmp |= (2 << 16) | (3 << 20); |
| 1404 | break; |
| 1405 | case MEM_CLOCK_1067MT: |
| 1406 | if (!sff) |
| 1407 | tmp |= (2 << 16) | (1 << 20); |
| 1408 | else |
| 1409 | tmp |= (2 << 16) | (2 << 20); |
| 1410 | break; |
| 1411 | default: |
| 1412 | die("Wrong clock"); |
| 1413 | } |
| 1414 | MCHBAR32(addr) = tmp; |
| 1415 | } |
| 1416 | } |
| 1417 | } |
| 1418 | |
| 1419 | static void memory_io_init(const mem_clock_t ddr3clock, |
| 1420 | const dimminfo_t *const dimms, |
| 1421 | const stepping_t stepping, |
| 1422 | const int sff) |
| 1423 | { |
| 1424 | u32 tmp; |
| 1425 | |
| 1426 | if (stepping < STEPPING_B1) |
| 1427 | die("Stepping <B1 unsupported in " |
| 1428 | "system-memory i/o initialization.\n"); |
| 1429 | |
| 1430 | tmp = MCHBAR32(0x1400); |
| 1431 | tmp &= ~(3<<13); |
| 1432 | tmp |= (1<<9) | (1<<13); |
| 1433 | MCHBAR32(0x1400) = tmp; |
| 1434 | |
| 1435 | tmp = MCHBAR32(0x140c); |
| 1436 | tmp &= ~(0xff | (1<<11) | (1<<12) | |
| 1437 | (1<<16) | (1<<18) | (1<<27) | (0xf<<28)); |
| 1438 | tmp |= (1<<7) | (1<<11) | (1<<16); |
| 1439 | switch (ddr3clock) { |
| 1440 | case MEM_CLOCK_667MT: |
| 1441 | tmp |= 9 << 28; |
| 1442 | break; |
| 1443 | case MEM_CLOCK_800MT: |
| 1444 | tmp |= 7 << 28; |
| 1445 | break; |
| 1446 | case MEM_CLOCK_1067MT: |
| 1447 | tmp |= 8 << 28; |
| 1448 | break; |
| 1449 | } |
| 1450 | MCHBAR32(0x140c) = tmp; |
| 1451 | |
| 1452 | MCHBAR32(0x1440) &= ~1; |
| 1453 | |
| 1454 | tmp = MCHBAR32(0x1414); |
| 1455 | tmp &= ~((1<<20) | (7<<11) | (0xf << 24) | (0xf << 16)); |
| 1456 | tmp |= (3<<11); |
| 1457 | switch (ddr3clock) { |
| 1458 | case MEM_CLOCK_667MT: |
| 1459 | tmp |= (2 << 24) | (10 << 16); |
| 1460 | break; |
| 1461 | case MEM_CLOCK_800MT: |
| 1462 | tmp |= (3 << 24) | (7 << 16); |
| 1463 | break; |
| 1464 | case MEM_CLOCK_1067MT: |
| 1465 | tmp |= (4 << 24) | (4 << 16); |
| 1466 | break; |
| 1467 | } |
| 1468 | MCHBAR32(0x1414) = tmp; |
| 1469 | |
| 1470 | MCHBAR32(0x1418) &= ~((1<<3) | (1<<11) | (1<<19) | (1<<27)); |
| 1471 | |
| 1472 | MCHBAR32(0x141c) &= ~((1<<3) | (1<<11) | (1<<19) | (1<<27)); |
| 1473 | |
| 1474 | MCHBAR32(0x1428) |= 1<<14; |
| 1475 | |
| 1476 | tmp = MCHBAR32(0x142c); |
| 1477 | tmp &= ~((0xf << 8) | (0x7 << 20) | 0xf | (0xf << 24)); |
| 1478 | tmp |= (0x3 << 20) | (5 << 24); |
| 1479 | switch (ddr3clock) { |
| 1480 | case MEM_CLOCK_667MT: |
| 1481 | tmp |= (2 << 8) | 0xc; |
| 1482 | break; |
| 1483 | case MEM_CLOCK_800MT: |
| 1484 | tmp |= (3 << 8) | 0xa; |
| 1485 | break; |
| 1486 | case MEM_CLOCK_1067MT: |
| 1487 | tmp |= (4 << 8) | 0x7; |
| 1488 | break; |
| 1489 | } |
| 1490 | MCHBAR32(0x142c) = tmp; |
| 1491 | |
| 1492 | tmp = MCHBAR32(0x400); |
| 1493 | tmp &= ~((3 << 4) | (3 << 16) | (3 << 30)); |
| 1494 | tmp |= (2 << 4) | (2 << 16); |
| 1495 | MCHBAR32(0x400) = tmp; |
| 1496 | |
| 1497 | MCHBAR32(0x404) &= ~(0xf << 20); |
| 1498 | |
| 1499 | MCHBAR32(0x40c) &= ~(1 << 6); |
| 1500 | |
| 1501 | tmp = MCHBAR32(0x410); |
| 1502 | tmp &= ~(7 << 28); |
| 1503 | tmp |= 2 << 28; |
| 1504 | MCHBAR32(0x410) = tmp; |
| 1505 | |
| 1506 | tmp = MCHBAR32(0x41c); |
| 1507 | tmp &= ~0x77; |
| 1508 | tmp |= 0x11; |
| 1509 | MCHBAR32(0x41c) = tmp; |
| 1510 | |
| 1511 | ddr3_select_clock_mux(ddr3clock, dimms, stepping); |
| 1512 | |
| 1513 | ddr3_write_io_init(ddr3clock, dimms, stepping, sff); |
| 1514 | |
| 1515 | ddr3_read_io_init(ddr3clock, dimms, sff); |
| 1516 | } |
| 1517 | |
| 1518 | static void jedec_init(const timings_t *const timings, |
| 1519 | const dimminfo_t *const dimms) |
| 1520 | { |
| 1521 | if ((timings->tWR < 5) || (timings->tWR > 12)) |
| 1522 | die("tWR value unsupported in Jedec initialization.\n"); |
| 1523 | |
| 1524 | /* Pre-jedec settings */ |
| 1525 | MCHBAR32(0x40) |= (1 << 1); |
| 1526 | MCHBAR32(0x230) |= (3 << 1); |
| 1527 | MCHBAR32(0x238) |= (3 << 24); |
| 1528 | MCHBAR32(0x23c) |= (3 << 24); |
| 1529 | |
| 1530 | /* Normal write pointer operation */ |
| 1531 | MCHBAR32(0x14f0) |= (1 << 9); |
| 1532 | MCHBAR32(0x15f0) |= (1 << 9); |
| 1533 | |
| 1534 | MCHBAR32(DCC_MCHBAR) = (MCHBAR32(DCC_MCHBAR) & ~DCC_CMD_MASK) | DCC_CMD_NOP; |
| 1535 | |
| 1536 | u8 reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf0); |
| 1537 | pci_write_config8(PCI_DEV(0, 0, 0), 0xf0, reg8 & ~(1 << 2)); |
| 1538 | reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf0); |
| 1539 | pci_write_config8(PCI_DEV(0, 0, 0), 0xf0, reg8 | (1 << 2)); |
| 1540 | udelay(2); |
| 1541 | |
| 1542 | /* 5 6 7 8 9 10 11 12 */ |
| 1543 | static const u8 wr_lut[] = { 1, 2, 3, 4, 5, 5, 6, 6 }; |
| 1544 | |
| 1545 | const int WL = ((timings->tWL - 5) & 7) << 6; |
| 1546 | const int ODT_120OHMS = (1 << 9); |
| 1547 | const int ODS_34OHMS = (1 << 4); |
| 1548 | const int WR = (wr_lut[timings->tWR - 5] & 7) << 12; |
| 1549 | const int DLL1 = 1 << 11; |
| 1550 | const int CAS = ((timings->CAS - 4) & 7) << 7; |
| 1551 | const int INTERLEAVED = 1 << 6;/* This is READ Burst Type == interleaved. */ |
| 1552 | |
| 1553 | int ch, r; |
| 1554 | FOR_EACH_POPULATED_RANK(dimms, ch, r) { |
| 1555 | /* We won't do this in dual-interleaved mode, |
| 1556 | so don't care about the offset. */ |
| 1557 | const u32 rankaddr = raminit_get_rank_addr(ch, r); |
| 1558 | printk(BIOS_DEBUG, "Performing Jedec initialization at address 0x%08x.\n", rankaddr); |
| 1559 | MCHBAR32(DCC_MCHBAR) = (MCHBAR32(DCC_MCHBAR) & ~DCC_SET_EREG_MASK) | DCC_SET_EREGx(2); |
| 1560 | read32(rankaddr | WL); |
| 1561 | MCHBAR32(DCC_MCHBAR) = (MCHBAR32(DCC_MCHBAR) & ~DCC_SET_EREG_MASK) | DCC_SET_EREGx(3); |
| 1562 | read32(rankaddr); |
| 1563 | MCHBAR32(DCC_MCHBAR) = (MCHBAR32(DCC_MCHBAR) & ~DCC_SET_EREG_MASK) | DCC_SET_EREGx(1); |
| 1564 | read32(rankaddr | ODT_120OHMS | ODS_34OHMS); |
| 1565 | MCHBAR32(DCC_MCHBAR) = (MCHBAR32(DCC_MCHBAR) & ~DCC_CMD_MASK) | DCC_SET_MREG; |
| 1566 | read32(rankaddr | WR | DLL1 | CAS | INTERLEAVED); |
| 1567 | MCHBAR32(DCC_MCHBAR) = (MCHBAR32(DCC_MCHBAR) & ~DCC_CMD_MASK) | DCC_SET_MREG; |
| 1568 | read32(rankaddr | WR | CAS | INTERLEAVED); |
| 1569 | } |
| 1570 | } |
| 1571 | |
| 1572 | static void ddr3_calibrate_zq(void) { |
| 1573 | udelay(2); |
| 1574 | |
| 1575 | u32 tmp = MCHBAR32(DCC_MCHBAR); |
| 1576 | tmp &= ~(7 << 16); |
| 1577 | tmp |= (5 << 16); /* ZQ calibration mode */ |
| 1578 | MCHBAR32(DCC_MCHBAR) = tmp; |
| 1579 | |
| 1580 | MCHBAR32(CxDRT6_MCHBAR(0)) |= (1 << 3); |
| 1581 | MCHBAR32(CxDRT6_MCHBAR(1)) |= (1 << 3); |
| 1582 | |
| 1583 | udelay(1); |
| 1584 | |
| 1585 | MCHBAR32(CxDRT6_MCHBAR(0)) &= ~(1 << 3); |
| 1586 | MCHBAR32(CxDRT6_MCHBAR(1)) &= ~(1 << 3); |
| 1587 | |
| 1588 | MCHBAR32(DCC_MCHBAR) |= (7 << 16); /* Normal operation */ |
| 1589 | } |
| 1590 | |
| 1591 | static void post_jedec_sequence(const int cores) { |
| 1592 | const int quadcore = cores == 4; |
| 1593 | |
| 1594 | MCHBAR32(0x0040) &= ~(1 << 1); |
| 1595 | MCHBAR32(0x0230) &= ~(3 << 1); |
| 1596 | MCHBAR32(0x0230) |= 1 << 15; |
| 1597 | MCHBAR32(0x0230) &= ~(1 << 19); |
| 1598 | MCHBAR32(0x1250) = 0x6c4; |
| 1599 | MCHBAR32(0x1350) = 0x6c4; |
| 1600 | MCHBAR32(0x1254) = 0x871a066d; |
| 1601 | MCHBAR32(0x1354) = 0x871a066d; |
| 1602 | MCHBAR32(0x0238) |= 1 << 26; |
| 1603 | MCHBAR32(0x0238) &= ~(3 << 24); |
| 1604 | MCHBAR32(0x0238) |= 1 << 23; |
| 1605 | MCHBAR32(0x0238) = (MCHBAR32(0x238) & ~(7 << 20)) | (3 << 20); |
| 1606 | MCHBAR32(0x0238) = (MCHBAR32(0x238) & ~(7 << 17)) | (6 << 17); |
| 1607 | MCHBAR32(0x0238) = (MCHBAR32(0x238) & ~(7 << 14)) | (6 << 14); |
| 1608 | MCHBAR32(0x0238) = (MCHBAR32(0x238) & ~(7 << 11)) | (6 << 11); |
| 1609 | MCHBAR32(0x0238) = (MCHBAR32(0x238) & ~(7 << 8)) | (6 << 8); |
| 1610 | MCHBAR32(0x023c) &= ~(3 << 24); |
| 1611 | MCHBAR32(0x023c) &= ~(1 << 23); |
| 1612 | MCHBAR32(0x023c) = (MCHBAR32(0x23c) & ~(7 << 20)) | (3 << 20); |
| 1613 | MCHBAR32(0x023c) = (MCHBAR32(0x23c) & ~(7 << 17)) | (6 << 17); |
| 1614 | MCHBAR32(0x023c) = (MCHBAR32(0x23c) & ~(7 << 14)) | (6 << 14); |
| 1615 | MCHBAR32(0x023c) = (MCHBAR32(0x23c) & ~(7 << 11)) | (6 << 11); |
| 1616 | MCHBAR32(0x023c) = (MCHBAR32(0x23c) & ~(7 << 8)) | (6 << 8); |
| 1617 | |
| 1618 | if (quadcore) { |
| 1619 | MCHBAR32(0xb14) |= (0xbfbf << 16); |
| 1620 | } |
| 1621 | } |
| 1622 | |
| 1623 | static void dram_optimizations(const timings_t *const timings, |
| 1624 | const dimminfo_t *const dimms) |
| 1625 | { |
| 1626 | int ch; |
| 1627 | |
| 1628 | FOR_EACH_POPULATED_CHANNEL(dimms, ch) { |
| 1629 | const unsigned int mchbar = CxDRC1_MCHBAR(ch); |
| 1630 | u32 cxdrc1 = MCHBAR32(mchbar); |
| 1631 | cxdrc1 &= ~CxDRC1_SSDS_MASK; |
| 1632 | if (dimms[ch].ranks == 1) |
| 1633 | cxdrc1 |= CxDRC1_SS; |
| 1634 | else |
| 1635 | cxdrc1 |= CxDRC1_DS; |
| 1636 | MCHBAR32(mchbar) = cxdrc1; |
| 1637 | } |
| 1638 | } |
| 1639 | |
| 1640 | u32 raminit_get_rank_addr(unsigned int channel, unsigned int rank) |
| 1641 | { |
| 1642 | if (!channel && !rank) |
| 1643 | return 0; /* Address of first rank */ |
| 1644 | |
| 1645 | /* Read the bound of the previous rank. */ |
| 1646 | if (rank > 0) { |
| 1647 | rank--; |
| 1648 | } else { |
| 1649 | rank = 3; /* Highest rank per channel */ |
| 1650 | channel--; |
| 1651 | } |
| 1652 | const u32 reg = MCHBAR32(CxDRBy_MCHBAR(channel, rank)); |
| 1653 | /* Bound is in 32MB. */ |
| 1654 | return ((reg & CxDRBy_BOUND_MASK(rank)) >> CxDRBy_BOUND_SHIFT(rank)) << 25; |
| 1655 | } |
| 1656 | |
| 1657 | void raminit_reset_readwrite_pointers(void) { |
| 1658 | MCHBAR32(0x1234) |= (1 << 6); |
| 1659 | MCHBAR32(0x1234) &= ~(1 << 6); |
| 1660 | MCHBAR32(0x1334) |= (1 << 6); |
| 1661 | MCHBAR32(0x1334) &= ~(1 << 6); |
| 1662 | MCHBAR32(0x14f0) &= ~(1 << 9); |
| 1663 | MCHBAR32(0x14f0) |= (1 << 9); |
| 1664 | MCHBAR32(0x14f0) |= (1 << 10); |
| 1665 | MCHBAR32(0x15f0) &= ~(1 << 9); |
| 1666 | MCHBAR32(0x15f0) |= (1 << 9); |
| 1667 | MCHBAR32(0x15f0) |= (1 << 10); |
| 1668 | } |
| 1669 | |
| 1670 | void raminit(sysinfo_t *const sysinfo, const int s3resume) |
| 1671 | { |
| 1672 | const dimminfo_t *const dimms = sysinfo->dimms; |
| 1673 | const timings_t *const timings = &sysinfo->selected_timings; |
| 1674 | const int sff = sysinfo->gfx_type == GMCH_GS45; |
| 1675 | |
| 1676 | int ch; |
| 1677 | u8 reg8; |
| 1678 | |
| 1679 | |
| 1680 | /* Wait for some bit, maybe TXT clear. */ |
| 1681 | if (sysinfo->txt_enabled) { |
| 1682 | while (!(read8(0xfed40000) & (1 << 7))) {} |
| 1683 | } |
| 1684 | |
| 1685 | /* Enable SMBUS. */ |
| 1686 | enable_smbus(); |
| 1687 | |
| 1688 | /* Collect information about DIMMs and find common settings. */ |
| 1689 | collect_dimm_config(sysinfo); |
| 1690 | |
| 1691 | /* Check for bad warm boot. */ |
| 1692 | reset_on_bad_warmboot(); |
| 1693 | |
| 1694 | |
| 1695 | /***** From now on, program according to collected infos: *****/ |
| 1696 | |
| 1697 | /* Program DRAM type. */ |
| 1698 | switch (sysinfo->spd_type) { |
| 1699 | case DDR2: |
| 1700 | MCHBAR8(0x1434) |= (1 << 7); |
| 1701 | break; |
| 1702 | case DDR3: |
| 1703 | MCHBAR8(0x1434) |= (3 << 0); |
| 1704 | break; |
| 1705 | } |
| 1706 | |
| 1707 | /* Program system memory frequency. */ |
| 1708 | set_system_memory_frequency(timings); |
| 1709 | /* Program IGD memory frequency. */ |
| 1710 | set_igd_memory_frequencies(sysinfo); |
| 1711 | |
| 1712 | /* Configure DRAM control mode for populated channels. */ |
| 1713 | configure_dram_control_mode(timings, dimms); |
| 1714 | |
| 1715 | /* Initialize RCOMP. */ |
| 1716 | rcomp_initialization(sysinfo->stepping, sff); |
| 1717 | |
| 1718 | /* Power-up DRAM. */ |
| 1719 | dram_powerup(s3resume); |
| 1720 | /* Program DRAM timings. */ |
| 1721 | dram_program_timings(timings); |
| 1722 | /* Program number of banks. */ |
| 1723 | dram_program_banks(dimms); |
| 1724 | /* Enable DRAM clock pairs for populated DIMMs. */ |
| 1725 | FOR_EACH_POPULATED_CHANNEL(dimms, ch) |
| 1726 | MCHBAR32(CxDCLKDIS_MCHBAR(ch)) |= CxDCLKDIS_ENABLE; |
| 1727 | |
| 1728 | /* Enable On-Die Termination. */ |
| 1729 | odt_setup(timings, sff); |
| 1730 | /* Miscellaneous settings. */ |
| 1731 | misc_settings(timings, sysinfo->stepping); |
| 1732 | /* Program clock crossing registers. */ |
| 1733 | clock_crossing_setup(timings->fsb_clock, timings->mem_clock, dimms); |
| 1734 | /* Program egress VC1 timings. */ |
| 1735 | vc1_program_timings(timings->fsb_clock); |
| 1736 | /* Perform system-memory i/o initialization. */ |
| 1737 | memory_io_init(timings->mem_clock, dimms, sysinfo->stepping, sff); |
| 1738 | |
| 1739 | /* Initialize memory map with dummy values of 128MB per rank with a |
| 1740 | page size of 4KB. This makes the JEDEC initialization code easier. */ |
| 1741 | prejedec_memory_map(dimms, timings->channel_mode); |
| 1742 | if (!s3resume) |
| 1743 | /* Perform JEDEC initialization of DIMMS. */ |
| 1744 | jedec_init(timings, dimms); |
| 1745 | /* Some programming steps after JEDEC initialization. */ |
| 1746 | post_jedec_sequence(sysinfo->cores); |
| 1747 | |
| 1748 | /* Announce normal operation, initialization completed. */ |
| 1749 | MCHBAR32(DCC_MCHBAR) |= (0x7 << 16) | (0x1 << 19); |
| 1750 | reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf0); |
| 1751 | pci_write_config8(PCI_DEV(0, 0, 0), 0xf0, reg8 | (1 << 2)); |
| 1752 | reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf0); |
| 1753 | pci_write_config8(PCI_DEV(0, 0, 0), 0xf0, reg8 & ~(1 << 2)); |
| 1754 | |
| 1755 | |
| 1756 | /* Take a breath (the reader). */ |
| 1757 | |
| 1758 | |
| 1759 | /* Perform ZQ calibration for DDR3. */ |
| 1760 | ddr3_calibrate_zq(); |
| 1761 | |
| 1762 | /* Perform receive-enable calibration. */ |
| 1763 | raminit_receive_enable_calibration(timings, dimms); |
| 1764 | /* Lend clock values from receive-enable calibration. */ |
| 1765 | MCHBAR32(0x1224) = (MCHBAR32(0x1224) & ~(0xf0)) | |
| 1766 | ((((MCHBAR32(0x121c) >> 7) - 1) & 0xf) << 4); |
| 1767 | MCHBAR32(0x1324) = (MCHBAR32(0x1324) & ~(0xf0)) | |
| 1768 | ((((MCHBAR32(0x131c) >> 7) - 1) & 0xf) << 4); |
| 1769 | |
| 1770 | /* Perform read/write training for high clock rate. */ |
| 1771 | if (timings->mem_clock == MEM_CLOCK_1067MT) { |
| 1772 | raminit_read_training(dimms, s3resume); |
| 1773 | raminit_write_training(timings->mem_clock, dimms, s3resume); |
| 1774 | } |
| 1775 | |
| 1776 | /* Program final memory map (with real values). */ |
| 1777 | program_memory_map(dimms, timings->channel_mode, 0); |
| 1778 | |
| 1779 | /* Some last optimizations. */ |
| 1780 | dram_optimizations(timings, dimms); |
| 1781 | |
| 1782 | /* Mark raminit beeing finished. :-) */ |
| 1783 | u8 tmp8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2) & ~(1 << 7); |
| 1784 | pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, tmp8); |
| 1785 | } |